1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm = "",
16 list<dag> pattern = []> : Instruction {
17 field bit isRegisterLoad = 0;
18 field bit isRegisterStore = 0;
20 let Namespace = "AMDGPU";
21 let OutOperandList = outs;
22 let InOperandList = ins;
24 let Pattern = pattern;
25 let Itinerary = NullALU;
27 // SoftFail is a field the disassembler can use to provide a way for
28 // instructions to not match without killing the whole decode process. It is
29 // mainly used for ARM, but Tablegen expects this field to exist or it fails
30 // to build the decode table.
31 field bits<64> SoftFail = 0;
33 let DecoderNamespace = Namespace;
35 let TSFlags{63} = isRegisterLoad;
36 let TSFlags{62} = isRegisterStore;
39 class AMDGPUShaderInst <dag outs, dag ins, string asm = "",
40 list<dag> pattern = []> : AMDGPUInst<outs, ins, asm, pattern> {
42 field bits<32> Inst = 0xffffffff;
45 def FP16Denormals : Predicate<"Subtarget.hasFP16Denormals()">;
46 def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
47 def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
48 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
50 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
51 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
53 let OperandType = "OPERAND_IMMEDIATE" in {
55 def u32imm : Operand<i32> {
56 let PrintMethod = "printU32ImmOperand";
59 def u16imm : Operand<i16> {
60 let PrintMethod = "printU16ImmOperand";
63 def u8imm : Operand<i8> {
64 let PrintMethod = "printU8ImmOperand";
67 } // End OperandType = "OPERAND_IMMEDIATE"
69 //===--------------------------------------------------------------------===//
71 //===--------------------------------------------------------------------===//
72 def brtarget : Operand<OtherVT>;
74 //===----------------------------------------------------------------------===//
75 // PatLeafs for floating-point comparisons
76 //===----------------------------------------------------------------------===//
78 def COND_OEQ : PatLeaf <
80 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
83 def COND_ONE : PatLeaf <
85 [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
88 def COND_OGT : PatLeaf <
90 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
93 def COND_OGE : PatLeaf <
95 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
98 def COND_OLT : PatLeaf <
100 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
103 def COND_OLE : PatLeaf <
105 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
109 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
110 def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
112 //===----------------------------------------------------------------------===//
113 // PatLeafs for unsigned / unordered comparisons
114 //===----------------------------------------------------------------------===//
116 def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
117 def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
118 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
119 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
120 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
121 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
123 // XXX - For some reason R600 version is preferring to use unordered
125 def COND_UNE_NE : PatLeaf <
127 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
130 //===----------------------------------------------------------------------===//
131 // PatLeafs for signed comparisons
132 //===----------------------------------------------------------------------===//
134 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
135 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
136 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
137 def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
139 //===----------------------------------------------------------------------===//
140 // PatLeafs for integer equality
141 //===----------------------------------------------------------------------===//
143 def COND_EQ : PatLeaf <
145 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
148 def COND_NE : PatLeaf <
150 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
153 def COND_NULL : PatLeaf <
155 [{(void)N; return false;}]
159 //===----------------------------------------------------------------------===//
161 //===----------------------------------------------------------------------===//
163 class HasOneUseBinOp<SDPatternOperator op> : PatFrag<
164 (ops node:$src0, node:$src1),
166 [{ return N->hasOneUse(); }]
169 class HasOneUseTernaryOp<SDPatternOperator op> : PatFrag<
170 (ops node:$src0, node:$src1, node:$src2),
171 (op $src0, $src1, $src2),
172 [{ return N->hasOneUse(); }]
175 //===----------------------------------------------------------------------===//
176 // Load/Store Pattern Fragments
177 //===----------------------------------------------------------------------===//
179 class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
180 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
183 class PrivateLoad <SDPatternOperator op> : PrivateMemOp <
184 (ops node:$ptr), (op node:$ptr)
187 class PrivateStore <SDPatternOperator op> : PrivateMemOp <
188 (ops node:$value, node:$ptr), (op node:$value, node:$ptr)
191 def load_private : PrivateLoad <load>;
193 def truncstorei8_private : PrivateStore <truncstorei8>;
194 def truncstorei16_private : PrivateStore <truncstorei16>;
195 def store_private : PrivateStore <store>;
197 class GlobalMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
198 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
201 // Global address space loads
202 class GlobalLoad <SDPatternOperator op> : GlobalMemOp <
203 (ops node:$ptr), (op node:$ptr)
206 def global_load : GlobalLoad <load>;
208 // Global address space stores
209 class GlobalStore <SDPatternOperator op> : GlobalMemOp <
210 (ops node:$value, node:$ptr), (op node:$value, node:$ptr)
213 def global_store : GlobalStore <store>;
214 def global_store_atomic : GlobalStore<atomic_store>;
217 class ConstantMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
218 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
221 // Constant address space loads
222 class ConstantLoad <SDPatternOperator op> : ConstantMemOp <
223 (ops node:$ptr), (op node:$ptr)
226 def constant_load : ConstantLoad<load>;
228 class LocalMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
229 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
232 // Local address space loads
233 class LocalLoad <SDPatternOperator op> : LocalMemOp <
234 (ops node:$ptr), (op node:$ptr)
237 class LocalStore <SDPatternOperator op> : LocalMemOp <
238 (ops node:$value, node:$ptr), (op node:$value, node:$ptr)
241 class FlatMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
242 return cast<MemSDNode>(N)->getAddressSPace() == AMDGPUAS::FLAT_ADDRESS;
245 class FlatLoad <SDPatternOperator op> : FlatMemOp <
246 (ops node:$ptr), (op node:$ptr)
249 class AZExtLoadBase <SDPatternOperator ld_node>: PatFrag<(ops node:$ptr),
250 (ld_node node:$ptr), [{
251 LoadSDNode *L = cast<LoadSDNode>(N);
252 return L->getExtensionType() == ISD::ZEXTLOAD ||
253 L->getExtensionType() == ISD::EXTLOAD;
256 def az_extload : AZExtLoadBase <unindexedload>;
258 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
259 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
262 def az_extloadi8_global : GlobalLoad <az_extloadi8>;
263 def sextloadi8_global : GlobalLoad <sextloadi8>;
265 def az_extloadi8_constant : ConstantLoad <az_extloadi8>;
266 def sextloadi8_constant : ConstantLoad <sextloadi8>;
268 def az_extloadi8_local : LocalLoad <az_extloadi8>;
269 def sextloadi8_local : LocalLoad <sextloadi8>;
271 def extloadi8_private : PrivateLoad <az_extloadi8>;
272 def sextloadi8_private : PrivateLoad <sextloadi8>;
274 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
275 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
278 def az_extloadi16_global : GlobalLoad <az_extloadi16>;
279 def sextloadi16_global : GlobalLoad <sextloadi16>;
281 def az_extloadi16_constant : ConstantLoad <az_extloadi16>;
282 def sextloadi16_constant : ConstantLoad <sextloadi16>;
284 def az_extloadi16_local : LocalLoad <az_extloadi16>;
285 def sextloadi16_local : LocalLoad <sextloadi16>;
287 def extloadi16_private : PrivateLoad <az_extloadi16>;
288 def sextloadi16_private : PrivateLoad <sextloadi16>;
290 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
291 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
294 def az_extloadi32_global : GlobalLoad <az_extloadi32>;
296 def az_extloadi32_flat : FlatLoad <az_extloadi32>;
298 def az_extloadi32_constant : ConstantLoad <az_extloadi32>;
300 def truncstorei8_global : GlobalStore <truncstorei8>;
301 def truncstorei16_global : GlobalStore <truncstorei16>;
303 def local_store : LocalStore <store>;
304 def truncstorei8_local : LocalStore <truncstorei8>;
305 def truncstorei16_local : LocalStore <truncstorei16>;
307 def local_load : LocalLoad <load>;
309 class Aligned8Bytes <dag ops, dag frag> : PatFrag <ops, frag, [{
310 return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
313 def local_load_aligned8bytes : Aligned8Bytes <
314 (ops node:$ptr), (local_load node:$ptr)
317 def local_store_aligned8bytes : Aligned8Bytes <
318 (ops node:$val, node:$ptr), (local_store node:$val, node:$ptr)
321 class local_binary_atomic_op<SDNode atomic_op> :
322 PatFrag<(ops node:$ptr, node:$value),
323 (atomic_op node:$ptr, node:$value), [{
324 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
328 def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
329 def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
330 def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
331 def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
332 def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
333 def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
334 def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
335 def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
336 def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
337 def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
338 def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
340 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
341 (AMDGPUstore_mskor node:$val, node:$ptr), [{
342 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
345 multiclass AtomicCmpSwapLocal <SDNode cmp_swap_node> {
347 def _32_local : PatFrag <
348 (ops node:$ptr, node:$cmp, node:$swap),
349 (cmp_swap_node node:$ptr, node:$cmp, node:$swap), [{
350 AtomicSDNode *AN = cast<AtomicSDNode>(N);
351 return AN->getMemoryVT() == MVT::i32 &&
352 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
355 def _64_local : PatFrag<
356 (ops node:$ptr, node:$cmp, node:$swap),
357 (cmp_swap_node node:$ptr, node:$cmp, node:$swap), [{
358 AtomicSDNode *AN = cast<AtomicSDNode>(N);
359 return AN->getMemoryVT() == MVT::i64 &&
360 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
364 defm atomic_cmp_swap : AtomicCmpSwapLocal <atomic_cmp_swap>;
366 multiclass global_binary_atomic_op<SDNode atomic_op> {
368 (ops node:$ptr, node:$value),
369 (atomic_op node:$ptr, node:$value),
370 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;}]>;
372 def _noret : PatFrag<
373 (ops node:$ptr, node:$value),
374 (atomic_op node:$ptr, node:$value),
375 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>;
378 (ops node:$ptr, node:$value),
379 (atomic_op node:$ptr, node:$value),
380 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>;
383 defm atomic_swap_global : global_binary_atomic_op<atomic_swap>;
384 defm atomic_add_global : global_binary_atomic_op<atomic_load_add>;
385 defm atomic_and_global : global_binary_atomic_op<atomic_load_and>;
386 defm atomic_max_global : global_binary_atomic_op<atomic_load_max>;
387 defm atomic_min_global : global_binary_atomic_op<atomic_load_min>;
388 defm atomic_or_global : global_binary_atomic_op<atomic_load_or>;
389 defm atomic_sub_global : global_binary_atomic_op<atomic_load_sub>;
390 defm atomic_umax_global : global_binary_atomic_op<atomic_load_umax>;
391 defm atomic_umin_global : global_binary_atomic_op<atomic_load_umin>;
392 defm atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
395 def AMDGPUatomic_cmp_swap_global : PatFrag<
396 (ops node:$ptr, node:$value),
397 (AMDGPUatomic_cmp_swap node:$ptr, node:$value),
398 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;}]>;
400 def atomic_cmp_swap_global : PatFrag<
401 (ops node:$ptr, node:$cmp, node:$value),
402 (atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
403 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;}]>;
405 def atomic_cmp_swap_global_noret : PatFrag<
406 (ops node:$ptr, node:$cmp, node:$value),
407 (atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
408 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>;
410 def atomic_cmp_swap_global_ret : PatFrag<
411 (ops node:$ptr, node:$cmp, node:$value),
412 (atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
413 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>;
415 //===----------------------------------------------------------------------===//
416 // Misc Pattern Fragments
417 //===----------------------------------------------------------------------===//
420 int TWO_PI = 0x40c90fdb;
422 int TWO_PI_INV = 0x3e22f983;
423 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
424 int FP16_ONE = 0x3C00;
425 int FP32_ONE = 0x3f800000;
426 int FP32_NEG_ONE = 0xbf800000;
427 int FP64_ONE = 0x3ff0000000000000;
428 int FP64_NEG_ONE = 0xbff0000000000000;
430 def CONST : Constants;
432 def FP_ZERO : PatLeaf <
434 [{return N->getValueAPF().isZero();}]
437 def FP_ONE : PatLeaf <
439 [{return N->isExactlyValue(1.0);}]
442 def FP_HALF : PatLeaf <
444 [{return N->isExactlyValue(0.5);}]
447 let isCodeGenOnly = 1, isPseudo = 1 in {
449 let usesCustomInserter = 1 in {
451 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
455 [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
458 class FABS <RegisterClass rc> : AMDGPUShaderInst <
462 [(set f32:$dst, (fabs f32:$src0))]
465 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
469 [(set f32:$dst, (fneg f32:$src0))]
472 } // usesCustomInserter = 1
474 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
475 ComplexPattern addrPat> {
476 let UseNamedOperandTable = 1 in {
478 def RegisterLoad : AMDGPUShaderInst <
479 (outs dstClass:$dst),
480 (ins addrClass:$addr, i32imm:$chan),
481 "RegisterLoad $dst, $addr",
482 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
484 let isRegisterLoad = 1;
487 def RegisterStore : AMDGPUShaderInst <
489 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
490 "RegisterStore $val, $addr",
491 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
493 let isRegisterStore = 1;
498 } // End isCodeGenOnly = 1, isPseudo = 1
500 /* Generic helper patterns for intrinsics */
501 /* -------------------------------------- */
503 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
505 (fpow f32:$src0, f32:$src1),
506 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
509 /* Other helper patterns */
510 /* --------------------- */
512 /* Extract element pattern */
513 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
516 (sub_type (extractelt vec_type:$src, sub_idx)),
517 (EXTRACT_SUBREG $src, sub_reg)
520 /* Insert element pattern */
521 class Insert_Element <ValueType elem_type, ValueType vec_type,
522 int sub_idx, SubRegIndex sub_reg>
524 (insertelt vec_type:$vec, elem_type:$elem, sub_idx),
525 (INSERT_SUBREG $vec, $elem, sub_reg)
528 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
529 // can handle COPY instructions.
530 // bitconvert pattern
531 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
532 (dt (bitconvert (st rc:$src0))),
536 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
537 // can handle COPY instructions.
538 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
539 (vt (AMDGPUdwordaddr (vt rc:$addr))),
545 multiclass BFIPatterns <Instruction BFI_INT,
546 Instruction LoadImm32,
547 RegisterClass RC64> {
548 // Definition from ISA doc:
549 // (y & x) | (z & ~x)
551 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
555 // SHA-256 Ch function
558 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
563 (fcopysign f32:$src0, f32:$src1),
564 (BFI_INT (LoadImm32 (i32 0x7fffffff)), $src0, $src1)
568 (f64 (fcopysign f64:$src0, f64:$src1)),
570 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
571 (BFI_INT (LoadImm32 (i32 0x7fffffff)),
572 (i32 (EXTRACT_SUBREG $src0, sub1)),
573 (i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
577 (f64 (fcopysign f64:$src0, f32:$src1)),
579 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
580 (BFI_INT (LoadImm32 (i32 0x7fffffff)),
581 (i32 (EXTRACT_SUBREG $src0, sub1)),
586 // SHA-256 Ma patterns
588 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
589 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
590 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
591 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
594 // Bitfield extract patterns
596 def IMMZeroBasedBitfieldMask : PatLeaf <(imm), [{
597 return isMask_32(N->getZExtValue());
600 def IMMPopCount : SDNodeXForm<imm, [{
601 return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N),
605 class BFEPattern <Instruction BFE, Instruction MOV> : Pat <
606 (i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)),
607 (BFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
611 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
612 (rotr i32:$src0, i32:$src1),
613 (BIT_ALIGN $src0, $src0, $src1)
616 // This matches 16 permutations of
617 // max(min(x, y), min(max(x, y), z))
618 class IntMed3Pat<Instruction med3Inst,
619 SDPatternOperator max,
620 SDPatternOperator max_oneuse,
621 SDPatternOperator min_oneuse> : Pat<
622 (max (min_oneuse i32:$src0, i32:$src1),
623 (min_oneuse (max_oneuse i32:$src0, i32:$src1), i32:$src2)),
624 (med3Inst $src0, $src1, $src2)
627 let Properties = [SDNPCommutative, SDNPAssociative] in {
628 def smax_oneuse : HasOneUseBinOp<smax>;
629 def smin_oneuse : HasOneUseBinOp<smin>;
630 def umax_oneuse : HasOneUseBinOp<umax>;
631 def umin_oneuse : HasOneUseBinOp<umin>;
632 def sub_oneuse : HasOneUseBinOp<sub>;
633 } // Properties = [SDNPCommutative, SDNPAssociative]
635 def select_oneuse : HasOneUseTernaryOp<select>;
637 // Special conversion patterns
639 def cvt_rpi_i32_f32 : PatFrag <
641 (fp_to_sint (ffloor (fadd $src, FP_HALF))),
642 [{ (void) N; return TM.Options.NoNaNsFPMath; }]
645 def cvt_flr_i32_f32 : PatFrag <
647 (fp_to_sint (ffloor $src)),
648 [{ (void)N; return TM.Options.NoNaNsFPMath; }]
651 class IMad24Pat<Instruction Inst> : Pat <
652 (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
653 (Inst $src0, $src1, $src2)
656 class UMad24Pat<Instruction Inst> : Pat <
657 (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
658 (Inst $src0, $src1, $src2)
661 class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
662 (fdiv FP_ONE, vt:$src),
666 class RsqPat<Instruction RsqInst, ValueType vt> : Pat <
667 (AMDGPUrcp (fsqrt vt:$src)),
671 include "R600Instructions.td"
672 include "R700Instructions.td"
673 include "EvergreenInstructions.td"
674 include "CaymanInstructions.td"
676 include "SIInstrInfo.td"