1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
13 //===----------------------------------------------------------------------===//
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "InstPrinter/AMDGPUInstPrinter.h"
21 #include "SIInstrInfo.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCObjectStreamer.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/Format.h"
39 #include "AMDGPUGenMCPseudoLowering.inc"
41 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st,
42 const AsmPrinter &ap):
43 Ctx(ctx), ST(st), AP(ap) { }
45 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
48 return MCSymbolRefExpr::VK_None;
49 case SIInstrInfo::MO_GOTPCREL:
50 return MCSymbolRefExpr::VK_GOTPCREL;
51 case SIInstrInfo::MO_GOTPCREL32_LO:
52 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
53 case SIInstrInfo::MO_GOTPCREL32_HI:
54 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
55 case SIInstrInfo::MO_REL32_LO:
56 return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
57 case SIInstrInfo::MO_REL32_HI:
58 return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
62 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
63 const MachineBasicBlock &SrcBB,
64 const MachineOperand &MO) const {
65 const MCExpr *DestBBSym
66 = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
67 const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
69 assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
70 ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
72 // s_getpc_b64 returns the address of next instruction.
73 const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
74 SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
76 if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
77 return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
79 assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
80 return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
83 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
84 MCOperand &MCOp) const {
85 switch (MO.getType()) {
87 llvm_unreachable("unknown operand type");
88 case MachineOperand::MO_Immediate:
89 MCOp = MCOperand::createImm(MO.getImm());
91 case MachineOperand::MO_Register:
92 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
94 case MachineOperand::MO_MachineBasicBlock: {
95 if (MO.getTargetFlags() != 0) {
96 MCOp = MCOperand::createExpr(
97 getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
99 MCOp = MCOperand::createExpr(
100 MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
105 case MachineOperand::MO_GlobalAddress: {
106 const GlobalValue *GV = MO.getGlobal();
107 SmallString<128> SymbolName;
108 AP.getNameWithPrefix(SymbolName, GV);
109 MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
110 const MCExpr *SymExpr =
111 MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
112 const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
113 MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
114 MCOp = MCOperand::createExpr(Expr);
117 case MachineOperand::MO_ExternalSymbol: {
118 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
119 Sym->setExternal(true);
120 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
121 MCOp = MCOperand::createExpr(Expr);
124 case MachineOperand::MO_RegisterMask:
125 // Regmasks are like implicit defs.
130 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
131 unsigned Opcode = MI->getOpcode();
132 const auto *TII = ST.getInstrInfo();
134 // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
135 // need to select it to the subtarget specific version, and there's no way to
136 // do that with a single pseudo source operation.
137 if (Opcode == AMDGPU::S_SETPC_B64_return)
138 Opcode = AMDGPU::S_SETPC_B64;
139 else if (Opcode == AMDGPU::SI_CALL) {
140 // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
141 // called function (which we need to remove here).
142 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
144 lowerOperand(MI->getOperand(0), Dest);
145 lowerOperand(MI->getOperand(1), Src);
146 OutMI.addOperand(Dest);
147 OutMI.addOperand(Src);
149 } else if (Opcode == AMDGPU::SI_TCRETURN) {
150 // TODO: How to use branch immediate and avoid register+add?
151 Opcode = AMDGPU::S_SETPC_B64;
154 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
155 if (MCOpcode == -1) {
156 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
157 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
158 "a target-specific version: " + Twine(MI->getOpcode()));
161 OutMI.setOpcode(MCOpcode);
163 for (const MachineOperand &MO : MI->explicit_operands()) {
165 lowerOperand(MO, MCOp);
166 OutMI.addOperand(MCOp);
170 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
171 MCOperand &MCOp) const {
172 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
173 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
174 return MCInstLowering.lowerOperand(MO, MCOp);
177 const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
178 // TargetMachine does not support llvm-style cast. Use C++-style cast.
179 // This is safe since TM is always of type AMDGPUTargetMachine or its
181 auto *AT = static_cast<AMDGPUTargetMachine*>(&TM);
182 auto *CE = dyn_cast<ConstantExpr>(CV);
184 // Lower null pointers in private and local address space.
185 // Clang generates addrspacecast for null pointers in private and local
186 // address space, which needs to be lowered.
187 if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
188 auto Op = CE->getOperand(0);
189 auto SrcAddr = Op->getType()->getPointerAddressSpace();
190 if (Op->isNullValue() && AT->getNullPointerValue(SrcAddr) == 0) {
191 auto DstAddr = CE->getType()->getPointerAddressSpace();
192 return MCConstantExpr::create(AT->getNullPointerValue(DstAddr),
196 return AsmPrinter::lowerConstant(CV);
199 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
200 if (emitPseudoExpansionLowering(*OutStreamer, MI))
203 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
204 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
207 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
208 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
209 C.emitError("Illegal instruction detected: " + Err);
213 if (MI->isBundle()) {
214 const MachineBasicBlock *MBB = MI->getParent();
215 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
216 while (I != MBB->instr_end() && I->isInsideBundle()) {
217 EmitInstruction(&*I);
221 // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
222 // placeholder terminator instructions and should only be printed as
224 if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
226 SmallVector<char, 16> BBStr;
227 raw_svector_ostream Str(BBStr);
229 const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
230 const MCSymbolRefExpr *Expr
231 = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
232 Expr->print(Str, MAI);
233 OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
239 if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
241 OutStreamer->emitRawComment(" return to shader part epilog");
245 if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
247 OutStreamer->emitRawComment(" wave barrier");
251 if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
253 OutStreamer->emitRawComment(" divergent unreachable");
258 MCInstLowering.lower(MI, TmpInst);
259 EmitToStreamer(*OutStreamer, TmpInst);
261 if (STI.dumpCode()) {
262 // Disassemble instruction/operands to text.
263 DisasmLines.resize(DisasmLines.size() + 1);
264 std::string &DisasmLine = DisasmLines.back();
265 raw_string_ostream DisasmStream(DisasmLine);
267 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
269 *STI.getRegisterInfo());
270 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
272 // Disassemble instruction/operands to hex representation.
273 SmallVector<MCFixup, 4> Fixups;
274 SmallVector<char, 16> CodeBytes;
275 raw_svector_ostream CodeStream(CodeBytes);
277 auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
278 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
279 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
280 MF->getSubtarget<MCSubtargetInfo>());
281 HexLines.resize(HexLines.size() + 1);
282 std::string &HexLine = HexLines.back();
283 raw_string_ostream HexStream(HexLine);
285 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
286 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
287 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
290 DisasmStream.flush();
291 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());