1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
13 //===----------------------------------------------------------------------===//
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "InstPrinter/AMDGPUInstPrinter.h"
21 #include "SIInstrInfo.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCObjectStreamer.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/Format.h"
39 #include "AMDGPUGenMCPseudoLowering.inc"
41 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st,
42 const AsmPrinter &ap):
43 Ctx(ctx), ST(st), AP(ap) { }
45 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
48 return MCSymbolRefExpr::VK_None;
49 case SIInstrInfo::MO_GOTPCREL:
50 return MCSymbolRefExpr::VK_GOTPCREL;
51 case SIInstrInfo::MO_GOTPCREL32_LO:
52 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
53 case SIInstrInfo::MO_GOTPCREL32_HI:
54 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
55 case SIInstrInfo::MO_REL32_LO:
56 return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
57 case SIInstrInfo::MO_REL32_HI:
58 return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
62 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
63 const MachineBasicBlock &SrcBB,
64 const MachineOperand &MO) const {
65 const MCExpr *DestBBSym
66 = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
67 const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
69 assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
70 ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
72 // s_getpc_b64 returns the address of next instruction.
73 const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
74 SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
76 if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
77 return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
79 assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
80 return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
83 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
84 MCOperand &MCOp) const {
85 switch (MO.getType()) {
87 llvm_unreachable("unknown operand type");
88 case MachineOperand::MO_Immediate:
89 MCOp = MCOperand::createImm(MO.getImm());
91 case MachineOperand::MO_Register:
92 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
94 case MachineOperand::MO_MachineBasicBlock: {
95 if (MO.getTargetFlags() != 0) {
96 MCOp = MCOperand::createExpr(
97 getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
99 MCOp = MCOperand::createExpr(
100 MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
105 case MachineOperand::MO_GlobalAddress: {
106 const GlobalValue *GV = MO.getGlobal();
107 SmallString<128> SymbolName;
108 AP.getNameWithPrefix(SymbolName, GV);
109 MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
110 const MCExpr *SymExpr =
111 MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
112 const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
113 MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
114 MCOp = MCOperand::createExpr(Expr);
117 case MachineOperand::MO_ExternalSymbol: {
118 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
119 Sym->setExternal(true);
120 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
121 MCOp = MCOperand::createExpr(Expr);
127 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
128 unsigned Opcode = MI->getOpcode();
130 // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
131 // need to select it to the subtarget specific version, and there's no way to
132 // do that with a single pseudo source operation.
133 if (Opcode == AMDGPU::S_SETPC_B64_return)
134 Opcode = AMDGPU::S_SETPC_B64;
136 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(Opcode);
137 if (MCOpcode == -1) {
138 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
139 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
140 "a target-specific version: " + Twine(MI->getOpcode()));
143 OutMI.setOpcode(MCOpcode);
145 for (const MachineOperand &MO : MI->explicit_operands()) {
147 lowerOperand(MO, MCOp);
148 OutMI.addOperand(MCOp);
152 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
153 MCOperand &MCOp) const {
154 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
155 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
156 return MCInstLowering.lowerOperand(MO, MCOp);
159 const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
160 // TargetMachine does not support llvm-style cast. Use C++-style cast.
161 // This is safe since TM is always of type AMDGPUTargetMachine or its
163 auto *AT = static_cast<AMDGPUTargetMachine*>(&TM);
164 auto *CE = dyn_cast<ConstantExpr>(CV);
166 // Lower null pointers in private and local address space.
167 // Clang generates addrspacecast for null pointers in private and local
168 // address space, which needs to be lowered.
169 if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
170 auto Op = CE->getOperand(0);
171 auto SrcAddr = Op->getType()->getPointerAddressSpace();
172 if (Op->isNullValue() && AT->getNullPointerValue(SrcAddr) == 0) {
173 auto DstAddr = CE->getType()->getPointerAddressSpace();
174 return MCConstantExpr::create(AT->getNullPointerValue(DstAddr),
178 return AsmPrinter::lowerConstant(CV);
181 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
182 if (emitPseudoExpansionLowering(*OutStreamer, MI))
185 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
186 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
189 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
190 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
191 C.emitError("Illegal instruction detected: " + Err);
195 if (MI->isBundle()) {
196 const MachineBasicBlock *MBB = MI->getParent();
197 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
198 while (I != MBB->instr_end() && I->isInsideBundle()) {
199 EmitInstruction(&*I);
203 // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
204 // placeholder terminator instructions and should only be printed as
206 if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
208 SmallVector<char, 16> BBStr;
209 raw_svector_ostream Str(BBStr);
211 const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
212 const MCSymbolRefExpr *Expr
213 = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
214 Expr->print(Str, MAI);
215 OutStreamer->emitRawComment(" mask branch " + BBStr);
221 if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
223 OutStreamer->emitRawComment(" return to shader part epilog");
227 if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
229 OutStreamer->emitRawComment(" wave barrier");
233 if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
235 OutStreamer->emitRawComment(" divergent unreachable");
240 MCInstLowering.lower(MI, TmpInst);
241 EmitToStreamer(*OutStreamer, TmpInst);
243 if (STI.dumpCode()) {
244 // Disassemble instruction/operands to text.
245 DisasmLines.resize(DisasmLines.size() + 1);
246 std::string &DisasmLine = DisasmLines.back();
247 raw_string_ostream DisasmStream(DisasmLine);
249 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
251 *STI.getRegisterInfo());
252 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
254 // Disassemble instruction/operands to hex representation.
255 SmallVector<MCFixup, 4> Fixups;
256 SmallVector<char, 16> CodeBytes;
257 raw_svector_ostream CodeStream(CodeBytes);
259 auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
260 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
261 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
262 MF->getSubtarget<MCSubtargetInfo>());
263 HexLines.resize(HexLines.size() + 1);
264 std::string &HexLine = HexLines.back();
265 raw_string_ostream HexStream(HexLine);
267 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
268 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
269 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
272 DisasmStream.flush();
273 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());