1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
22 class TargetRegisterInfo;
30 } // End AMDGPU namespace.
32 /// This class provides the information for the target register banks.
33 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
37 #define GET_TARGET_REGBANK_CLASS
38 #include "AMDGPUGenRegisterBank.inc"
40 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
41 const SIRegisterInfo *TRI;
43 /// See RegisterBankInfo::applyMapping.
44 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
46 const RegisterBankInfo::InstructionMapping &
47 getInstrMappingForLoad(const MachineInstr &MI) const;
50 AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
52 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
53 unsigned Size) const override;
56 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
59 getInstrAlternativeMappings(const MachineInstr &MI) const override;
61 const InstructionMapping &
62 getInstrMapping(const MachineInstr &MI) const override;
64 } // End llvm namespace.