1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
22 class TargetRegisterInfo;
30 } // End AMDGPU namespace.
32 /// This class provides the information for the target register banks.
33 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
37 #define GET_TARGET_REGBANK_CLASS
38 #include "AMDGPUGenRegisterBank.inc"
41 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
42 const SIRegisterInfo *TRI;
44 /// See RegisterBankInfo::applyMapping.
45 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
47 const RegisterBankInfo::InstructionMapping &
48 getInstrMappingForLoad(const MachineInstr &MI) const;
51 AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
53 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
54 unsigned Size) const override;
57 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
60 getInstrAlternativeMappings(const MachineInstr &MI) const override;
62 const InstructionMapping &
63 getInstrMapping(const MachineInstr &MI) const override;
65 } // End llvm namespace.