1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
19 #define GET_REGBANK_DECLARATIONS
20 #include "AMDGPUGenRegisterBank.inc"
21 #undef GET_REGBANK_DECLARATIONS
26 class TargetRegisterInfo;
28 /// This class provides the information for the target register banks.
29 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
33 #define GET_TARGET_REGBANK_CLASS
34 #include "AMDGPUGenRegisterBank.inc"
36 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
37 const SIRegisterInfo *TRI;
39 /// See RegisterBankInfo::applyMapping.
40 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
42 const RegisterBankInfo::InstructionMapping &
43 getInstrMappingForLoad(const MachineInstr &MI) const;
45 unsigned getRegBankID(unsigned Reg, const MachineRegisterInfo &MRI,
46 const TargetRegisterInfo &TRI,
47 unsigned Default = AMDGPU::VGPRRegBankID) const;
49 bool isSALUMapping(const MachineInstr &MI) const;
50 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
51 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
52 const InstructionMapping &getDefaultMappingAllVGPR(
53 const MachineInstr &MI) const;
55 AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
57 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
58 unsigned Size) const override;
61 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
64 getInstrAlternativeMappings(const MachineInstr &MI) const override;
66 const InstructionMapping &
67 getInstrMapping(const MachineInstr &MI) const override;
69 } // End llvm namespace.