1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "AMDGPUCallLowering.h"
20 #include "R600FrameLowering.h"
21 #include "R600ISelLowering.h"
22 #include "R600InstrInfo.h"
23 #include "SIFrameLowering.h"
24 #include "SIISelLowering.h"
25 #include "SIInstrInfo.h"
26 #include "Utils/AMDGPUBaseInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
29 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
30 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
33 #include "llvm/MC/MCInstrItineraries.h"
34 #include "llvm/Support/MathExtras.h"
40 #define GET_SUBTARGETINFO_HEADER
41 #include "AMDGPUGenSubtargetInfo.inc"
42 #define GET_SUBTARGETINFO_HEADER
43 #include "R600GenSubtargetInfo.inc"
49 class AMDGPUSubtarget {
66 const FeatureBitset &SubtargetFeatureBits;
75 bool HasFminFmaxLegacy;
76 bool EnablePromoteAlloca;
78 unsigned WavefrontSize;
81 AMDGPUSubtarget(const Triple &TT, const FeatureBitset &FeatureBits);
83 static const AMDGPUSubtarget &get(const MachineFunction &MF);
84 static const AMDGPUSubtarget &get(const TargetMachine &TM,
87 /// \returns Default range flat work group size for a calling convention.
88 std::pair<unsigned, unsigned> getDefaultFlatWorkGroupSize(CallingConv::ID CC) const;
90 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
91 /// for function \p F, or minimum/maximum flat work group sizes explicitly
92 /// requested using "amdgpu-flat-work-group-size" attribute attached to
95 /// \returns Subtarget's default values if explicitly requested values cannot
96 /// be converted to integer, or violate subtarget's specifications.
97 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
99 /// \returns Subtarget's default pair of minimum/maximum number of waves per
100 /// execution unit for function \p F, or minimum/maximum number of waves per
101 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
102 /// attached to function \p F.
104 /// \returns Subtarget's default values if explicitly requested values cannot
105 /// be converted to integer, violate subtarget's specifications, or are not
106 /// compatible with minimum/maximum number of waves limited by flat work group
107 /// size, register usage, and/or lds usage.
108 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
110 /// Return the amount of LDS that can be used that will not restrict the
111 /// occupancy lower than WaveCount.
112 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
113 const Function &) const;
115 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
116 /// the given LDS memory size is the only constraint.
117 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
119 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const;
121 bool isAmdHsaOS() const {
122 return TargetTriple.getOS() == Triple::AMDHSA;
125 bool isAmdPalOS() const {
126 return TargetTriple.getOS() == Triple::AMDPAL;
129 bool isMesa3DOS() const {
130 return TargetTriple.getOS() == Triple::Mesa3D;
133 bool isMesaKernel(const Function &F) const {
134 return isMesa3DOS() && !AMDGPU::isShader(F.getCallingConv());
137 bool isAmdCodeObjectV2(const Function &F) const {
138 return isAmdHsaOS() || isMesaKernel(F);
141 bool has16BitInsts() const {
142 return Has16BitInsts;
145 bool hasMadMixInsts() const {
146 return HasMadMixInsts;
149 bool hasFP32Denormals() const {
150 return FP32Denormals;
153 bool hasFPExceptions() const {
157 bool hasSDWA() const {
161 bool hasVOP3PInsts() const {
162 return HasVOP3PInsts;
165 bool hasMulI24() const {
169 bool hasMulU24() const {
173 bool hasFminFmaxLegacy() const {
174 return HasFminFmaxLegacy;
177 bool isPromoteAllocaEnabled() const {
178 return EnablePromoteAlloca;
181 unsigned getWavefrontSize() const {
182 return WavefrontSize;
185 int getLocalMemorySize() const {
186 return LocalMemorySize;
189 unsigned getAlignmentForImplicitArgPtr() const {
190 return isAmdHsaOS() ? 8 : 4;
193 /// Returns the offset in bytes from the start of the input buffer
194 /// of the first explicit kernel argument.
195 unsigned getExplicitKernelArgOffset(const Function &F) const {
196 return isAmdCodeObjectV2(F) ? 0 : 36;
199 /// \returns Maximum number of work groups per compute unit supported by the
200 /// subtarget and limited by given \p FlatWorkGroupSize.
201 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
202 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(SubtargetFeatureBits,
206 /// \returns Minimum flat work group size supported by the subtarget.
207 unsigned getMinFlatWorkGroupSize() const {
208 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(SubtargetFeatureBits);
211 /// \returns Maximum flat work group size supported by the subtarget.
212 unsigned getMaxFlatWorkGroupSize() const {
213 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(SubtargetFeatureBits);
216 /// \returns Maximum number of waves per execution unit supported by the
217 /// subtarget and limited by given \p FlatWorkGroupSize.
218 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
219 return AMDGPU::IsaInfo::getMaxWavesPerEU(SubtargetFeatureBits,
223 /// \returns Minimum number of waves per execution unit supported by the
225 unsigned getMinWavesPerEU() const {
226 return AMDGPU::IsaInfo::getMinWavesPerEU(SubtargetFeatureBits);
229 unsigned getMaxWavesPerEU() const { return 10; }
231 /// Creates value range metadata on an workitemid.* inrinsic call or load.
232 bool makeLIDRangeMetadata(Instruction *I) const;
234 /// \returns Number of bytes of arguments that are passed to a shader or
235 /// kernel in addition to the explicit ones declared for the function.
236 unsigned getImplicitArgNumBytes(const Function &F) const {
239 return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0);
241 uint64_t getExplicitKernArgSize(const Function &F,
242 unsigned &MaxAlign) const;
243 unsigned getKernArgSegmentSize(const Function &F,
244 unsigned &MaxAlign) const;
246 virtual ~AMDGPUSubtarget() {}
249 class GCNSubtarget : public AMDGPUGenSubtargetInfo,
250 public AMDGPUSubtarget {
271 enum TrapHandlerAbi {
272 TrapHandlerAbiNone = 0,
273 TrapHandlerAbiHsa = 1
277 TrapIDHardwareReserved = 0,
278 TrapIDHSADebugTrap = 1,
280 TrapIDLLVMDebugTrap = 3,
281 TrapIDDebugBreakpoint = 7,
282 TrapIDDebugReserved8 = 8,
283 TrapIDDebugReservedFE = 0xfe,
284 TrapIDDebugReservedFF = 0xff
288 LLVMTrapHandlerRegValue = 1
292 /// GlobalISel related APIs.
293 std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
294 std::unique_ptr<InstructionSelector> InstSelector;
295 std::unique_ptr<LegalizerInfo> Legalizer;
296 std::unique_ptr<RegisterBankInfo> RegBankInfo;
299 // Basic subtarget description.
304 unsigned MaxPrivateElementSize;
306 // Possibly statically set by tablegen, but may want to be overridden.
310 // Dynamially set bits that enable features.
311 bool FP64FP16Denormals;
314 bool AutoWaitcntBeforeBarrier;
316 bool UnalignedScratchAccess;
317 bool UnalignedBufferAccess;
318 bool HasApertureRegs;
321 bool DebuggerInsertNops;
322 bool DebuggerEmitPrologue;
325 bool EnableHugePrivateBuffer;
326 bool EnableVGPRSpilling;
327 bool EnableLoadStoreOpt;
328 bool EnableUnsafeDSOffsetFolding;
329 bool EnableSIScheduler;
333 // Subtarget statically properties set by tablegen
342 bool HasSMemRealTime;
346 bool HasVGPRIndexMode;
347 bool HasScalarStores;
348 bool HasScalarAtomics;
349 bool HasInv2PiInlineImm;
354 bool HasSDWAOutModsVOPC;
357 bool D16PreservesUnusedBits;
358 bool FlatAddressSpace;
359 bool FlatInstOffsets;
360 bool FlatGlobalInsts;
361 bool FlatScratchInsts;
362 bool AddNoCarryInsts;
363 bool HasUnpackedD16VMem;
368 short TexVTXClauseSize;
369 bool ScalarizeGlobal;
371 // Dummy feature to use for assembler in tablegen.
374 SelectionDAGTargetInfo TSInfo;
377 SIInstrInfo InstrInfo;
378 SITargetLowering TLInfo;
379 SIFrameLowering FrameLowering;
382 GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
383 const GCNTargetMachine &TM);
384 ~GCNSubtarget() override;
386 GCNSubtarget &initializeSubtargetDependencies(const Triple &TT,
387 StringRef GPU, StringRef FS);
389 const SIInstrInfo *getInstrInfo() const override {
393 const SIFrameLowering *getFrameLowering() const override {
394 return &FrameLowering;
397 const SITargetLowering *getTargetLowering() const override {
401 const SIRegisterInfo *getRegisterInfo() const override {
402 return &InstrInfo.getRegisterInfo();
405 const CallLowering *getCallLowering() const override {
406 return CallLoweringInfo.get();
409 const InstructionSelector *getInstructionSelector() const override {
410 return InstSelector.get();
413 const LegalizerInfo *getLegalizerInfo() const override {
414 return Legalizer.get();
417 const RegisterBankInfo *getRegBankInfo() const override {
418 return RegBankInfo.get();
421 // Nothing implemented, just prevent crashes on use.
422 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
426 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
428 Generation getGeneration() const {
429 return (Generation)Gen;
432 unsigned getWavefrontSizeLog2() const {
433 return Log2_32(WavefrontSize);
436 int getLDSBankCount() const {
440 unsigned getMaxPrivateElementSize() const {
441 return MaxPrivateElementSize;
444 AMDGPUAS getAMDGPUAS() const {
448 bool hasIntClamp() const {
452 bool hasFP64() const {
456 bool hasMIMG_R128() const {
460 bool hasHWFP64() const {
464 bool hasFastFMAF32() const {
468 bool hasHalfRate64Ops() const {
469 return HalfRate64Ops;
472 bool hasAddr64() const {
473 return (getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS);
476 bool hasBFE() const {
480 bool hasBFI() const {
484 bool hasBFM() const {
488 bool hasBCNT(unsigned Size) const {
492 bool hasFFBL() const {
496 bool hasFFBH() const {
500 bool hasMed3_16() const {
501 return getGeneration() >= AMDGPUSubtarget::GFX9;
504 bool hasMin3Max3_16() const {
505 return getGeneration() >= AMDGPUSubtarget::GFX9;
508 bool hasFmaMixInsts() const {
509 return HasFmaMixInsts;
512 bool hasCARRY() const {
516 bool hasFMA() const {
520 TrapHandlerAbi getTrapHandlerAbi() const {
521 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
524 bool enableHugePrivateBuffer() const {
525 return EnableHugePrivateBuffer;
528 bool unsafeDSOffsetFoldingEnabled() const {
529 return EnableUnsafeDSOffsetFolding;
532 bool dumpCode() const {
536 /// Return the amount of LDS that can be used that will not restrict the
537 /// occupancy lower than WaveCount.
538 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
539 const Function &) const;
541 bool hasFP16Denormals() const {
542 return FP64FP16Denormals;
545 bool hasFP64Denormals() const {
546 return FP64FP16Denormals;
549 bool supportsMinMaxDenormModes() const {
550 return getGeneration() >= AMDGPUSubtarget::GFX9;
553 bool enableDX10Clamp() const {
557 bool enableIEEEBit(const MachineFunction &MF) const {
558 return AMDGPU::isCompute(MF.getFunction().getCallingConv());
561 bool useFlatForGlobal() const {
562 return FlatForGlobal;
565 /// \returns If target supports ds_read/write_b128 and user enables generation
566 /// of ds_read/write_b128.
567 bool useDS128() const {
568 return CIInsts && EnableDS128;
571 /// \returns If MUBUF instructions always perform range checking, even for
572 /// buffer resources used for private memory access.
573 bool privateMemoryResourceIsRangeChecked() const {
574 return getGeneration() < AMDGPUSubtarget::GFX9;
577 bool hasAutoWaitcntBeforeBarrier() const {
578 return AutoWaitcntBeforeBarrier;
581 bool hasCodeObjectV3() const {
585 bool hasUnalignedBufferAccess() const {
586 return UnalignedBufferAccess;
589 bool hasUnalignedScratchAccess() const {
590 return UnalignedScratchAccess;
593 bool hasApertureRegs() const {
594 return HasApertureRegs;
597 bool isTrapHandlerEnabled() const {
601 bool isXNACKEnabled() const {
605 bool hasFlatAddressSpace() const {
606 return FlatAddressSpace;
609 bool hasFlatInstOffsets() const {
610 return FlatInstOffsets;
613 bool hasFlatGlobalInsts() const {
614 return FlatGlobalInsts;
617 bool hasFlatScratchInsts() const {
618 return FlatScratchInsts;
621 bool hasFlatLgkmVMemCountInOrder() const {
622 return getGeneration() > GFX9;
625 bool hasD16LoadStore() const {
626 return getGeneration() >= GFX9;
629 /// Return if most LDS instructions have an m0 use that require m0 to be
631 bool ldsRequiresM0Init() const {
632 return getGeneration() < GFX9;
635 bool hasAddNoCarry() const {
636 return AddNoCarryInsts;
639 bool hasUnpackedD16VMem() const {
640 return HasUnpackedD16VMem;
643 // Covers VS/PS/CS graphics shaders
644 bool isMesaGfxShader(const Function &F) const {
645 return isMesa3DOS() && AMDGPU::isShader(F.getCallingConv());
648 bool hasMad64_32() const {
649 return getGeneration() >= SEA_ISLANDS;
652 bool hasSDWAOmod() const {
656 bool hasSDWAScalar() const {
657 return HasSDWAScalar;
660 bool hasSDWASdst() const {
664 bool hasSDWAMac() const {
668 bool hasSDWAOutModsVOPC() const {
669 return HasSDWAOutModsVOPC;
672 bool vmemWriteNeedsExpWaitcnt() const {
673 return getGeneration() < SEA_ISLANDS;
676 bool hasDLInsts() const {
680 bool d16PreservesUnusedBits() const {
681 return D16PreservesUnusedBits;
684 // Scratch is allocated in 256 dword per wave blocks for the entire
685 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
686 // is 4-byte aligned.
688 // Only 4-byte alignment is really needed to access anything. Transformations
689 // on the pointer value itself may rely on the alignment / known low bits of
690 // the pointer. Set this to something above the minimum to avoid needing
691 // dynamic realignment in common cases.
692 unsigned getStackAlignment() const {
696 bool enableMachineScheduler() const override {
700 bool enableSubRegLiveness() const override {
704 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b; }
705 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal; }
707 /// \returns Number of execution units per compute unit supported by the
709 unsigned getEUsPerCU() const {
710 return AMDGPU::IsaInfo::getEUsPerCU(MCSubtargetInfo::getFeatureBits());
713 /// \returns Maximum number of waves per compute unit supported by the
714 /// subtarget without any kind of limitation.
715 unsigned getMaxWavesPerCU() const {
716 return AMDGPU::IsaInfo::getMaxWavesPerCU(MCSubtargetInfo::getFeatureBits());
719 /// \returns Maximum number of waves per compute unit supported by the
720 /// subtarget and limited by given \p FlatWorkGroupSize.
721 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
722 return AMDGPU::IsaInfo::getMaxWavesPerCU(MCSubtargetInfo::getFeatureBits(),
726 /// \returns Maximum number of waves per execution unit supported by the
727 /// subtarget without any kind of limitation.
728 unsigned getMaxWavesPerEU() const {
729 return AMDGPU::IsaInfo::getMaxWavesPerEU();
732 /// \returns Number of waves per work group supported by the subtarget and
733 /// limited by given \p FlatWorkGroupSize.
734 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
735 return AMDGPU::IsaInfo::getWavesPerWorkGroup(
736 MCSubtargetInfo::getFeatureBits(), FlatWorkGroupSize);
740 static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
742 // XXX - Why is this here if it isn't in the default pass set?
743 bool enableEarlyIfConversion() const override {
747 void overrideSchedPolicy(MachineSchedPolicy &Policy,
748 unsigned NumRegionInstrs) const override;
750 bool isVGPRSpillingEnabled(const Function &F) const;
752 unsigned getMaxNumUserSGPRs() const {
756 bool hasSMemRealTime() const {
757 return HasSMemRealTime;
760 bool hasMovrel() const {
764 bool hasVGPRIndexMode() const {
765 return HasVGPRIndexMode;
768 bool useVGPRIndexMode(bool UserEnable) const {
769 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
772 bool hasScalarCompareEq64() const {
773 return getGeneration() >= VOLCANIC_ISLANDS;
776 bool hasScalarStores() const {
777 return HasScalarStores;
780 bool hasScalarAtomics() const {
781 return HasScalarAtomics;
784 bool hasInv2PiInlineImm() const {
785 return HasInv2PiInlineImm;
788 bool hasDPP() const {
792 bool enableSIScheduler() const {
793 return EnableSIScheduler;
796 bool debuggerSupported() const {
797 return debuggerInsertNops() && debuggerEmitPrologue();
800 bool debuggerInsertNops() const {
801 return DebuggerInsertNops;
804 bool debuggerEmitPrologue() const {
805 return DebuggerEmitPrologue;
808 bool loadStoreOptEnabled() const {
809 return EnableLoadStoreOpt;
812 bool hasSGPRInitBug() const {
816 bool has12DWordStoreHazard() const {
817 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
820 bool hasSMovFedHazard() const {
821 return getGeneration() >= AMDGPUSubtarget::GFX9;
824 bool hasReadM0MovRelInterpHazard() const {
825 return getGeneration() >= AMDGPUSubtarget::GFX9;
828 bool hasReadM0SendMsgHazard() const {
829 return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
832 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs
834 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
836 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs
838 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
840 /// \returns true if the flat_scratch register should be initialized with the
841 /// pointer to the wave's scratch memory rather than a size and offset.
842 bool flatScratchIsPointer() const {
843 return getGeneration() >= AMDGPUSubtarget::GFX9;
846 /// \returns true if the machine has merged shaders in which s0-s7 are
847 /// reserved by the hardware and user SGPRs start at s8
848 bool hasMergedShaders() const {
849 return getGeneration() >= GFX9;
852 /// \returns SGPR allocation granularity supported by the subtarget.
853 unsigned getSGPRAllocGranule() const {
854 return AMDGPU::IsaInfo::getSGPRAllocGranule(
855 MCSubtargetInfo::getFeatureBits());
858 /// \returns SGPR encoding granularity supported by the subtarget.
859 unsigned getSGPREncodingGranule() const {
860 return AMDGPU::IsaInfo::getSGPREncodingGranule(
861 MCSubtargetInfo::getFeatureBits());
864 /// \returns Total number of SGPRs supported by the subtarget.
865 unsigned getTotalNumSGPRs() const {
866 return AMDGPU::IsaInfo::getTotalNumSGPRs(MCSubtargetInfo::getFeatureBits());
869 /// \returns Addressable number of SGPRs supported by the subtarget.
870 unsigned getAddressableNumSGPRs() const {
871 return AMDGPU::IsaInfo::getAddressableNumSGPRs(
872 MCSubtargetInfo::getFeatureBits());
875 /// \returns Minimum number of SGPRs that meets the given number of waves per
876 /// execution unit requirement supported by the subtarget.
877 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
878 return AMDGPU::IsaInfo::getMinNumSGPRs(MCSubtargetInfo::getFeatureBits(),
882 /// \returns Maximum number of SGPRs that meets the given number of waves per
883 /// execution unit requirement supported by the subtarget.
884 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
885 return AMDGPU::IsaInfo::getMaxNumSGPRs(MCSubtargetInfo::getFeatureBits(),
886 WavesPerEU, Addressable);
889 /// \returns Reserved number of SGPRs for given function \p MF.
890 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
892 /// \returns Maximum number of SGPRs that meets number of waves per execution
893 /// unit requirement for function \p MF, or number of SGPRs explicitly
894 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
896 /// \returns Value that meets number of waves per execution unit requirement
897 /// if explicitly requested value cannot be converted to integer, violates
898 /// subtarget's specifications, or does not meet number of waves per execution
899 /// unit requirement.
900 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
902 /// \returns VGPR allocation granularity supported by the subtarget.
903 unsigned getVGPRAllocGranule() const {
904 return AMDGPU::IsaInfo::getVGPRAllocGranule(
905 MCSubtargetInfo::getFeatureBits());
908 /// \returns VGPR encoding granularity supported by the subtarget.
909 unsigned getVGPREncodingGranule() const {
910 return AMDGPU::IsaInfo::getVGPREncodingGranule(
911 MCSubtargetInfo::getFeatureBits());
914 /// \returns Total number of VGPRs supported by the subtarget.
915 unsigned getTotalNumVGPRs() const {
916 return AMDGPU::IsaInfo::getTotalNumVGPRs(MCSubtargetInfo::getFeatureBits());
919 /// \returns Addressable number of VGPRs supported by the subtarget.
920 unsigned getAddressableNumVGPRs() const {
921 return AMDGPU::IsaInfo::getAddressableNumVGPRs(
922 MCSubtargetInfo::getFeatureBits());
925 /// \returns Minimum number of VGPRs that meets given number of waves per
926 /// execution unit requirement supported by the subtarget.
927 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
928 return AMDGPU::IsaInfo::getMinNumVGPRs(MCSubtargetInfo::getFeatureBits(),
932 /// \returns Maximum number of VGPRs that meets given number of waves per
933 /// execution unit requirement supported by the subtarget.
934 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
935 return AMDGPU::IsaInfo::getMaxNumVGPRs(MCSubtargetInfo::getFeatureBits(),
939 /// \returns Maximum number of VGPRs that meets number of waves per execution
940 /// unit requirement for function \p MF, or number of VGPRs explicitly
941 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
943 /// \returns Value that meets number of waves per execution unit requirement
944 /// if explicitly requested value cannot be converted to integer, violates
945 /// subtarget's specifications, or does not meet number of waves per execution
946 /// unit requirement.
947 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
949 void getPostRAMutations(
950 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
954 class R600Subtarget final : public R600GenSubtargetInfo,
955 public AMDGPUSubtarget {
957 R600InstrInfo InstrInfo;
958 R600FrameLowering FrameLowering;
966 short TexVTXClauseSize;
968 R600TargetLowering TLInfo;
969 InstrItineraryData InstrItins;
970 SelectionDAGTargetInfo TSInfo;
974 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
975 const TargetMachine &TM);
977 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
979 const R600FrameLowering *getFrameLowering() const override {
980 return &FrameLowering;
983 const R600TargetLowering *getTargetLowering() const override {
987 const R600RegisterInfo *getRegisterInfo() const override {
988 return &InstrInfo.getRegisterInfo();
991 const InstrItineraryData *getInstrItineraryData() const override {
995 // Nothing implemented, just prevent crashes on use.
996 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
1000 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
1002 Generation getGeneration() const {
1006 unsigned getStackAlignment() const {
1010 R600Subtarget &initializeSubtargetDependencies(const Triple &TT,
1011 StringRef GPU, StringRef FS);
1013 bool hasBFE() const {
1014 return (getGeneration() >= EVERGREEN);
1017 bool hasBFI() const {
1018 return (getGeneration() >= EVERGREEN);
1021 bool hasBCNT(unsigned Size) const {
1023 return (getGeneration() >= EVERGREEN);
1028 bool hasBORROW() const {
1029 return (getGeneration() >= EVERGREEN);
1032 bool hasCARRY() const {
1033 return (getGeneration() >= EVERGREEN);
1036 bool hasCaymanISA() const {
1040 bool hasFFBL() const {
1041 return (getGeneration() >= EVERGREEN);
1044 bool hasFFBH() const {
1045 return (getGeneration() >= EVERGREEN);
1048 bool hasFMA() const { return FMA; }
1050 bool hasCFAluBug() const { return CFALUBug; }
1052 bool hasVertexCache() const { return HasVertexCache; }
1054 short getTexVTXClauseSize() const { return TexVTXClauseSize; }
1056 AMDGPUAS getAMDGPUAS() const { return AS; }
1058 bool enableMachineScheduler() const override {
1062 bool enableSubRegLiveness() const override {
1067 } // end namespace llvm
1069 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H