1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "R600FrameLowering.h"
20 #include "R600ISelLowering.h"
21 #include "R600InstrInfo.h"
22 #include "SIFrameLowering.h"
23 #include "SIISelLowering.h"
24 #include "SIInstrInfo.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "Utils/AMDGPUBaseInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/MathExtras.h"
38 #define GET_SUBTARGETINFO_HEADER
39 #include "AMDGPUGenSubtargetInfo.inc"
45 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
79 TrapHandlerAbiNone = 0,
84 TrapIDHardwareReserved = 0,
85 TrapIDHSADebugTrap = 1,
87 TrapIDLLVMDebugTrap = 3,
88 TrapIDDebugBreakpoint = 7,
89 TrapIDDebugReserved8 = 8,
90 TrapIDDebugReservedFE = 0xfe,
91 TrapIDDebugReservedFF = 0xff
95 LLVMTrapHandlerRegValue = 1
99 // Basic subtarget description.
103 unsigned WavefrontSize;
106 unsigned MaxPrivateElementSize;
108 // Possibly statically set by tablegen, but may want to be overridden.
112 // Dynamially set bits that enable features.
114 bool FP64FP16Denormals;
118 bool AutoWaitcntBeforeBarrier;
119 bool UnalignedScratchAccess;
120 bool UnalignedBufferAccess;
121 bool HasApertureRegs;
124 bool DebuggerInsertNops;
125 bool DebuggerReserveRegs;
126 bool DebuggerEmitPrologue;
129 bool EnableVGPRSpilling;
130 bool EnablePromoteAlloca;
131 bool EnableLoadStoreOpt;
132 bool EnableUnsafeDSOffsetFolding;
133 bool EnableSIScheduler;
136 // Subtarget statically properties set by tablegen
144 bool HasSMemRealTime;
148 bool HasVGPRIndexMode;
149 bool HasScalarStores;
150 bool HasInv2PiInlineImm;
156 bool HasSDWAOutModsVOPC;
158 bool FlatAddressSpace;
159 bool FlatInstOffsets;
160 bool FlatGlobalInsts;
161 bool FlatScratchInsts;
166 short TexVTXClauseSize;
167 bool ScalarizeGlobal;
169 // Dummy feature to use for assembler in tablegen.
172 InstrItineraryData InstrItins;
173 SelectionDAGTargetInfo TSInfo;
177 AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
178 const TargetMachine &TM);
179 ~AMDGPUSubtarget() override;
181 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
182 StringRef GPU, StringRef FS);
184 const AMDGPUInstrInfo *getInstrInfo() const override = 0;
185 const AMDGPUFrameLowering *getFrameLowering() const override = 0;
186 const AMDGPUTargetLowering *getTargetLowering() const override = 0;
187 const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
189 const InstrItineraryData *getInstrItineraryData() const override {
193 // Nothing implemented, just prevent crashes on use.
194 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
198 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
200 bool isAmdHsaOS() const {
201 return TargetTriple.getOS() == Triple::AMDHSA;
204 bool isMesa3DOS() const {
205 return TargetTriple.getOS() == Triple::Mesa3D;
208 bool isOpenCLEnv() const {
209 return TargetTriple.getEnvironment() == Triple::OpenCL ||
210 TargetTriple.getEnvironmentName() == "amdgizcl";
213 Generation getGeneration() const {
217 unsigned getWavefrontSize() const {
218 return WavefrontSize;
221 int getLocalMemorySize() const {
222 return LocalMemorySize;
225 int getLDSBankCount() const {
229 unsigned getMaxPrivateElementSize() const {
230 return MaxPrivateElementSize;
233 AMDGPUAS getAMDGPUAS() const {
237 bool has16BitInsts() const {
238 return Has16BitInsts;
241 bool hasVOP3PInsts() const {
242 return HasVOP3PInsts;
245 bool hasHWFP64() const {
249 bool hasFastFMAF32() const {
253 bool hasHalfRate64Ops() const {
254 return HalfRate64Ops;
257 bool hasAddr64() const {
258 return (getGeneration() < VOLCANIC_ISLANDS);
261 bool hasBFE() const {
262 return (getGeneration() >= EVERGREEN);
265 bool hasBFI() const {
266 return (getGeneration() >= EVERGREEN);
269 bool hasBFM() const {
273 bool hasBCNT(unsigned Size) const {
275 return (getGeneration() >= EVERGREEN);
278 return (getGeneration() >= SOUTHERN_ISLANDS);
283 bool hasMulU24() const {
284 return (getGeneration() >= EVERGREEN);
287 bool hasMulI24() const {
288 return (getGeneration() >= SOUTHERN_ISLANDS ||
292 bool hasFFBL() const {
293 return (getGeneration() >= EVERGREEN);
296 bool hasFFBH() const {
297 return (getGeneration() >= EVERGREEN);
300 bool hasMed3_16() const {
301 return getGeneration() >= GFX9;
304 bool hasMin3Max3_16() const {
305 return getGeneration() >= GFX9;
308 bool hasCARRY() const {
309 return (getGeneration() >= EVERGREEN);
312 bool hasBORROW() const {
313 return (getGeneration() >= EVERGREEN);
316 bool hasCaymanISA() const {
320 TrapHandlerAbi getTrapHandlerAbi() const {
321 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
324 bool isPromoteAllocaEnabled() const {
325 return EnablePromoteAlloca;
328 bool unsafeDSOffsetFoldingEnabled() const {
329 return EnableUnsafeDSOffsetFolding;
332 bool dumpCode() const {
336 /// Return the amount of LDS that can be used that will not restrict the
337 /// occupancy lower than WaveCount.
338 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
339 const Function &) const;
341 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
342 /// the given LDS memory size is the only constraint.
343 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
345 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const {
346 const auto *MFI = MF.getInfo<SIMachineFunctionInfo>();
347 return getOccupancyWithLocalMemSize(MFI->getLDSSize(), *MF.getFunction());
350 bool hasFP16Denormals() const {
351 return FP64FP16Denormals;
354 bool hasFP32Denormals() const {
355 return FP32Denormals;
358 bool hasFP64Denormals() const {
359 return FP64FP16Denormals;
362 bool supportsMinMaxDenormModes() const {
363 return getGeneration() >= AMDGPUSubtarget::GFX9;
366 bool hasFPExceptions() const {
370 bool enableDX10Clamp() const {
374 bool enableIEEEBit(const MachineFunction &MF) const {
375 return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
378 bool useFlatForGlobal() const {
379 return FlatForGlobal;
382 bool hasAutoWaitcntBeforeBarrier() const {
383 return AutoWaitcntBeforeBarrier;
386 bool hasUnalignedBufferAccess() const {
387 return UnalignedBufferAccess;
390 bool hasUnalignedScratchAccess() const {
391 return UnalignedScratchAccess;
394 bool hasApertureRegs() const {
395 return HasApertureRegs;
398 bool isTrapHandlerEnabled() const {
402 bool isXNACKEnabled() const {
406 bool hasFlatAddressSpace() const {
407 return FlatAddressSpace;
410 bool hasFlatInstOffsets() const {
411 return FlatInstOffsets;
414 bool hasFlatGlobalInsts() const {
415 return FlatGlobalInsts;
418 bool hasFlatScratchInsts() const {
419 return FlatScratchInsts;
422 bool isMesaKernel(const MachineFunction &MF) const {
423 return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
426 // Covers VS/PS/CS graphics shaders
427 bool isMesaGfxShader(const MachineFunction &MF) const {
428 return isMesa3DOS() && AMDGPU::isShader(MF.getFunction()->getCallingConv());
431 bool isAmdCodeObjectV2(const MachineFunction &MF) const {
432 return isAmdHsaOS() || isMesaKernel(MF);
435 bool hasFminFmaxLegacy() const {
436 return getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
439 bool hasSDWA() const {
443 bool hasSDWAOmod() const {
447 bool hasSDWAScalar() const {
448 return HasSDWAScalar;
451 bool hasSDWASdst() const {
455 bool hasSDWAMac() const {
459 bool hasSDWAOutModsVOPC() const {
460 return HasSDWAOutModsVOPC;
463 /// \brief Returns the offset in bytes from the start of the input buffer
464 /// of the first explicit kernel argument.
465 unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
466 return isAmdCodeObjectV2(MF) ? 0 : 36;
469 unsigned getAlignmentForImplicitArgPtr() const {
470 return isAmdHsaOS() ? 8 : 4;
473 unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
474 if (isMesaKernel(MF))
476 if (isAmdHsaOS() && isOpenCLEnv())
481 // Scratch is allocated in 256 dword per wave blocks for the entire
482 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
483 // is 4-byte aligned.
484 unsigned getStackAlignment() const {
488 bool enableMachineScheduler() const override {
492 bool enableSubRegLiveness() const override {
496 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
497 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
499 /// \returns Number of execution units per compute unit supported by the
501 unsigned getEUsPerCU() const {
502 return AMDGPU::IsaInfo::getEUsPerCU(getFeatureBits());
505 /// \returns Maximum number of work groups per compute unit supported by the
506 /// subtarget and limited by given \p FlatWorkGroupSize.
507 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
508 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(getFeatureBits(),
512 /// \returns Maximum number of waves per compute unit supported by the
513 /// subtarget without any kind of limitation.
514 unsigned getMaxWavesPerCU() const {
515 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits());
518 /// \returns Maximum number of waves per compute unit supported by the
519 /// subtarget and limited by given \p FlatWorkGroupSize.
520 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
521 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits(),
525 /// \returns Minimum number of waves per execution unit supported by the
527 unsigned getMinWavesPerEU() const {
528 return AMDGPU::IsaInfo::getMinWavesPerEU(getFeatureBits());
531 /// \returns Maximum number of waves per execution unit supported by the
532 /// subtarget without any kind of limitation.
533 unsigned getMaxWavesPerEU() const {
534 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits());
537 /// \returns Maximum number of waves per execution unit supported by the
538 /// subtarget and limited by given \p FlatWorkGroupSize.
539 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
540 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits(),
544 /// \returns Minimum flat work group size supported by the subtarget.
545 unsigned getMinFlatWorkGroupSize() const {
546 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(getFeatureBits());
549 /// \returns Maximum flat work group size supported by the subtarget.
550 unsigned getMaxFlatWorkGroupSize() const {
551 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(getFeatureBits());
554 /// \returns Number of waves per work group supported by the subtarget and
555 /// limited by given \p FlatWorkGroupSize.
556 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
557 return AMDGPU::IsaInfo::getWavesPerWorkGroup(getFeatureBits(),
561 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
562 /// for function \p F, or minimum/maximum flat work group sizes explicitly
563 /// requested using "amdgpu-flat-work-group-size" attribute attached to
566 /// \returns Subtarget's default values if explicitly requested values cannot
567 /// be converted to integer, or violate subtarget's specifications.
568 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
570 /// \returns Subtarget's default pair of minimum/maximum number of waves per
571 /// execution unit for function \p F, or minimum/maximum number of waves per
572 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
573 /// attached to function \p F.
575 /// \returns Subtarget's default values if explicitly requested values cannot
576 /// be converted to integer, violate subtarget's specifications, or are not
577 /// compatible with minimum/maximum number of waves limited by flat work group
578 /// size, register usage, and/or lds usage.
579 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
581 /// Creates value range metadata on an workitemid.* inrinsic call or load.
582 bool makeLIDRangeMetadata(Instruction *I) const;
585 class R600Subtarget final : public AMDGPUSubtarget {
587 R600InstrInfo InstrInfo;
588 R600FrameLowering FrameLowering;
589 R600TargetLowering TLInfo;
592 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
593 const TargetMachine &TM);
595 const R600InstrInfo *getInstrInfo() const override {
599 const R600FrameLowering *getFrameLowering() const override {
600 return &FrameLowering;
603 const R600TargetLowering *getTargetLowering() const override {
607 const R600RegisterInfo *getRegisterInfo() const override {
608 return &InstrInfo.getRegisterInfo();
611 bool hasCFAluBug() const {
615 bool hasVertexCache() const {
616 return HasVertexCache;
619 short getTexVTXClauseSize() const {
620 return TexVTXClauseSize;
624 class SISubtarget final : public AMDGPUSubtarget {
626 SIInstrInfo InstrInfo;
627 SIFrameLowering FrameLowering;
628 SITargetLowering TLInfo;
629 std::unique_ptr<GISelAccessor> GISel;
632 SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
633 const TargetMachine &TM);
635 const SIInstrInfo *getInstrInfo() const override {
639 const SIFrameLowering *getFrameLowering() const override {
640 return &FrameLowering;
643 const SITargetLowering *getTargetLowering() const override {
647 const CallLowering *getCallLowering() const override {
648 assert(GISel && "Access to GlobalISel APIs not set");
649 return GISel->getCallLowering();
652 const InstructionSelector *getInstructionSelector() const override {
653 assert(GISel && "Access to GlobalISel APIs not set");
654 return GISel->getInstructionSelector();
657 const LegalizerInfo *getLegalizerInfo() const override {
658 assert(GISel && "Access to GlobalISel APIs not set");
659 return GISel->getLegalizerInfo();
662 const RegisterBankInfo *getRegBankInfo() const override {
663 assert(GISel && "Access to GlobalISel APIs not set");
664 return GISel->getRegBankInfo();
667 const SIRegisterInfo *getRegisterInfo() const override {
668 return &InstrInfo.getRegisterInfo();
671 void setGISelAccessor(GISelAccessor &GISel) {
672 this->GISel.reset(&GISel);
675 // XXX - Why is this here if it isn't in the default pass set?
676 bool enableEarlyIfConversion() const override {
680 void overrideSchedPolicy(MachineSchedPolicy &Policy,
681 unsigned NumRegionInstrs) const override;
683 bool isVGPRSpillingEnabled(const Function& F) const;
685 unsigned getMaxNumUserSGPRs() const {
689 bool hasSMemRealTime() const {
690 return HasSMemRealTime;
693 bool hasMovrel() const {
697 bool hasVGPRIndexMode() const {
698 return HasVGPRIndexMode;
701 bool useVGPRIndexMode(bool UserEnable) const {
702 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
705 bool hasScalarCompareEq64() const {
706 return getGeneration() >= VOLCANIC_ISLANDS;
709 bool hasScalarStores() const {
710 return HasScalarStores;
713 bool hasInv2PiInlineImm() const {
714 return HasInv2PiInlineImm;
717 bool hasDPP() const {
721 bool enableSIScheduler() const {
722 return EnableSIScheduler;
725 bool debuggerSupported() const {
726 return debuggerInsertNops() && debuggerReserveRegs() &&
727 debuggerEmitPrologue();
730 bool debuggerInsertNops() const {
731 return DebuggerInsertNops;
734 bool debuggerReserveRegs() const {
735 return DebuggerReserveRegs;
738 bool debuggerEmitPrologue() const {
739 return DebuggerEmitPrologue;
742 bool loadStoreOptEnabled() const {
743 return EnableLoadStoreOpt;
746 bool hasSGPRInitBug() const {
750 bool has12DWordStoreHazard() const {
751 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
754 bool hasSMovFedHazard() const {
755 return getGeneration() >= AMDGPUSubtarget::GFX9;
758 bool hasReadM0Hazard() const {
759 return getGeneration() >= AMDGPUSubtarget::GFX9;
762 unsigned getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const;
764 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
765 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
767 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
768 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
770 /// \returns true if the flat_scratch register should be initialized with the
771 /// pointer to the wave's scratch memory rather than a size and offset.
772 bool flatScratchIsPointer() const {
773 return getGeneration() >= GFX9;
776 /// \returns SGPR allocation granularity supported by the subtarget.
777 unsigned getSGPRAllocGranule() const {
778 return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
781 /// \returns SGPR encoding granularity supported by the subtarget.
782 unsigned getSGPREncodingGranule() const {
783 return AMDGPU::IsaInfo::getSGPREncodingGranule(getFeatureBits());
786 /// \returns Total number of SGPRs supported by the subtarget.
787 unsigned getTotalNumSGPRs() const {
788 return AMDGPU::IsaInfo::getTotalNumSGPRs(getFeatureBits());
791 /// \returns Addressable number of SGPRs supported by the subtarget.
792 unsigned getAddressableNumSGPRs() const {
793 return AMDGPU::IsaInfo::getAddressableNumSGPRs(getFeatureBits());
796 /// \returns Minimum number of SGPRs that meets the given number of waves per
797 /// execution unit requirement supported by the subtarget.
798 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
799 return AMDGPU::IsaInfo::getMinNumSGPRs(getFeatureBits(), WavesPerEU);
802 /// \returns Maximum number of SGPRs that meets the given number of waves per
803 /// execution unit requirement supported by the subtarget.
804 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
805 return AMDGPU::IsaInfo::getMaxNumSGPRs(getFeatureBits(), WavesPerEU,
809 /// \returns Reserved number of SGPRs for given function \p MF.
810 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
812 /// \returns Maximum number of SGPRs that meets number of waves per execution
813 /// unit requirement for function \p MF, or number of SGPRs explicitly
814 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
816 /// \returns Value that meets number of waves per execution unit requirement
817 /// if explicitly requested value cannot be converted to integer, violates
818 /// subtarget's specifications, or does not meet number of waves per execution
819 /// unit requirement.
820 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
822 /// \returns VGPR allocation granularity supported by the subtarget.
823 unsigned getVGPRAllocGranule() const {
824 return AMDGPU::IsaInfo::getVGPRAllocGranule(getFeatureBits());
827 /// \returns VGPR encoding granularity supported by the subtarget.
828 unsigned getVGPREncodingGranule() const {
829 return AMDGPU::IsaInfo::getVGPREncodingGranule(getFeatureBits());
832 /// \returns Total number of VGPRs supported by the subtarget.
833 unsigned getTotalNumVGPRs() const {
834 return AMDGPU::IsaInfo::getTotalNumVGPRs(getFeatureBits());
837 /// \returns Addressable number of VGPRs supported by the subtarget.
838 unsigned getAddressableNumVGPRs() const {
839 return AMDGPU::IsaInfo::getAddressableNumVGPRs(getFeatureBits());
842 /// \returns Minimum number of VGPRs that meets given number of waves per
843 /// execution unit requirement supported by the subtarget.
844 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
845 return AMDGPU::IsaInfo::getMinNumVGPRs(getFeatureBits(), WavesPerEU);
848 /// \returns Maximum number of VGPRs that meets given number of waves per
849 /// execution unit requirement supported by the subtarget.
850 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
851 return AMDGPU::IsaInfo::getMaxNumVGPRs(getFeatureBits(), WavesPerEU);
854 /// \returns Reserved number of VGPRs for given function \p MF.
855 unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
856 return debuggerReserveRegs() ? 4 : 0;
859 /// \returns Maximum number of VGPRs that meets number of waves per execution
860 /// unit requirement for function \p MF, or number of VGPRs explicitly
861 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
863 /// \returns Value that meets number of waves per execution unit requirement
864 /// if explicitly requested value cannot be converted to integer, violates
865 /// subtarget's specifications, or does not meet number of waves per execution
866 /// unit requirement.
867 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
870 } // end namespace llvm
872 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H