1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "R600InstrInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600FrameLowering.h"
22 #include "SIInstrInfo.h"
23 #include "SIISelLowering.h"
24 #include "SIFrameLowering.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm/ADT/Triple.h"
27 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/Support/MathExtras.h"
37 #define GET_SUBTARGETINFO_HEADER
38 #include "AMDGPUGenSubtargetInfo.inc"
44 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
70 // Basic subtarget description.
74 unsigned WavefrontSize;
77 unsigned MaxPrivateElementSize;
79 // Possibly statically set by tablegen, but may want to be overridden.
83 // Dynamially set bits that enable features.
89 bool UnalignedScratchAccess;
90 bool UnalignedBufferAccess;
92 bool DebuggerInsertNops;
93 bool DebuggerReserveRegs;
94 bool DebuggerEmitPrologue;
97 bool EnableVGPRSpilling;
98 bool EnablePromoteAlloca;
99 bool EnableLoadStoreOpt;
100 bool EnableUnsafeDSOffsetFolding;
101 bool EnableSIScheduler;
104 // Subtarget statically properties set by tablegen
111 bool HasSMemRealTime;
114 bool HasVGPRIndexMode;
115 bool HasScalarStores;
116 bool HasInv2PiInlineImm;
117 bool FlatAddressSpace;
122 short TexVTXClauseSize;
123 bool ScalarizeGlobal;
125 // Dummy feature to use for assembler in tablegen.
128 InstrItineraryData InstrItins;
129 SelectionDAGTargetInfo TSInfo;
132 AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
133 const TargetMachine &TM);
134 ~AMDGPUSubtarget() override;
136 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
137 StringRef GPU, StringRef FS);
139 const AMDGPUInstrInfo *getInstrInfo() const override = 0;
140 const AMDGPUFrameLowering *getFrameLowering() const override = 0;
141 const AMDGPUTargetLowering *getTargetLowering() const override = 0;
142 const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
144 const InstrItineraryData *getInstrItineraryData() const override {
148 // Nothing implemented, just prevent crashes on use.
149 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
153 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
155 bool isAmdHsaOS() const {
156 return TargetTriple.getOS() == Triple::AMDHSA;
159 bool isMesa3DOS() const {
160 return TargetTriple.getOS() == Triple::Mesa3D;
163 bool isOpenCLEnv() const {
164 return TargetTriple.getEnvironment() == Triple::OpenCL;
167 Generation getGeneration() const {
171 unsigned getWavefrontSize() const {
172 return WavefrontSize;
175 int getLocalMemorySize() const {
176 return LocalMemorySize;
179 int getLDSBankCount() const {
183 unsigned getMaxPrivateElementSize() const {
184 return MaxPrivateElementSize;
187 bool has16BitInsts() const {
188 return Has16BitInsts;
191 bool hasHWFP64() const {
195 bool hasFastFMAF32() const {
199 bool hasHalfRate64Ops() const {
200 return HalfRate64Ops;
203 bool hasAddr64() const {
204 return (getGeneration() < VOLCANIC_ISLANDS);
207 bool hasBFE() const {
208 return (getGeneration() >= EVERGREEN);
211 bool hasBFI() const {
212 return (getGeneration() >= EVERGREEN);
215 bool hasBFM() const {
219 bool hasBCNT(unsigned Size) const {
221 return (getGeneration() >= EVERGREEN);
224 return (getGeneration() >= SOUTHERN_ISLANDS);
229 bool hasMulU24() const {
230 return (getGeneration() >= EVERGREEN);
233 bool hasMulI24() const {
234 return (getGeneration() >= SOUTHERN_ISLANDS ||
238 bool hasFFBL() const {
239 return (getGeneration() >= EVERGREEN);
242 bool hasFFBH() const {
243 return (getGeneration() >= EVERGREEN);
246 bool hasCARRY() const {
247 return (getGeneration() >= EVERGREEN);
250 bool hasBORROW() const {
251 return (getGeneration() >= EVERGREEN);
254 bool hasCaymanISA() const {
258 bool isPromoteAllocaEnabled() const {
259 return EnablePromoteAlloca;
262 bool unsafeDSOffsetFoldingEnabled() const {
263 return EnableUnsafeDSOffsetFolding;
266 bool dumpCode() const {
270 bool enableIEEEBit(const MachineFunction &MF) const {
271 return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
274 /// Return the amount of LDS that can be used that will not restrict the
275 /// occupancy lower than WaveCount.
276 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount) const;
278 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
279 /// the given LDS memory size is the only constraint.
280 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes) const;
282 bool hasFP16Denormals() const {
283 return FP16Denormals;
286 bool hasFP32Denormals() const {
287 return FP32Denormals;
290 bool hasFP64Denormals() const {
291 return FP64Denormals;
294 bool hasFPExceptions() const {
298 bool useFlatForGlobal() const {
299 return FlatForGlobal;
302 bool hasUnalignedBufferAccess() const {
303 return UnalignedBufferAccess;
306 bool hasUnalignedScratchAccess() const {
307 return UnalignedScratchAccess;
310 bool isXNACKEnabled() const {
314 bool isMesaKernel(const MachineFunction &MF) const {
315 return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
318 // Covers VS/PS/CS graphics shaders
319 bool isMesaGfxShader(const MachineFunction &MF) const {
320 return isMesa3DOS() && AMDGPU::isShader(MF.getFunction()->getCallingConv());
323 bool isAmdCodeObjectV2(const MachineFunction &MF) const {
324 return isAmdHsaOS() || isMesaKernel(MF);
327 /// \brief Returns the offset in bytes from the start of the input buffer
328 /// of the first explicit kernel argument.
329 unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
330 return isAmdCodeObjectV2(MF) ? 0 : 36;
333 unsigned getAlignmentForImplicitArgPtr() const {
334 return isAmdHsaOS() ? 8 : 4;
337 unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
338 if (isMesaKernel(MF))
340 if (isAmdHsaOS() && isOpenCLEnv())
345 unsigned getStackAlignment() const {
346 // Scratch is allocated in 256 dword per wave blocks.
347 return 4 * 256 / getWavefrontSize();
350 bool enableMachineScheduler() const override {
354 bool enableSubRegLiveness() const override {
358 /// \returns Number of execution units per compute unit supported by the
360 unsigned getEUsPerCU() const {
364 /// \returns Maximum number of work groups per compute unit supported by the
365 /// subtarget and limited by given flat work group size.
366 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
367 if (getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
369 return getWavesPerWorkGroup(FlatWorkGroupSize) == 1 ? 40 : 16;
372 /// \returns Maximum number of waves per compute unit supported by the
373 /// subtarget without any kind of limitation.
374 unsigned getMaxWavesPerCU() const {
375 return getMaxWavesPerEU() * getEUsPerCU();
378 /// \returns Maximum number of waves per compute unit supported by the
379 /// subtarget and limited by given flat work group size.
380 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
381 return getWavesPerWorkGroup(FlatWorkGroupSize);
384 /// \returns Minimum number of waves per execution unit supported by the
386 unsigned getMinWavesPerEU() const {
390 /// \returns Maximum number of waves per execution unit supported by the
391 /// subtarget without any kind of limitation.
392 unsigned getMaxWavesPerEU() const {
393 if (getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
395 // FIXME: Need to take scratch memory into account.
399 /// \returns Maximum number of waves per execution unit supported by the
400 /// subtarget and limited by given flat work group size.
401 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
402 return alignTo(getMaxWavesPerCU(FlatWorkGroupSize), getEUsPerCU()) /
406 /// \returns Minimum flat work group size supported by the subtarget.
407 unsigned getMinFlatWorkGroupSize() const {
411 /// \returns Maximum flat work group size supported by the subtarget.
412 unsigned getMaxFlatWorkGroupSize() const {
416 /// \returns Number of waves per work group given the flat work group size.
417 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
418 return alignTo(FlatWorkGroupSize, getWavefrontSize()) / getWavefrontSize();
421 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
422 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
424 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
425 /// for function \p F, or minimum/maximum flat work group sizes explicitly
426 /// requested using "amdgpu-flat-work-group-size" attribute attached to
429 /// \returns Subtarget's default values if explicitly requested values cannot
430 /// be converted to integer, or violate subtarget's specifications.
431 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
433 /// \returns Subtarget's default pair of minimum/maximum number of waves per
434 /// execution unit for function \p F, or minimum/maximum number of waves per
435 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
436 /// attached to function \p F.
438 /// \returns Subtarget's default values if explicitly requested values cannot
439 /// be converted to integer, violate subtarget's specifications, or are not
440 /// compatible with minimum/maximum number of waves limited by flat work group
441 /// size, register usage, and/or lds usage.
442 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
445 class R600Subtarget final : public AMDGPUSubtarget {
447 R600InstrInfo InstrInfo;
448 R600FrameLowering FrameLowering;
449 R600TargetLowering TLInfo;
452 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
453 const TargetMachine &TM);
455 const R600InstrInfo *getInstrInfo() const override {
459 const R600FrameLowering *getFrameLowering() const override {
460 return &FrameLowering;
463 const R600TargetLowering *getTargetLowering() const override {
467 const R600RegisterInfo *getRegisterInfo() const override {
468 return &InstrInfo.getRegisterInfo();
471 bool hasCFAluBug() const {
475 bool hasVertexCache() const {
476 return HasVertexCache;
479 short getTexVTXClauseSize() const {
480 return TexVTXClauseSize;
484 class SISubtarget final : public AMDGPUSubtarget {
487 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
488 // doesn't spill SGPRs as much as when 80 is set.
489 FIXED_SGPR_COUNT_FOR_INIT_BUG = 96
493 SIInstrInfo InstrInfo;
494 SIFrameLowering FrameLowering;
495 SITargetLowering TLInfo;
496 std::unique_ptr<GISelAccessor> GISel;
499 SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
500 const TargetMachine &TM);
502 const SIInstrInfo *getInstrInfo() const override {
506 const SIFrameLowering *getFrameLowering() const override {
507 return &FrameLowering;
510 const SITargetLowering *getTargetLowering() const override {
514 const CallLowering *getCallLowering() const override {
515 assert(GISel && "Access to GlobalISel APIs not set");
516 return GISel->getCallLowering();
519 const SIRegisterInfo *getRegisterInfo() const override {
520 return &InstrInfo.getRegisterInfo();
523 void setGISelAccessor(GISelAccessor &GISel) {
524 this->GISel.reset(&GISel);
527 void overrideSchedPolicy(MachineSchedPolicy &Policy,
528 unsigned NumRegionInstrs) const override;
530 bool isVGPRSpillingEnabled(const Function& F) const;
532 unsigned getMaxNumUserSGPRs() const {
536 bool hasFlatAddressSpace() const {
537 return FlatAddressSpace;
540 bool hasSMemRealTime() const {
541 return HasSMemRealTime;
544 bool hasMovrel() const {
548 bool hasVGPRIndexMode() const {
549 return HasVGPRIndexMode;
552 bool hasScalarCompareEq64() const {
553 return getGeneration() >= VOLCANIC_ISLANDS;
556 bool hasScalarStores() const {
557 return HasScalarStores;
560 bool hasInv2PiInlineImm() const {
561 return HasInv2PiInlineImm;
564 bool enableSIScheduler() const {
565 return EnableSIScheduler;
568 bool debuggerSupported() const {
569 return debuggerInsertNops() && debuggerReserveRegs() &&
570 debuggerEmitPrologue();
573 bool debuggerInsertNops() const {
574 return DebuggerInsertNops;
577 bool debuggerReserveRegs() const {
578 return DebuggerReserveRegs;
581 bool debuggerEmitPrologue() const {
582 return DebuggerEmitPrologue;
585 bool loadStoreOptEnabled() const {
586 return EnableLoadStoreOpt;
589 bool hasSGPRInitBug() const {
593 bool has12DWordStoreHazard() const {
594 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
597 unsigned getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const;
599 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
600 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
602 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
603 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
605 /// \returns True if waitcnt instruction is needed before barrier instruction,
607 bool needWaitcntBeforeBarrier() const {
611 unsigned getMaxNumSGPRs() const;
614 } // end namespace llvm
616 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H