1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "R600InstrInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600FrameLowering.h"
22 #include "SIInstrInfo.h"
23 #include "SIISelLowering.h"
24 #include "SIFrameLowering.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "Utils/AMDGPUBaseInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/MathExtras.h"
38 #define GET_SUBTARGETINFO_HEADER
39 #include "AMDGPUGenSubtargetInfo.inc"
45 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
74 TrapHandlerAbiNone = 0,
79 TrapIDHardwareReserved = 0,
80 TrapIDHSADebugTrap = 1,
82 TrapIDLLVMDebugTrap = 3,
83 TrapIDDebugBreakpoint = 7,
84 TrapIDDebugReserved8 = 8,
85 TrapIDDebugReservedFE = 0xfe,
86 TrapIDDebugReservedFF = 0xff
90 LLVMTrapHandlerRegValue = 1
94 // Basic subtarget description.
98 unsigned WavefrontSize;
101 unsigned MaxPrivateElementSize;
103 // Possibly statically set by tablegen, but may want to be overridden.
107 // Dynamially set bits that enable features.
109 bool FP64FP16Denormals;
113 bool UnalignedScratchAccess;
114 bool UnalignedBufferAccess;
115 bool HasApertureRegs;
118 bool DebuggerInsertNops;
119 bool DebuggerReserveRegs;
120 bool DebuggerEmitPrologue;
123 bool EnableVGPRSpilling;
124 bool EnablePromoteAlloca;
125 bool EnableLoadStoreOpt;
126 bool EnableUnsafeDSOffsetFolding;
127 bool EnableSIScheduler;
130 // Subtarget statically properties set by tablegen
138 bool HasSMemRealTime;
142 bool HasVGPRIndexMode;
143 bool HasScalarStores;
144 bool HasInv2PiInlineImm;
147 bool FlatAddressSpace;
152 short TexVTXClauseSize;
153 bool ScalarizeGlobal;
155 // Dummy feature to use for assembler in tablegen.
158 InstrItineraryData InstrItins;
159 SelectionDAGTargetInfo TSInfo;
163 AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
164 const TargetMachine &TM);
165 ~AMDGPUSubtarget() override;
167 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
168 StringRef GPU, StringRef FS);
170 const AMDGPUInstrInfo *getInstrInfo() const override = 0;
171 const AMDGPUFrameLowering *getFrameLowering() const override = 0;
172 const AMDGPUTargetLowering *getTargetLowering() const override = 0;
173 const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
175 const InstrItineraryData *getInstrItineraryData() const override {
179 // Nothing implemented, just prevent crashes on use.
180 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
184 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
186 bool isAmdHsaOS() const {
187 return TargetTriple.getOS() == Triple::AMDHSA;
190 bool isMesa3DOS() const {
191 return TargetTriple.getOS() == Triple::Mesa3D;
194 bool isOpenCLEnv() const {
195 return TargetTriple.getEnvironment() == Triple::OpenCL;
198 Generation getGeneration() const {
202 unsigned getWavefrontSize() const {
203 return WavefrontSize;
206 int getLocalMemorySize() const {
207 return LocalMemorySize;
210 int getLDSBankCount() const {
214 unsigned getMaxPrivateElementSize() const {
215 return MaxPrivateElementSize;
218 AMDGPUAS getAMDGPUAS() const {
222 bool has16BitInsts() const {
223 return Has16BitInsts;
226 bool hasVOP3PInsts() const {
227 return HasVOP3PInsts;
230 bool hasHWFP64() const {
234 bool hasFastFMAF32() const {
238 bool hasHalfRate64Ops() const {
239 return HalfRate64Ops;
242 bool hasAddr64() const {
243 return (getGeneration() < VOLCANIC_ISLANDS);
246 bool hasBFE() const {
247 return (getGeneration() >= EVERGREEN);
250 bool hasBFI() const {
251 return (getGeneration() >= EVERGREEN);
254 bool hasBFM() const {
258 bool hasBCNT(unsigned Size) const {
260 return (getGeneration() >= EVERGREEN);
263 return (getGeneration() >= SOUTHERN_ISLANDS);
268 bool hasMulU24() const {
269 return (getGeneration() >= EVERGREEN);
272 bool hasMulI24() const {
273 return (getGeneration() >= SOUTHERN_ISLANDS ||
277 bool hasFFBL() const {
278 return (getGeneration() >= EVERGREEN);
281 bool hasFFBH() const {
282 return (getGeneration() >= EVERGREEN);
285 bool hasMed3_16() const {
286 return getGeneration() >= GFX9;
289 bool hasCARRY() const {
290 return (getGeneration() >= EVERGREEN);
293 bool hasBORROW() const {
294 return (getGeneration() >= EVERGREEN);
297 bool hasCaymanISA() const {
301 TrapHandlerAbi getTrapHandlerAbi() const {
302 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
305 bool isPromoteAllocaEnabled() const {
306 return EnablePromoteAlloca;
309 bool unsafeDSOffsetFoldingEnabled() const {
310 return EnableUnsafeDSOffsetFolding;
313 bool dumpCode() const {
317 /// Return the amount of LDS that can be used that will not restrict the
318 /// occupancy lower than WaveCount.
319 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
320 const Function &) const;
322 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
323 /// the given LDS memory size is the only constraint.
324 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
326 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const {
327 const auto *MFI = MF.getInfo<SIMachineFunctionInfo>();
328 return getOccupancyWithLocalMemSize(MFI->getLDSSize(), *MF.getFunction());
331 bool hasFP16Denormals() const {
332 return FP64FP16Denormals;
335 bool hasFP32Denormals() const {
336 return FP32Denormals;
339 bool hasFP64Denormals() const {
340 return FP64FP16Denormals;
343 bool hasFPExceptions() const {
347 bool enableDX10Clamp() const {
351 bool enableIEEEBit(const MachineFunction &MF) const {
352 return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
355 bool useFlatForGlobal() const {
356 return FlatForGlobal;
359 bool hasUnalignedBufferAccess() const {
360 return UnalignedBufferAccess;
363 bool hasUnalignedScratchAccess() const {
364 return UnalignedScratchAccess;
367 bool hasApertureRegs() const {
368 return HasApertureRegs;
371 bool isTrapHandlerEnabled() const {
375 bool isXNACKEnabled() const {
379 bool hasFlatAddressSpace() const {
380 return FlatAddressSpace;
383 bool isMesaKernel(const MachineFunction &MF) const {
384 return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
387 // Covers VS/PS/CS graphics shaders
388 bool isMesaGfxShader(const MachineFunction &MF) const {
389 return isMesa3DOS() && AMDGPU::isShader(MF.getFunction()->getCallingConv());
392 bool isAmdCodeObjectV2(const MachineFunction &MF) const {
393 return isAmdHsaOS() || isMesaKernel(MF);
396 bool hasFminFmaxLegacy() const {
397 return getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
400 /// \brief Returns the offset in bytes from the start of the input buffer
401 /// of the first explicit kernel argument.
402 unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
403 return isAmdCodeObjectV2(MF) ? 0 : 36;
406 unsigned getAlignmentForImplicitArgPtr() const {
407 return isAmdHsaOS() ? 8 : 4;
410 unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
411 if (isMesaKernel(MF))
413 if (isAmdHsaOS() && isOpenCLEnv())
418 // Scratch is allocated in 256 dword per wave blocks for the entire
419 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
420 // is 4-byte aligned.
421 unsigned getStackAlignment() const {
425 bool enableMachineScheduler() const override {
429 bool enableSubRegLiveness() const override {
433 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
434 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
436 /// \returns Number of execution units per compute unit supported by the
438 unsigned getEUsPerCU() const {
439 return AMDGPU::IsaInfo::getEUsPerCU(getFeatureBits());
442 /// \returns Maximum number of work groups per compute unit supported by the
443 /// subtarget and limited by given \p FlatWorkGroupSize.
444 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
445 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(getFeatureBits(),
449 /// \returns Maximum number of waves per compute unit supported by the
450 /// subtarget without any kind of limitation.
451 unsigned getMaxWavesPerCU() const {
452 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits());
455 /// \returns Maximum number of waves per compute unit supported by the
456 /// subtarget and limited by given \p FlatWorkGroupSize.
457 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
458 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits(),
462 /// \returns Minimum number of waves per execution unit supported by the
464 unsigned getMinWavesPerEU() const {
465 return AMDGPU::IsaInfo::getMinWavesPerEU(getFeatureBits());
468 /// \returns Maximum number of waves per execution unit supported by the
469 /// subtarget without any kind of limitation.
470 unsigned getMaxWavesPerEU() const {
471 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits());
474 /// \returns Maximum number of waves per execution unit supported by the
475 /// subtarget and limited by given \p FlatWorkGroupSize.
476 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
477 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits(),
481 /// \returns Minimum flat work group size supported by the subtarget.
482 unsigned getMinFlatWorkGroupSize() const {
483 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(getFeatureBits());
486 /// \returns Maximum flat work group size supported by the subtarget.
487 unsigned getMaxFlatWorkGroupSize() const {
488 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(getFeatureBits());
491 /// \returns Number of waves per work group supported by the subtarget and
492 /// limited by given \p FlatWorkGroupSize.
493 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
494 return AMDGPU::IsaInfo::getWavesPerWorkGroup(getFeatureBits(),
498 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
499 /// for function \p F, or minimum/maximum flat work group sizes explicitly
500 /// requested using "amdgpu-flat-work-group-size" attribute attached to
503 /// \returns Subtarget's default values if explicitly requested values cannot
504 /// be converted to integer, or violate subtarget's specifications.
505 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
507 /// \returns Subtarget's default pair of minimum/maximum number of waves per
508 /// execution unit for function \p F, or minimum/maximum number of waves per
509 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
510 /// attached to function \p F.
512 /// \returns Subtarget's default values if explicitly requested values cannot
513 /// be converted to integer, violate subtarget's specifications, or are not
514 /// compatible with minimum/maximum number of waves limited by flat work group
515 /// size, register usage, and/or lds usage.
516 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
518 /// Creates value range metadata on an workitemid.* inrinsic call or load.
519 bool makeLIDRangeMetadata(Instruction *I) const;
522 class R600Subtarget final : public AMDGPUSubtarget {
524 R600InstrInfo InstrInfo;
525 R600FrameLowering FrameLowering;
526 R600TargetLowering TLInfo;
529 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
530 const TargetMachine &TM);
532 const R600InstrInfo *getInstrInfo() const override {
536 const R600FrameLowering *getFrameLowering() const override {
537 return &FrameLowering;
540 const R600TargetLowering *getTargetLowering() const override {
544 const R600RegisterInfo *getRegisterInfo() const override {
545 return &InstrInfo.getRegisterInfo();
548 bool hasCFAluBug() const {
552 bool hasVertexCache() const {
553 return HasVertexCache;
556 short getTexVTXClauseSize() const {
557 return TexVTXClauseSize;
561 class SISubtarget final : public AMDGPUSubtarget {
563 SIInstrInfo InstrInfo;
564 SIFrameLowering FrameLowering;
565 SITargetLowering TLInfo;
566 std::unique_ptr<GISelAccessor> GISel;
569 SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
570 const TargetMachine &TM);
572 const SIInstrInfo *getInstrInfo() const override {
576 const SIFrameLowering *getFrameLowering() const override {
577 return &FrameLowering;
580 const SITargetLowering *getTargetLowering() const override {
584 const CallLowering *getCallLowering() const override {
585 assert(GISel && "Access to GlobalISel APIs not set");
586 return GISel->getCallLowering();
589 const InstructionSelector *getInstructionSelector() const override {
590 assert(GISel && "Access to GlobalISel APIs not set");
591 return GISel->getInstructionSelector();
594 const LegalizerInfo *getLegalizerInfo() const override {
595 assert(GISel && "Access to GlobalISel APIs not set");
596 return GISel->getLegalizerInfo();
599 const RegisterBankInfo *getRegBankInfo() const override {
600 assert(GISel && "Access to GlobalISel APIs not set");
601 return GISel->getRegBankInfo();
604 const SIRegisterInfo *getRegisterInfo() const override {
605 return &InstrInfo.getRegisterInfo();
608 void setGISelAccessor(GISelAccessor &GISel) {
609 this->GISel.reset(&GISel);
612 // XXX - Why is this here if it isn't in the default pass set?
613 bool enableEarlyIfConversion() const override {
617 void overrideSchedPolicy(MachineSchedPolicy &Policy,
618 unsigned NumRegionInstrs) const override;
620 bool isVGPRSpillingEnabled(const Function& F) const;
622 unsigned getMaxNumUserSGPRs() const {
626 bool hasSMemRealTime() const {
627 return HasSMemRealTime;
630 bool hasMovrel() const {
634 bool hasVGPRIndexMode() const {
635 return HasVGPRIndexMode;
638 bool useVGPRIndexMode(bool UserEnable) const {
639 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
642 bool hasScalarCompareEq64() const {
643 return getGeneration() >= VOLCANIC_ISLANDS;
646 bool hasScalarStores() const {
647 return HasScalarStores;
650 bool hasInv2PiInlineImm() const {
651 return HasInv2PiInlineImm;
654 bool hasSDWA() const {
658 bool hasDPP() const {
662 bool enableSIScheduler() const {
663 return EnableSIScheduler;
666 bool debuggerSupported() const {
667 return debuggerInsertNops() && debuggerReserveRegs() &&
668 debuggerEmitPrologue();
671 bool debuggerInsertNops() const {
672 return DebuggerInsertNops;
675 bool debuggerReserveRegs() const {
676 return DebuggerReserveRegs;
679 bool debuggerEmitPrologue() const {
680 return DebuggerEmitPrologue;
683 bool loadStoreOptEnabled() const {
684 return EnableLoadStoreOpt;
687 bool hasSGPRInitBug() const {
691 bool has12DWordStoreHazard() const {
692 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
695 bool hasSMovFedHazard() const {
696 return getGeneration() >= AMDGPUSubtarget::GFX9;
699 bool hasReadM0Hazard() const {
700 return getGeneration() >= AMDGPUSubtarget::GFX9;
703 unsigned getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const;
705 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
706 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
708 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
709 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
711 /// \returns True if waitcnt instruction is needed before barrier instruction,
713 bool needWaitcntBeforeBarrier() const {
714 return getGeneration() < GFX9;
717 /// \returns true if the flat_scratch register should be initialized with the
718 /// pointer to the wave's scratch memory rather than a size and offset.
719 bool flatScratchIsPointer() const {
720 return getGeneration() >= GFX9;
723 /// \returns SGPR allocation granularity supported by the subtarget.
724 unsigned getSGPRAllocGranule() const {
725 return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
728 /// \returns SGPR encoding granularity supported by the subtarget.
729 unsigned getSGPREncodingGranule() const {
730 return AMDGPU::IsaInfo::getSGPREncodingGranule(getFeatureBits());
733 /// \returns Total number of SGPRs supported by the subtarget.
734 unsigned getTotalNumSGPRs() const {
735 return AMDGPU::IsaInfo::getTotalNumSGPRs(getFeatureBits());
738 /// \returns Addressable number of SGPRs supported by the subtarget.
739 unsigned getAddressableNumSGPRs() const {
740 return AMDGPU::IsaInfo::getAddressableNumSGPRs(getFeatureBits());
743 /// \returns Minimum number of SGPRs that meets the given number of waves per
744 /// execution unit requirement supported by the subtarget.
745 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
746 return AMDGPU::IsaInfo::getMinNumSGPRs(getFeatureBits(), WavesPerEU);
749 /// \returns Maximum number of SGPRs that meets the given number of waves per
750 /// execution unit requirement supported by the subtarget.
751 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
752 return AMDGPU::IsaInfo::getMaxNumSGPRs(getFeatureBits(), WavesPerEU,
756 /// \returns Reserved number of SGPRs for given function \p MF.
757 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
759 /// \returns Maximum number of SGPRs that meets number of waves per execution
760 /// unit requirement for function \p MF, or number of SGPRs explicitly
761 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
763 /// \returns Value that meets number of waves per execution unit requirement
764 /// if explicitly requested value cannot be converted to integer, violates
765 /// subtarget's specifications, or does not meet number of waves per execution
766 /// unit requirement.
767 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
769 /// \returns VGPR allocation granularity supported by the subtarget.
770 unsigned getVGPRAllocGranule() const {
771 return AMDGPU::IsaInfo::getVGPRAllocGranule(getFeatureBits());;
774 /// \returns VGPR encoding granularity supported by the subtarget.
775 unsigned getVGPREncodingGranule() const {
776 return AMDGPU::IsaInfo::getVGPREncodingGranule(getFeatureBits());
779 /// \returns Total number of VGPRs supported by the subtarget.
780 unsigned getTotalNumVGPRs() const {
781 return AMDGPU::IsaInfo::getTotalNumVGPRs(getFeatureBits());
784 /// \returns Addressable number of VGPRs supported by the subtarget.
785 unsigned getAddressableNumVGPRs() const {
786 return AMDGPU::IsaInfo::getAddressableNumVGPRs(getFeatureBits());
789 /// \returns Minimum number of VGPRs that meets given number of waves per
790 /// execution unit requirement supported by the subtarget.
791 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
792 return AMDGPU::IsaInfo::getMinNumVGPRs(getFeatureBits(), WavesPerEU);
795 /// \returns Maximum number of VGPRs that meets given number of waves per
796 /// execution unit requirement supported by the subtarget.
797 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
798 return AMDGPU::IsaInfo::getMaxNumVGPRs(getFeatureBits(), WavesPerEU);
801 /// \returns Reserved number of VGPRs for given function \p MF.
802 unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
803 return debuggerReserveRegs() ? 4 : 0;
806 /// \returns Maximum number of VGPRs that meets number of waves per execution
807 /// unit requirement for function \p MF, or number of VGPRs explicitly
808 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
810 /// \returns Value that meets number of waves per execution unit requirement
811 /// if explicitly requested value cannot be converted to integer, violates
812 /// subtarget's specifications, or does not meet number of waves per execution
813 /// unit requirement.
814 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
817 } // end namespace llvm
819 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H