1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "R600InstrInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600FrameLowering.h"
22 #include "SIInstrInfo.h"
23 #include "SIISelLowering.h"
24 #include "SIFrameLowering.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "Utils/AMDGPUBaseInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/MathExtras.h"
38 #define GET_SUBTARGETINFO_HEADER
39 #include "AMDGPUGenSubtargetInfo.inc"
45 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
74 TrapHandlerAbiNone = 0,
79 TrapIDHardwareReserved = 0,
80 TrapIDHSADebugTrap = 1,
82 TrapIDLLVMDebugTrap = 3,
83 TrapIDDebugBreakpoint = 7,
84 TrapIDDebugReserved8 = 8,
85 TrapIDDebugReservedFE = 0xfe,
86 TrapIDDebugReservedFF = 0xff
90 LLVMTrapHandlerRegValue = 1
94 // Basic subtarget description.
98 unsigned WavefrontSize;
101 unsigned MaxPrivateElementSize;
103 // Possibly statically set by tablegen, but may want to be overridden.
107 // Dynamially set bits that enable features.
109 bool FP64FP16Denormals;
113 bool UnalignedScratchAccess;
114 bool UnalignedBufferAccess;
115 bool HasApertureRegs;
118 bool DebuggerInsertNops;
119 bool DebuggerReserveRegs;
120 bool DebuggerEmitPrologue;
123 bool EnableVGPRSpilling;
124 bool EnablePromoteAlloca;
125 bool EnableLoadStoreOpt;
126 bool EnableUnsafeDSOffsetFolding;
127 bool EnableSIScheduler;
130 // Subtarget statically properties set by tablegen
138 bool HasSMemRealTime;
142 bool HasVGPRIndexMode;
143 bool HasScalarStores;
144 bool HasInv2PiInlineImm;
147 bool FlatAddressSpace;
148 bool FlatInstOffsets;
149 bool FlatGlobalInsts;
150 bool FlatScratchInsts;
155 short TexVTXClauseSize;
156 bool ScalarizeGlobal;
158 // Dummy feature to use for assembler in tablegen.
161 InstrItineraryData InstrItins;
162 SelectionDAGTargetInfo TSInfo;
166 AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
167 const TargetMachine &TM);
168 ~AMDGPUSubtarget() override;
170 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
171 StringRef GPU, StringRef FS);
173 const AMDGPUInstrInfo *getInstrInfo() const override = 0;
174 const AMDGPUFrameLowering *getFrameLowering() const override = 0;
175 const AMDGPUTargetLowering *getTargetLowering() const override = 0;
176 const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
178 const InstrItineraryData *getInstrItineraryData() const override {
182 // Nothing implemented, just prevent crashes on use.
183 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
187 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
189 bool isAmdHsaOS() const {
190 return TargetTriple.getOS() == Triple::AMDHSA;
193 bool isMesa3DOS() const {
194 return TargetTriple.getOS() == Triple::Mesa3D;
197 bool isOpenCLEnv() const {
198 return TargetTriple.getEnvironment() == Triple::OpenCL;
201 Generation getGeneration() const {
205 unsigned getWavefrontSize() const {
206 return WavefrontSize;
209 int getLocalMemorySize() const {
210 return LocalMemorySize;
213 int getLDSBankCount() const {
217 unsigned getMaxPrivateElementSize() const {
218 return MaxPrivateElementSize;
221 AMDGPUAS getAMDGPUAS() const {
225 bool has16BitInsts() const {
226 return Has16BitInsts;
229 bool hasVOP3PInsts() const {
230 return HasVOP3PInsts;
233 bool hasHWFP64() const {
237 bool hasFastFMAF32() const {
241 bool hasHalfRate64Ops() const {
242 return HalfRate64Ops;
245 bool hasAddr64() const {
246 return (getGeneration() < VOLCANIC_ISLANDS);
249 bool hasBFE() const {
250 return (getGeneration() >= EVERGREEN);
253 bool hasBFI() const {
254 return (getGeneration() >= EVERGREEN);
257 bool hasBFM() const {
261 bool hasBCNT(unsigned Size) const {
263 return (getGeneration() >= EVERGREEN);
266 return (getGeneration() >= SOUTHERN_ISLANDS);
271 bool hasMulU24() const {
272 return (getGeneration() >= EVERGREEN);
275 bool hasMulI24() const {
276 return (getGeneration() >= SOUTHERN_ISLANDS ||
280 bool hasFFBL() const {
281 return (getGeneration() >= EVERGREEN);
284 bool hasFFBH() const {
285 return (getGeneration() >= EVERGREEN);
288 bool hasMed3_16() const {
289 return getGeneration() >= GFX9;
292 bool hasMin3Max3_16() const {
293 return getGeneration() >= GFX9;
296 bool hasCARRY() const {
297 return (getGeneration() >= EVERGREEN);
300 bool hasBORROW() const {
301 return (getGeneration() >= EVERGREEN);
304 bool hasCaymanISA() const {
308 TrapHandlerAbi getTrapHandlerAbi() const {
309 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
312 bool isPromoteAllocaEnabled() const {
313 return EnablePromoteAlloca;
316 bool unsafeDSOffsetFoldingEnabled() const {
317 return EnableUnsafeDSOffsetFolding;
320 bool dumpCode() const {
324 /// Return the amount of LDS that can be used that will not restrict the
325 /// occupancy lower than WaveCount.
326 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
327 const Function &) const;
329 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
330 /// the given LDS memory size is the only constraint.
331 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
333 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const {
334 const auto *MFI = MF.getInfo<SIMachineFunctionInfo>();
335 return getOccupancyWithLocalMemSize(MFI->getLDSSize(), *MF.getFunction());
338 bool hasFP16Denormals() const {
339 return FP64FP16Denormals;
342 bool hasFP32Denormals() const {
343 return FP32Denormals;
346 bool hasFP64Denormals() const {
347 return FP64FP16Denormals;
350 bool hasFPExceptions() const {
354 bool enableDX10Clamp() const {
358 bool enableIEEEBit(const MachineFunction &MF) const {
359 return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
362 bool useFlatForGlobal() const {
363 return FlatForGlobal;
366 bool hasUnalignedBufferAccess() const {
367 return UnalignedBufferAccess;
370 bool hasUnalignedScratchAccess() const {
371 return UnalignedScratchAccess;
374 bool hasApertureRegs() const {
375 return HasApertureRegs;
378 bool isTrapHandlerEnabled() const {
382 bool isXNACKEnabled() const {
386 bool hasFlatAddressSpace() const {
387 return FlatAddressSpace;
390 bool hasFlatInstOffsets() const {
391 return FlatInstOffsets;
394 bool hasFlatGlobalInsts() const {
395 return FlatGlobalInsts;
398 bool hasFlatScratchInsts() const {
399 return FlatScratchInsts;
402 bool isMesaKernel(const MachineFunction &MF) const {
403 return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
406 // Covers VS/PS/CS graphics shaders
407 bool isMesaGfxShader(const MachineFunction &MF) const {
408 return isMesa3DOS() && AMDGPU::isShader(MF.getFunction()->getCallingConv());
411 bool isAmdCodeObjectV2(const MachineFunction &MF) const {
412 return isAmdHsaOS() || isMesaKernel(MF);
415 bool hasFminFmaxLegacy() const {
416 return getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
419 bool hasSDWA() const {
423 /// \brief Returns the offset in bytes from the start of the input buffer
424 /// of the first explicit kernel argument.
425 unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
426 return isAmdCodeObjectV2(MF) ? 0 : 36;
429 unsigned getAlignmentForImplicitArgPtr() const {
430 return isAmdHsaOS() ? 8 : 4;
433 unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
434 if (isMesaKernel(MF))
436 if (isAmdHsaOS() && isOpenCLEnv())
441 // Scratch is allocated in 256 dword per wave blocks for the entire
442 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
443 // is 4-byte aligned.
444 unsigned getStackAlignment() const {
448 bool enableMachineScheduler() const override {
452 bool enableSubRegLiveness() const override {
456 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
457 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
459 /// \returns Number of execution units per compute unit supported by the
461 unsigned getEUsPerCU() const {
462 return AMDGPU::IsaInfo::getEUsPerCU(getFeatureBits());
465 /// \returns Maximum number of work groups per compute unit supported by the
466 /// subtarget and limited by given \p FlatWorkGroupSize.
467 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
468 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(getFeatureBits(),
472 /// \returns Maximum number of waves per compute unit supported by the
473 /// subtarget without any kind of limitation.
474 unsigned getMaxWavesPerCU() const {
475 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits());
478 /// \returns Maximum number of waves per compute unit supported by the
479 /// subtarget and limited by given \p FlatWorkGroupSize.
480 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
481 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits(),
485 /// \returns Minimum number of waves per execution unit supported by the
487 unsigned getMinWavesPerEU() const {
488 return AMDGPU::IsaInfo::getMinWavesPerEU(getFeatureBits());
491 /// \returns Maximum number of waves per execution unit supported by the
492 /// subtarget without any kind of limitation.
493 unsigned getMaxWavesPerEU() const {
494 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits());
497 /// \returns Maximum number of waves per execution unit supported by the
498 /// subtarget and limited by given \p FlatWorkGroupSize.
499 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
500 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits(),
504 /// \returns Minimum flat work group size supported by the subtarget.
505 unsigned getMinFlatWorkGroupSize() const {
506 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(getFeatureBits());
509 /// \returns Maximum flat work group size supported by the subtarget.
510 unsigned getMaxFlatWorkGroupSize() const {
511 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(getFeatureBits());
514 /// \returns Number of waves per work group supported by the subtarget and
515 /// limited by given \p FlatWorkGroupSize.
516 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
517 return AMDGPU::IsaInfo::getWavesPerWorkGroup(getFeatureBits(),
521 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
522 /// for function \p F, or minimum/maximum flat work group sizes explicitly
523 /// requested using "amdgpu-flat-work-group-size" attribute attached to
526 /// \returns Subtarget's default values if explicitly requested values cannot
527 /// be converted to integer, or violate subtarget's specifications.
528 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
530 /// \returns Subtarget's default pair of minimum/maximum number of waves per
531 /// execution unit for function \p F, or minimum/maximum number of waves per
532 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
533 /// attached to function \p F.
535 /// \returns Subtarget's default values if explicitly requested values cannot
536 /// be converted to integer, violate subtarget's specifications, or are not
537 /// compatible with minimum/maximum number of waves limited by flat work group
538 /// size, register usage, and/or lds usage.
539 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
541 /// Creates value range metadata on an workitemid.* inrinsic call or load.
542 bool makeLIDRangeMetadata(Instruction *I) const;
545 class R600Subtarget final : public AMDGPUSubtarget {
547 R600InstrInfo InstrInfo;
548 R600FrameLowering FrameLowering;
549 R600TargetLowering TLInfo;
552 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
553 const TargetMachine &TM);
555 const R600InstrInfo *getInstrInfo() const override {
559 const R600FrameLowering *getFrameLowering() const override {
560 return &FrameLowering;
563 const R600TargetLowering *getTargetLowering() const override {
567 const R600RegisterInfo *getRegisterInfo() const override {
568 return &InstrInfo.getRegisterInfo();
571 bool hasCFAluBug() const {
575 bool hasVertexCache() const {
576 return HasVertexCache;
579 short getTexVTXClauseSize() const {
580 return TexVTXClauseSize;
584 class SISubtarget final : public AMDGPUSubtarget {
586 SIInstrInfo InstrInfo;
587 SIFrameLowering FrameLowering;
588 SITargetLowering TLInfo;
589 std::unique_ptr<GISelAccessor> GISel;
592 SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
593 const TargetMachine &TM);
595 const SIInstrInfo *getInstrInfo() const override {
599 const SIFrameLowering *getFrameLowering() const override {
600 return &FrameLowering;
603 const SITargetLowering *getTargetLowering() const override {
607 const CallLowering *getCallLowering() const override {
608 assert(GISel && "Access to GlobalISel APIs not set");
609 return GISel->getCallLowering();
612 const InstructionSelector *getInstructionSelector() const override {
613 assert(GISel && "Access to GlobalISel APIs not set");
614 return GISel->getInstructionSelector();
617 const LegalizerInfo *getLegalizerInfo() const override {
618 assert(GISel && "Access to GlobalISel APIs not set");
619 return GISel->getLegalizerInfo();
622 const RegisterBankInfo *getRegBankInfo() const override {
623 assert(GISel && "Access to GlobalISel APIs not set");
624 return GISel->getRegBankInfo();
627 const SIRegisterInfo *getRegisterInfo() const override {
628 return &InstrInfo.getRegisterInfo();
631 void setGISelAccessor(GISelAccessor &GISel) {
632 this->GISel.reset(&GISel);
635 // XXX - Why is this here if it isn't in the default pass set?
636 bool enableEarlyIfConversion() const override {
640 void overrideSchedPolicy(MachineSchedPolicy &Policy,
641 unsigned NumRegionInstrs) const override;
643 bool isVGPRSpillingEnabled(const Function& F) const;
645 unsigned getMaxNumUserSGPRs() const {
649 bool hasSMemRealTime() const {
650 return HasSMemRealTime;
653 bool hasMovrel() const {
657 bool hasVGPRIndexMode() const {
658 return HasVGPRIndexMode;
661 bool useVGPRIndexMode(bool UserEnable) const {
662 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
665 bool hasScalarCompareEq64() const {
666 return getGeneration() >= VOLCANIC_ISLANDS;
669 bool hasScalarStores() const {
670 return HasScalarStores;
673 bool hasInv2PiInlineImm() const {
674 return HasInv2PiInlineImm;
677 bool hasDPP() const {
681 bool enableSIScheduler() const {
682 return EnableSIScheduler;
685 bool debuggerSupported() const {
686 return debuggerInsertNops() && debuggerReserveRegs() &&
687 debuggerEmitPrologue();
690 bool debuggerInsertNops() const {
691 return DebuggerInsertNops;
694 bool debuggerReserveRegs() const {
695 return DebuggerReserveRegs;
698 bool debuggerEmitPrologue() const {
699 return DebuggerEmitPrologue;
702 bool loadStoreOptEnabled() const {
703 return EnableLoadStoreOpt;
706 bool hasSGPRInitBug() const {
710 bool has12DWordStoreHazard() const {
711 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
714 bool hasSMovFedHazard() const {
715 return getGeneration() >= AMDGPUSubtarget::GFX9;
718 bool hasReadM0Hazard() const {
719 return getGeneration() >= AMDGPUSubtarget::GFX9;
722 unsigned getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const;
724 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
725 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
727 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
728 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
730 /// \returns True if waitcnt instruction is needed before barrier instruction,
732 bool needWaitcntBeforeBarrier() const {
736 /// \returns true if the flat_scratch register should be initialized with the
737 /// pointer to the wave's scratch memory rather than a size and offset.
738 bool flatScratchIsPointer() const {
739 return getGeneration() >= GFX9;
742 /// \returns SGPR allocation granularity supported by the subtarget.
743 unsigned getSGPRAllocGranule() const {
744 return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
747 /// \returns SGPR encoding granularity supported by the subtarget.
748 unsigned getSGPREncodingGranule() const {
749 return AMDGPU::IsaInfo::getSGPREncodingGranule(getFeatureBits());
752 /// \returns Total number of SGPRs supported by the subtarget.
753 unsigned getTotalNumSGPRs() const {
754 return AMDGPU::IsaInfo::getTotalNumSGPRs(getFeatureBits());
757 /// \returns Addressable number of SGPRs supported by the subtarget.
758 unsigned getAddressableNumSGPRs() const {
759 return AMDGPU::IsaInfo::getAddressableNumSGPRs(getFeatureBits());
762 /// \returns Minimum number of SGPRs that meets the given number of waves per
763 /// execution unit requirement supported by the subtarget.
764 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
765 return AMDGPU::IsaInfo::getMinNumSGPRs(getFeatureBits(), WavesPerEU);
768 /// \returns Maximum number of SGPRs that meets the given number of waves per
769 /// execution unit requirement supported by the subtarget.
770 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
771 return AMDGPU::IsaInfo::getMaxNumSGPRs(getFeatureBits(), WavesPerEU,
775 /// \returns Reserved number of SGPRs for given function \p MF.
776 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
778 /// \returns Maximum number of SGPRs that meets number of waves per execution
779 /// unit requirement for function \p MF, or number of SGPRs explicitly
780 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
782 /// \returns Value that meets number of waves per execution unit requirement
783 /// if explicitly requested value cannot be converted to integer, violates
784 /// subtarget's specifications, or does not meet number of waves per execution
785 /// unit requirement.
786 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
788 /// \returns VGPR allocation granularity supported by the subtarget.
789 unsigned getVGPRAllocGranule() const {
790 return AMDGPU::IsaInfo::getVGPRAllocGranule(getFeatureBits());;
793 /// \returns VGPR encoding granularity supported by the subtarget.
794 unsigned getVGPREncodingGranule() const {
795 return AMDGPU::IsaInfo::getVGPREncodingGranule(getFeatureBits());
798 /// \returns Total number of VGPRs supported by the subtarget.
799 unsigned getTotalNumVGPRs() const {
800 return AMDGPU::IsaInfo::getTotalNumVGPRs(getFeatureBits());
803 /// \returns Addressable number of VGPRs supported by the subtarget.
804 unsigned getAddressableNumVGPRs() const {
805 return AMDGPU::IsaInfo::getAddressableNumVGPRs(getFeatureBits());
808 /// \returns Minimum number of VGPRs that meets given number of waves per
809 /// execution unit requirement supported by the subtarget.
810 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
811 return AMDGPU::IsaInfo::getMinNumVGPRs(getFeatureBits(), WavesPerEU);
814 /// \returns Maximum number of VGPRs that meets given number of waves per
815 /// execution unit requirement supported by the subtarget.
816 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
817 return AMDGPU::IsaInfo::getMaxNumVGPRs(getFeatureBits(), WavesPerEU);
820 /// \returns Reserved number of VGPRs for given function \p MF.
821 unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
822 return debuggerReserveRegs() ? 4 : 0;
825 /// \returns Maximum number of VGPRs that meets number of waves per execution
826 /// unit requirement for function \p MF, or number of VGPRs explicitly
827 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
829 /// \returns Value that meets number of waves per execution unit requirement
830 /// if explicitly requested value cannot be converted to integer, violates
831 /// subtarget's specifications, or does not meet number of waves per execution
832 /// unit requirement.
833 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
836 } // end namespace llvm
838 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H