1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "R600FrameLowering.h"
20 #include "R600ISelLowering.h"
21 #include "R600InstrInfo.h"
22 #include "SIFrameLowering.h"
23 #include "SIISelLowering.h"
24 #include "SIInstrInfo.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "Utils/AMDGPUBaseInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/MathExtras.h"
38 #define GET_SUBTARGETINFO_HEADER
39 #include "AMDGPUGenSubtargetInfo.inc"
45 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
79 TrapHandlerAbiNone = 0,
84 TrapIDHardwareReserved = 0,
85 TrapIDHSADebugTrap = 1,
87 TrapIDLLVMDebugTrap = 3,
88 TrapIDDebugBreakpoint = 7,
89 TrapIDDebugReserved8 = 8,
90 TrapIDDebugReservedFE = 0xfe,
91 TrapIDDebugReservedFF = 0xff
95 LLVMTrapHandlerRegValue = 1
99 // Basic subtarget description.
103 unsigned WavefrontSize;
106 unsigned MaxPrivateElementSize;
108 // Possibly statically set by tablegen, but may want to be overridden.
112 // Dynamially set bits that enable features.
114 bool FP64FP16Denormals;
118 bool AutoWaitcntBeforeBarrier;
119 bool UnalignedScratchAccess;
120 bool UnalignedBufferAccess;
121 bool HasApertureRegs;
124 bool DebuggerInsertNops;
125 bool DebuggerReserveRegs;
126 bool DebuggerEmitPrologue;
129 bool EnableVGPRSpilling;
130 bool EnablePromoteAlloca;
131 bool EnableLoadStoreOpt;
132 bool EnableUnsafeDSOffsetFolding;
133 bool EnableSIScheduler;
136 // Subtarget statically properties set by tablegen
144 bool HasSMemRealTime;
148 bool HasVGPRIndexMode;
149 bool HasScalarStores;
150 bool HasInv2PiInlineImm;
156 bool HasSDWAOutModsVOPC;
158 bool FlatAddressSpace;
159 bool FlatInstOffsets;
160 bool FlatGlobalInsts;
161 bool FlatScratchInsts;
166 short TexVTXClauseSize;
167 bool ScalarizeGlobal;
169 // Dummy feature to use for assembler in tablegen.
172 InstrItineraryData InstrItins;
173 SelectionDAGTargetInfo TSInfo;
177 AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
178 const TargetMachine &TM);
179 ~AMDGPUSubtarget() override;
181 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
182 StringRef GPU, StringRef FS);
184 const AMDGPUInstrInfo *getInstrInfo() const override = 0;
185 const AMDGPUFrameLowering *getFrameLowering() const override = 0;
186 const AMDGPUTargetLowering *getTargetLowering() const override = 0;
187 const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
189 const InstrItineraryData *getInstrItineraryData() const override {
193 // Nothing implemented, just prevent crashes on use.
194 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
198 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
200 bool isAmdHsaOS() const {
201 return TargetTriple.getOS() == Triple::AMDHSA;
204 bool isMesa3DOS() const {
205 return TargetTriple.getOS() == Triple::Mesa3D;
208 bool isOpenCLEnv() const {
209 return TargetTriple.getEnvironment() == Triple::OpenCL ||
210 TargetTriple.getEnvironmentName() == "amdgizcl";
213 Generation getGeneration() const {
217 unsigned getWavefrontSize() const {
218 return WavefrontSize;
221 int getLocalMemorySize() const {
222 return LocalMemorySize;
225 int getLDSBankCount() const {
229 unsigned getMaxPrivateElementSize() const {
230 return MaxPrivateElementSize;
233 AMDGPUAS getAMDGPUAS() const {
237 bool has16BitInsts() const {
238 return Has16BitInsts;
241 bool hasVOP3PInsts() const {
242 return HasVOP3PInsts;
245 bool hasHWFP64() const {
249 bool hasFastFMAF32() const {
253 bool hasHalfRate64Ops() const {
254 return HalfRate64Ops;
257 bool hasAddr64() const {
258 return (getGeneration() < VOLCANIC_ISLANDS);
261 bool hasBFE() const {
262 return (getGeneration() >= EVERGREEN);
265 bool hasBFI() const {
266 return (getGeneration() >= EVERGREEN);
269 bool hasBFM() const {
273 bool hasBCNT(unsigned Size) const {
275 return (getGeneration() >= EVERGREEN);
278 return (getGeneration() >= SOUTHERN_ISLANDS);
283 bool hasMulU24() const {
284 return (getGeneration() >= EVERGREEN);
287 bool hasMulI24() const {
288 return (getGeneration() >= SOUTHERN_ISLANDS ||
292 bool hasFFBL() const {
293 return (getGeneration() >= EVERGREEN);
296 bool hasFFBH() const {
297 return (getGeneration() >= EVERGREEN);
300 bool hasMed3_16() const {
301 return getGeneration() >= GFX9;
304 bool hasMin3Max3_16() const {
305 return getGeneration() >= GFX9;
308 bool hasCARRY() const {
309 return (getGeneration() >= EVERGREEN);
312 bool hasBORROW() const {
313 return (getGeneration() >= EVERGREEN);
316 bool hasCaymanISA() const {
320 TrapHandlerAbi getTrapHandlerAbi() const {
321 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
324 bool isPromoteAllocaEnabled() const {
325 return EnablePromoteAlloca;
328 bool unsafeDSOffsetFoldingEnabled() const {
329 return EnableUnsafeDSOffsetFolding;
332 bool dumpCode() const {
336 /// Return the amount of LDS that can be used that will not restrict the
337 /// occupancy lower than WaveCount.
338 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
339 const Function &) const;
341 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
342 /// the given LDS memory size is the only constraint.
343 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
345 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const {
346 const auto *MFI = MF.getInfo<SIMachineFunctionInfo>();
347 return getOccupancyWithLocalMemSize(MFI->getLDSSize(), *MF.getFunction());
350 bool hasFP16Denormals() const {
351 return FP64FP16Denormals;
354 bool hasFP32Denormals() const {
355 return FP32Denormals;
358 bool hasFP64Denormals() const {
359 return FP64FP16Denormals;
362 bool hasFPExceptions() const {
366 bool enableDX10Clamp() const {
370 bool enableIEEEBit(const MachineFunction &MF) const {
371 return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
374 bool useFlatForGlobal() const {
375 return FlatForGlobal;
378 bool hasAutoWaitcntBeforeBarrier() const {
379 return AutoWaitcntBeforeBarrier;
382 bool hasUnalignedBufferAccess() const {
383 return UnalignedBufferAccess;
386 bool hasUnalignedScratchAccess() const {
387 return UnalignedScratchAccess;
390 bool hasApertureRegs() const {
391 return HasApertureRegs;
394 bool isTrapHandlerEnabled() const {
398 bool isXNACKEnabled() const {
402 bool hasFlatAddressSpace() const {
403 return FlatAddressSpace;
406 bool hasFlatInstOffsets() const {
407 return FlatInstOffsets;
410 bool hasFlatGlobalInsts() const {
411 return FlatGlobalInsts;
414 bool hasFlatScratchInsts() const {
415 return FlatScratchInsts;
418 bool isMesaKernel(const MachineFunction &MF) const {
419 return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
422 // Covers VS/PS/CS graphics shaders
423 bool isMesaGfxShader(const MachineFunction &MF) const {
424 return isMesa3DOS() && AMDGPU::isShader(MF.getFunction()->getCallingConv());
427 bool isAmdCodeObjectV2(const MachineFunction &MF) const {
428 return isAmdHsaOS() || isMesaKernel(MF);
431 bool hasFminFmaxLegacy() const {
432 return getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
435 bool hasSDWA() const {
439 bool hasSDWAOmod() const {
443 bool hasSDWAScalar() const {
444 return HasSDWAScalar;
447 bool hasSDWASdst() const {
451 bool hasSDWAMac() const {
455 bool hasSDWAOutModsVOPC() const {
456 return HasSDWAOutModsVOPC;
459 /// \brief Returns the offset in bytes from the start of the input buffer
460 /// of the first explicit kernel argument.
461 unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
462 return isAmdCodeObjectV2(MF) ? 0 : 36;
465 unsigned getAlignmentForImplicitArgPtr() const {
466 return isAmdHsaOS() ? 8 : 4;
469 unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
470 if (isMesaKernel(MF))
472 if (isAmdHsaOS() && isOpenCLEnv())
477 // Scratch is allocated in 256 dword per wave blocks for the entire
478 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
479 // is 4-byte aligned.
480 unsigned getStackAlignment() const {
484 bool enableMachineScheduler() const override {
488 bool enableSubRegLiveness() const override {
492 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
493 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
495 /// \returns Number of execution units per compute unit supported by the
497 unsigned getEUsPerCU() const {
498 return AMDGPU::IsaInfo::getEUsPerCU(getFeatureBits());
501 /// \returns Maximum number of work groups per compute unit supported by the
502 /// subtarget and limited by given \p FlatWorkGroupSize.
503 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
504 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(getFeatureBits(),
508 /// \returns Maximum number of waves per compute unit supported by the
509 /// subtarget without any kind of limitation.
510 unsigned getMaxWavesPerCU() const {
511 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits());
514 /// \returns Maximum number of waves per compute unit supported by the
515 /// subtarget and limited by given \p FlatWorkGroupSize.
516 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
517 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits(),
521 /// \returns Minimum number of waves per execution unit supported by the
523 unsigned getMinWavesPerEU() const {
524 return AMDGPU::IsaInfo::getMinWavesPerEU(getFeatureBits());
527 /// \returns Maximum number of waves per execution unit supported by the
528 /// subtarget without any kind of limitation.
529 unsigned getMaxWavesPerEU() const {
530 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits());
533 /// \returns Maximum number of waves per execution unit supported by the
534 /// subtarget and limited by given \p FlatWorkGroupSize.
535 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
536 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits(),
540 /// \returns Minimum flat work group size supported by the subtarget.
541 unsigned getMinFlatWorkGroupSize() const {
542 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(getFeatureBits());
545 /// \returns Maximum flat work group size supported by the subtarget.
546 unsigned getMaxFlatWorkGroupSize() const {
547 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(getFeatureBits());
550 /// \returns Number of waves per work group supported by the subtarget and
551 /// limited by given \p FlatWorkGroupSize.
552 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
553 return AMDGPU::IsaInfo::getWavesPerWorkGroup(getFeatureBits(),
557 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
558 /// for function \p F, or minimum/maximum flat work group sizes explicitly
559 /// requested using "amdgpu-flat-work-group-size" attribute attached to
562 /// \returns Subtarget's default values if explicitly requested values cannot
563 /// be converted to integer, or violate subtarget's specifications.
564 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
566 /// \returns Subtarget's default pair of minimum/maximum number of waves per
567 /// execution unit for function \p F, or minimum/maximum number of waves per
568 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
569 /// attached to function \p F.
571 /// \returns Subtarget's default values if explicitly requested values cannot
572 /// be converted to integer, violate subtarget's specifications, or are not
573 /// compatible with minimum/maximum number of waves limited by flat work group
574 /// size, register usage, and/or lds usage.
575 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
577 /// Creates value range metadata on an workitemid.* inrinsic call or load.
578 bool makeLIDRangeMetadata(Instruction *I) const;
581 class R600Subtarget final : public AMDGPUSubtarget {
583 R600InstrInfo InstrInfo;
584 R600FrameLowering FrameLowering;
585 R600TargetLowering TLInfo;
588 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
589 const TargetMachine &TM);
591 const R600InstrInfo *getInstrInfo() const override {
595 const R600FrameLowering *getFrameLowering() const override {
596 return &FrameLowering;
599 const R600TargetLowering *getTargetLowering() const override {
603 const R600RegisterInfo *getRegisterInfo() const override {
604 return &InstrInfo.getRegisterInfo();
607 bool hasCFAluBug() const {
611 bool hasVertexCache() const {
612 return HasVertexCache;
615 short getTexVTXClauseSize() const {
616 return TexVTXClauseSize;
620 class SISubtarget final : public AMDGPUSubtarget {
622 SIInstrInfo InstrInfo;
623 SIFrameLowering FrameLowering;
624 SITargetLowering TLInfo;
625 std::unique_ptr<GISelAccessor> GISel;
628 SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
629 const TargetMachine &TM);
631 const SIInstrInfo *getInstrInfo() const override {
635 const SIFrameLowering *getFrameLowering() const override {
636 return &FrameLowering;
639 const SITargetLowering *getTargetLowering() const override {
643 const CallLowering *getCallLowering() const override {
644 assert(GISel && "Access to GlobalISel APIs not set");
645 return GISel->getCallLowering();
648 const InstructionSelector *getInstructionSelector() const override {
649 assert(GISel && "Access to GlobalISel APIs not set");
650 return GISel->getInstructionSelector();
653 const LegalizerInfo *getLegalizerInfo() const override {
654 assert(GISel && "Access to GlobalISel APIs not set");
655 return GISel->getLegalizerInfo();
658 const RegisterBankInfo *getRegBankInfo() const override {
659 assert(GISel && "Access to GlobalISel APIs not set");
660 return GISel->getRegBankInfo();
663 const SIRegisterInfo *getRegisterInfo() const override {
664 return &InstrInfo.getRegisterInfo();
667 void setGISelAccessor(GISelAccessor &GISel) {
668 this->GISel.reset(&GISel);
671 // XXX - Why is this here if it isn't in the default pass set?
672 bool enableEarlyIfConversion() const override {
676 void overrideSchedPolicy(MachineSchedPolicy &Policy,
677 unsigned NumRegionInstrs) const override;
679 bool isVGPRSpillingEnabled(const Function& F) const;
681 unsigned getMaxNumUserSGPRs() const {
685 bool hasSMemRealTime() const {
686 return HasSMemRealTime;
689 bool hasMovrel() const {
693 bool hasVGPRIndexMode() const {
694 return HasVGPRIndexMode;
697 bool useVGPRIndexMode(bool UserEnable) const {
698 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
701 bool hasScalarCompareEq64() const {
702 return getGeneration() >= VOLCANIC_ISLANDS;
705 bool hasScalarStores() const {
706 return HasScalarStores;
709 bool hasInv2PiInlineImm() const {
710 return HasInv2PiInlineImm;
713 bool hasDPP() const {
717 bool enableSIScheduler() const {
718 return EnableSIScheduler;
721 bool debuggerSupported() const {
722 return debuggerInsertNops() && debuggerReserveRegs() &&
723 debuggerEmitPrologue();
726 bool debuggerInsertNops() const {
727 return DebuggerInsertNops;
730 bool debuggerReserveRegs() const {
731 return DebuggerReserveRegs;
734 bool debuggerEmitPrologue() const {
735 return DebuggerEmitPrologue;
738 bool loadStoreOptEnabled() const {
739 return EnableLoadStoreOpt;
742 bool hasSGPRInitBug() const {
746 bool has12DWordStoreHazard() const {
747 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
750 bool hasSMovFedHazard() const {
751 return getGeneration() >= AMDGPUSubtarget::GFX9;
754 bool hasReadM0Hazard() const {
755 return getGeneration() >= AMDGPUSubtarget::GFX9;
758 unsigned getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const;
760 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
761 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
763 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
764 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
766 /// \returns true if the flat_scratch register should be initialized with the
767 /// pointer to the wave's scratch memory rather than a size and offset.
768 bool flatScratchIsPointer() const {
769 return getGeneration() >= GFX9;
772 /// \returns SGPR allocation granularity supported by the subtarget.
773 unsigned getSGPRAllocGranule() const {
774 return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
777 /// \returns SGPR encoding granularity supported by the subtarget.
778 unsigned getSGPREncodingGranule() const {
779 return AMDGPU::IsaInfo::getSGPREncodingGranule(getFeatureBits());
782 /// \returns Total number of SGPRs supported by the subtarget.
783 unsigned getTotalNumSGPRs() const {
784 return AMDGPU::IsaInfo::getTotalNumSGPRs(getFeatureBits());
787 /// \returns Addressable number of SGPRs supported by the subtarget.
788 unsigned getAddressableNumSGPRs() const {
789 return AMDGPU::IsaInfo::getAddressableNumSGPRs(getFeatureBits());
792 /// \returns Minimum number of SGPRs that meets the given number of waves per
793 /// execution unit requirement supported by the subtarget.
794 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
795 return AMDGPU::IsaInfo::getMinNumSGPRs(getFeatureBits(), WavesPerEU);
798 /// \returns Maximum number of SGPRs that meets the given number of waves per
799 /// execution unit requirement supported by the subtarget.
800 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
801 return AMDGPU::IsaInfo::getMaxNumSGPRs(getFeatureBits(), WavesPerEU,
805 /// \returns Reserved number of SGPRs for given function \p MF.
806 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
808 /// \returns Maximum number of SGPRs that meets number of waves per execution
809 /// unit requirement for function \p MF, or number of SGPRs explicitly
810 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
812 /// \returns Value that meets number of waves per execution unit requirement
813 /// if explicitly requested value cannot be converted to integer, violates
814 /// subtarget's specifications, or does not meet number of waves per execution
815 /// unit requirement.
816 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
818 /// \returns VGPR allocation granularity supported by the subtarget.
819 unsigned getVGPRAllocGranule() const {
820 return AMDGPU::IsaInfo::getVGPRAllocGranule(getFeatureBits());
823 /// \returns VGPR encoding granularity supported by the subtarget.
824 unsigned getVGPREncodingGranule() const {
825 return AMDGPU::IsaInfo::getVGPREncodingGranule(getFeatureBits());
828 /// \returns Total number of VGPRs supported by the subtarget.
829 unsigned getTotalNumVGPRs() const {
830 return AMDGPU::IsaInfo::getTotalNumVGPRs(getFeatureBits());
833 /// \returns Addressable number of VGPRs supported by the subtarget.
834 unsigned getAddressableNumVGPRs() const {
835 return AMDGPU::IsaInfo::getAddressableNumVGPRs(getFeatureBits());
838 /// \returns Minimum number of VGPRs that meets given number of waves per
839 /// execution unit requirement supported by the subtarget.
840 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
841 return AMDGPU::IsaInfo::getMinNumVGPRs(getFeatureBits(), WavesPerEU);
844 /// \returns Maximum number of VGPRs that meets given number of waves per
845 /// execution unit requirement supported by the subtarget.
846 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
847 return AMDGPU::IsaInfo::getMaxNumVGPRs(getFeatureBits(), WavesPerEU);
850 /// \returns Reserved number of VGPRs for given function \p MF.
851 unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
852 return debuggerReserveRegs() ? 4 : 0;
855 /// \returns Maximum number of VGPRs that meets number of waves per execution
856 /// unit requirement for function \p MF, or number of VGPRs explicitly
857 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
859 /// \returns Value that meets number of waves per execution unit requirement
860 /// if explicitly requested value cannot be converted to integer, violates
861 /// subtarget's specifications, or does not meet number of waves per execution
862 /// unit requirement.
863 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
866 } // end namespace llvm
868 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H