1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "R600InstrInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600FrameLowering.h"
22 #include "SIInstrInfo.h"
23 #include "SIISelLowering.h"
24 #include "SIFrameLowering.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "Utils/AMDGPUBaseInfo.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/MathExtras.h"
38 #define GET_SUBTARGETINFO_HEADER
39 #include "AMDGPUGenSubtargetInfo.inc"
45 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
74 TrapHandlerAbiNone = 0,
79 TrapIDHardwareReserved = 0,
80 TrapIDHSADebugTrap = 1,
82 TrapIDLLVMDebugTrap = 3,
83 TrapIDDebugBreakpoint = 7,
84 TrapIDDebugReserved8 = 8,
85 TrapIDDebugReservedFE = 0xfe,
86 TrapIDDebugReservedFF = 0xff
90 LLVMTrapHandlerRegValue = 1
94 // Basic subtarget description.
98 unsigned WavefrontSize;
101 unsigned MaxPrivateElementSize;
103 // Possibly statically set by tablegen, but may want to be overridden.
107 // Dynamially set bits that enable features.
109 bool FP64FP16Denormals;
113 bool AutoWaitcntBeforeBarrier;
114 bool UnalignedScratchAccess;
115 bool UnalignedBufferAccess;
116 bool HasApertureRegs;
119 bool DebuggerInsertNops;
120 bool DebuggerReserveRegs;
121 bool DebuggerEmitPrologue;
124 bool EnableVGPRSpilling;
125 bool EnablePromoteAlloca;
126 bool EnableLoadStoreOpt;
127 bool EnableUnsafeDSOffsetFolding;
128 bool EnableSIScheduler;
131 // Subtarget statically properties set by tablegen
139 bool HasSMemRealTime;
143 bool HasVGPRIndexMode;
144 bool HasScalarStores;
145 bool HasInv2PiInlineImm;
148 bool FlatAddressSpace;
149 bool FlatInstOffsets;
150 bool FlatGlobalInsts;
151 bool FlatScratchInsts;
156 short TexVTXClauseSize;
157 bool ScalarizeGlobal;
159 // Dummy feature to use for assembler in tablegen.
162 InstrItineraryData InstrItins;
163 SelectionDAGTargetInfo TSInfo;
167 AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
168 const TargetMachine &TM);
169 ~AMDGPUSubtarget() override;
171 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
172 StringRef GPU, StringRef FS);
174 const AMDGPUInstrInfo *getInstrInfo() const override = 0;
175 const AMDGPUFrameLowering *getFrameLowering() const override = 0;
176 const AMDGPUTargetLowering *getTargetLowering() const override = 0;
177 const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
179 const InstrItineraryData *getInstrItineraryData() const override {
183 // Nothing implemented, just prevent crashes on use.
184 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
188 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
190 bool isAmdHsaOS() const {
191 return TargetTriple.getOS() == Triple::AMDHSA;
194 bool isMesa3DOS() const {
195 return TargetTriple.getOS() == Triple::Mesa3D;
198 bool isOpenCLEnv() const {
199 return TargetTriple.getEnvironment() == Triple::OpenCL ||
200 TargetTriple.getEnvironmentName() == "amdgizcl";
203 Generation getGeneration() const {
207 unsigned getWavefrontSize() const {
208 return WavefrontSize;
211 int getLocalMemorySize() const {
212 return LocalMemorySize;
215 int getLDSBankCount() const {
219 unsigned getMaxPrivateElementSize() const {
220 return MaxPrivateElementSize;
223 AMDGPUAS getAMDGPUAS() const {
227 bool has16BitInsts() const {
228 return Has16BitInsts;
231 bool hasVOP3PInsts() const {
232 return HasVOP3PInsts;
235 bool hasHWFP64() const {
239 bool hasFastFMAF32() const {
243 bool hasHalfRate64Ops() const {
244 return HalfRate64Ops;
247 bool hasAddr64() const {
248 return (getGeneration() < VOLCANIC_ISLANDS);
251 bool hasBFE() const {
252 return (getGeneration() >= EVERGREEN);
255 bool hasBFI() const {
256 return (getGeneration() >= EVERGREEN);
259 bool hasBFM() const {
263 bool hasBCNT(unsigned Size) const {
265 return (getGeneration() >= EVERGREEN);
268 return (getGeneration() >= SOUTHERN_ISLANDS);
273 bool hasMulU24() const {
274 return (getGeneration() >= EVERGREEN);
277 bool hasMulI24() const {
278 return (getGeneration() >= SOUTHERN_ISLANDS ||
282 bool hasFFBL() const {
283 return (getGeneration() >= EVERGREEN);
286 bool hasFFBH() const {
287 return (getGeneration() >= EVERGREEN);
290 bool hasMed3_16() const {
291 return getGeneration() >= GFX9;
294 bool hasMin3Max3_16() const {
295 return getGeneration() >= GFX9;
298 bool hasCARRY() const {
299 return (getGeneration() >= EVERGREEN);
302 bool hasBORROW() const {
303 return (getGeneration() >= EVERGREEN);
306 bool hasCaymanISA() const {
310 TrapHandlerAbi getTrapHandlerAbi() const {
311 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
314 bool isPromoteAllocaEnabled() const {
315 return EnablePromoteAlloca;
318 bool unsafeDSOffsetFoldingEnabled() const {
319 return EnableUnsafeDSOffsetFolding;
322 bool dumpCode() const {
326 /// Return the amount of LDS that can be used that will not restrict the
327 /// occupancy lower than WaveCount.
328 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
329 const Function &) const;
331 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
332 /// the given LDS memory size is the only constraint.
333 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
335 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const {
336 const auto *MFI = MF.getInfo<SIMachineFunctionInfo>();
337 return getOccupancyWithLocalMemSize(MFI->getLDSSize(), *MF.getFunction());
340 bool hasFP16Denormals() const {
341 return FP64FP16Denormals;
344 bool hasFP32Denormals() const {
345 return FP32Denormals;
348 bool hasFP64Denormals() const {
349 return FP64FP16Denormals;
352 bool hasFPExceptions() const {
356 bool enableDX10Clamp() const {
360 bool enableIEEEBit(const MachineFunction &MF) const {
361 return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
364 bool useFlatForGlobal() const {
365 return FlatForGlobal;
368 bool hasAutoWaitcntBeforeBarrier() const {
369 return AutoWaitcntBeforeBarrier;
372 bool hasUnalignedBufferAccess() const {
373 return UnalignedBufferAccess;
376 bool hasUnalignedScratchAccess() const {
377 return UnalignedScratchAccess;
380 bool hasApertureRegs() const {
381 return HasApertureRegs;
384 bool isTrapHandlerEnabled() const {
388 bool isXNACKEnabled() const {
392 bool hasFlatAddressSpace() const {
393 return FlatAddressSpace;
396 bool hasFlatInstOffsets() const {
397 return FlatInstOffsets;
400 bool hasFlatGlobalInsts() const {
401 return FlatGlobalInsts;
404 bool hasFlatScratchInsts() const {
405 return FlatScratchInsts;
408 bool isMesaKernel(const MachineFunction &MF) const {
409 return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
412 // Covers VS/PS/CS graphics shaders
413 bool isMesaGfxShader(const MachineFunction &MF) const {
414 return isMesa3DOS() && AMDGPU::isShader(MF.getFunction()->getCallingConv());
417 bool isAmdCodeObjectV2(const MachineFunction &MF) const {
418 return isAmdHsaOS() || isMesaKernel(MF);
421 bool hasFminFmaxLegacy() const {
422 return getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
425 bool hasSDWA() const {
429 /// \brief Returns the offset in bytes from the start of the input buffer
430 /// of the first explicit kernel argument.
431 unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const {
432 return isAmdCodeObjectV2(MF) ? 0 : 36;
435 unsigned getAlignmentForImplicitArgPtr() const {
436 return isAmdHsaOS() ? 8 : 4;
439 unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
440 if (isMesaKernel(MF))
442 if (isAmdHsaOS() && isOpenCLEnv())
447 // Scratch is allocated in 256 dword per wave blocks for the entire
448 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
449 // is 4-byte aligned.
450 unsigned getStackAlignment() const {
454 bool enableMachineScheduler() const override {
458 bool enableSubRegLiveness() const override {
462 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
463 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
465 /// \returns Number of execution units per compute unit supported by the
467 unsigned getEUsPerCU() const {
468 return AMDGPU::IsaInfo::getEUsPerCU(getFeatureBits());
471 /// \returns Maximum number of work groups per compute unit supported by the
472 /// subtarget and limited by given \p FlatWorkGroupSize.
473 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
474 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(getFeatureBits(),
478 /// \returns Maximum number of waves per compute unit supported by the
479 /// subtarget without any kind of limitation.
480 unsigned getMaxWavesPerCU() const {
481 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits());
484 /// \returns Maximum number of waves per compute unit supported by the
485 /// subtarget and limited by given \p FlatWorkGroupSize.
486 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
487 return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits(),
491 /// \returns Minimum number of waves per execution unit supported by the
493 unsigned getMinWavesPerEU() const {
494 return AMDGPU::IsaInfo::getMinWavesPerEU(getFeatureBits());
497 /// \returns Maximum number of waves per execution unit supported by the
498 /// subtarget without any kind of limitation.
499 unsigned getMaxWavesPerEU() const {
500 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits());
503 /// \returns Maximum number of waves per execution unit supported by the
504 /// subtarget and limited by given \p FlatWorkGroupSize.
505 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
506 return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits(),
510 /// \returns Minimum flat work group size supported by the subtarget.
511 unsigned getMinFlatWorkGroupSize() const {
512 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(getFeatureBits());
515 /// \returns Maximum flat work group size supported by the subtarget.
516 unsigned getMaxFlatWorkGroupSize() const {
517 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(getFeatureBits());
520 /// \returns Number of waves per work group supported by the subtarget and
521 /// limited by given \p FlatWorkGroupSize.
522 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
523 return AMDGPU::IsaInfo::getWavesPerWorkGroup(getFeatureBits(),
527 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
528 /// for function \p F, or minimum/maximum flat work group sizes explicitly
529 /// requested using "amdgpu-flat-work-group-size" attribute attached to
532 /// \returns Subtarget's default values if explicitly requested values cannot
533 /// be converted to integer, or violate subtarget's specifications.
534 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
536 /// \returns Subtarget's default pair of minimum/maximum number of waves per
537 /// execution unit for function \p F, or minimum/maximum number of waves per
538 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
539 /// attached to function \p F.
541 /// \returns Subtarget's default values if explicitly requested values cannot
542 /// be converted to integer, violate subtarget's specifications, or are not
543 /// compatible with minimum/maximum number of waves limited by flat work group
544 /// size, register usage, and/or lds usage.
545 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
547 /// Creates value range metadata on an workitemid.* inrinsic call or load.
548 bool makeLIDRangeMetadata(Instruction *I) const;
551 class R600Subtarget final : public AMDGPUSubtarget {
553 R600InstrInfo InstrInfo;
554 R600FrameLowering FrameLowering;
555 R600TargetLowering TLInfo;
558 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
559 const TargetMachine &TM);
561 const R600InstrInfo *getInstrInfo() const override {
565 const R600FrameLowering *getFrameLowering() const override {
566 return &FrameLowering;
569 const R600TargetLowering *getTargetLowering() const override {
573 const R600RegisterInfo *getRegisterInfo() const override {
574 return &InstrInfo.getRegisterInfo();
577 bool hasCFAluBug() const {
581 bool hasVertexCache() const {
582 return HasVertexCache;
585 short getTexVTXClauseSize() const {
586 return TexVTXClauseSize;
590 class SISubtarget final : public AMDGPUSubtarget {
592 SIInstrInfo InstrInfo;
593 SIFrameLowering FrameLowering;
594 SITargetLowering TLInfo;
595 std::unique_ptr<GISelAccessor> GISel;
598 SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
599 const TargetMachine &TM);
601 const SIInstrInfo *getInstrInfo() const override {
605 const SIFrameLowering *getFrameLowering() const override {
606 return &FrameLowering;
609 const SITargetLowering *getTargetLowering() const override {
613 const CallLowering *getCallLowering() const override {
614 assert(GISel && "Access to GlobalISel APIs not set");
615 return GISel->getCallLowering();
618 const InstructionSelector *getInstructionSelector() const override {
619 assert(GISel && "Access to GlobalISel APIs not set");
620 return GISel->getInstructionSelector();
623 const LegalizerInfo *getLegalizerInfo() const override {
624 assert(GISel && "Access to GlobalISel APIs not set");
625 return GISel->getLegalizerInfo();
628 const RegisterBankInfo *getRegBankInfo() const override {
629 assert(GISel && "Access to GlobalISel APIs not set");
630 return GISel->getRegBankInfo();
633 const SIRegisterInfo *getRegisterInfo() const override {
634 return &InstrInfo.getRegisterInfo();
637 void setGISelAccessor(GISelAccessor &GISel) {
638 this->GISel.reset(&GISel);
641 // XXX - Why is this here if it isn't in the default pass set?
642 bool enableEarlyIfConversion() const override {
646 void overrideSchedPolicy(MachineSchedPolicy &Policy,
647 unsigned NumRegionInstrs) const override;
649 bool isVGPRSpillingEnabled(const Function& F) const;
651 unsigned getMaxNumUserSGPRs() const {
655 bool hasSMemRealTime() const {
656 return HasSMemRealTime;
659 bool hasMovrel() const {
663 bool hasVGPRIndexMode() const {
664 return HasVGPRIndexMode;
667 bool useVGPRIndexMode(bool UserEnable) const {
668 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
671 bool hasScalarCompareEq64() const {
672 return getGeneration() >= VOLCANIC_ISLANDS;
675 bool hasScalarStores() const {
676 return HasScalarStores;
679 bool hasInv2PiInlineImm() const {
680 return HasInv2PiInlineImm;
683 bool hasDPP() const {
687 bool enableSIScheduler() const {
688 return EnableSIScheduler;
691 bool debuggerSupported() const {
692 return debuggerInsertNops() && debuggerReserveRegs() &&
693 debuggerEmitPrologue();
696 bool debuggerInsertNops() const {
697 return DebuggerInsertNops;
700 bool debuggerReserveRegs() const {
701 return DebuggerReserveRegs;
704 bool debuggerEmitPrologue() const {
705 return DebuggerEmitPrologue;
708 bool loadStoreOptEnabled() const {
709 return EnableLoadStoreOpt;
712 bool hasSGPRInitBug() const {
716 bool has12DWordStoreHazard() const {
717 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
720 bool hasSMovFedHazard() const {
721 return getGeneration() >= AMDGPUSubtarget::GFX9;
724 bool hasReadM0Hazard() const {
725 return getGeneration() >= AMDGPUSubtarget::GFX9;
728 unsigned getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const;
730 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
731 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
733 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
734 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
736 /// \returns true if the flat_scratch register should be initialized with the
737 /// pointer to the wave's scratch memory rather than a size and offset.
738 bool flatScratchIsPointer() const {
739 return getGeneration() >= GFX9;
742 /// \returns SGPR allocation granularity supported by the subtarget.
743 unsigned getSGPRAllocGranule() const {
744 return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
747 /// \returns SGPR encoding granularity supported by the subtarget.
748 unsigned getSGPREncodingGranule() const {
749 return AMDGPU::IsaInfo::getSGPREncodingGranule(getFeatureBits());
752 /// \returns Total number of SGPRs supported by the subtarget.
753 unsigned getTotalNumSGPRs() const {
754 return AMDGPU::IsaInfo::getTotalNumSGPRs(getFeatureBits());
757 /// \returns Addressable number of SGPRs supported by the subtarget.
758 unsigned getAddressableNumSGPRs() const {
759 return AMDGPU::IsaInfo::getAddressableNumSGPRs(getFeatureBits());
762 /// \returns Minimum number of SGPRs that meets the given number of waves per
763 /// execution unit requirement supported by the subtarget.
764 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
765 return AMDGPU::IsaInfo::getMinNumSGPRs(getFeatureBits(), WavesPerEU);
768 /// \returns Maximum number of SGPRs that meets the given number of waves per
769 /// execution unit requirement supported by the subtarget.
770 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
771 return AMDGPU::IsaInfo::getMaxNumSGPRs(getFeatureBits(), WavesPerEU,
775 /// \returns Reserved number of SGPRs for given function \p MF.
776 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
778 /// \returns Maximum number of SGPRs that meets number of waves per execution
779 /// unit requirement for function \p MF, or number of SGPRs explicitly
780 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
782 /// \returns Value that meets number of waves per execution unit requirement
783 /// if explicitly requested value cannot be converted to integer, violates
784 /// subtarget's specifications, or does not meet number of waves per execution
785 /// unit requirement.
786 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
788 /// \returns VGPR allocation granularity supported by the subtarget.
789 unsigned getVGPRAllocGranule() const {
790 return AMDGPU::IsaInfo::getVGPRAllocGranule(getFeatureBits());;
793 /// \returns VGPR encoding granularity supported by the subtarget.
794 unsigned getVGPREncodingGranule() const {
795 return AMDGPU::IsaInfo::getVGPREncodingGranule(getFeatureBits());
798 /// \returns Total number of VGPRs supported by the subtarget.
799 unsigned getTotalNumVGPRs() const {
800 return AMDGPU::IsaInfo::getTotalNumVGPRs(getFeatureBits());
803 /// \returns Addressable number of VGPRs supported by the subtarget.
804 unsigned getAddressableNumVGPRs() const {
805 return AMDGPU::IsaInfo::getAddressableNumVGPRs(getFeatureBits());
808 /// \returns Minimum number of VGPRs that meets given number of waves per
809 /// execution unit requirement supported by the subtarget.
810 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
811 return AMDGPU::IsaInfo::getMinNumVGPRs(getFeatureBits(), WavesPerEU);
814 /// \returns Maximum number of VGPRs that meets given number of waves per
815 /// execution unit requirement supported by the subtarget.
816 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
817 return AMDGPU::IsaInfo::getMaxNumVGPRs(getFeatureBits(), WavesPerEU);
820 /// \returns Reserved number of VGPRs for given function \p MF.
821 unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
822 return debuggerReserveRegs() ? 4 : 0;
825 /// \returns Maximum number of VGPRs that meets number of waves per execution
826 /// unit requirement for function \p MF, or number of VGPRs explicitly
827 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
829 /// \returns Value that meets number of waves per execution unit requirement
830 /// if explicitly requested value cannot be converted to integer, violates
831 /// subtarget's specifications, or does not meet number of waves per execution
832 /// unit requirement.
833 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
836 } // end namespace llvm
838 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H