1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetLoweringObjectFile.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/LegacyPassManager.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
53 static cl::opt<bool> EnableR600StructurizeCFG(
54 "r600-ir-structurize",
55 cl::desc("Use StructurizeCFG IR pass"),
58 static cl::opt<bool> EnableSROA(
60 cl::desc("Run SROA after promote alloca pass"),
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66 cl::desc("Run early if-conversion"),
69 static cl::opt<bool> EnableR600IfConvert(
71 cl::desc("Use if conversion pass"),
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77 "amdgpu-load-store-vectorizer",
78 cl::desc("Enable load store vectorizer"),
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84 "amdgpu-scalarize-global-loads",
85 cl::desc("Enable global load scalarization"),
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91 "amdgpu-internalize-symbols",
92 cl::desc("Enable elimination of non-kernel functions and unused globals"),
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98 "amdgpu-early-inline-all",
99 cl::desc("Inline all functions early"),
103 static cl::opt<bool> EnableSDWAPeephole(
104 "amdgpu-sdwa-peephole",
105 cl::desc("Enable SDWA peepholer"),
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110 cl::desc("Enable AMDGPU Alias Analysis"),
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115 "enable-si-insert-waitcnts",
116 cl::desc("Use new waitcnt insertion pass"),
119 // Option to run late CFG structurizer
120 static cl::opt<bool, true> LateCFGStructurize(
121 "amdgpu-late-structurize",
122 cl::desc("Enable late CFG structurization"),
123 cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127 "amdgpu-function-calls",
129 cl::desc("Enable AMDGPU function call support"),
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134 "amdgpu-simplify-libcall",
135 cl::desc("Enable mdgpu library simplifications"),
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140 // Register the target
141 RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142 RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
144 PassRegistry *PR = PassRegistry::getPassRegistry();
145 initializeR600ClauseMergePassPass(*PR);
146 initializeR600ControlFlowFinalizerPass(*PR);
147 initializeR600PacketizerPass(*PR);
148 initializeR600ExpandSpecialInstrsPassPass(*PR);
149 initializeR600VectorRegMergerPass(*PR);
150 initializeAMDGPUDAGToDAGISelPass(*PR);
151 initializeSILowerI1CopiesPass(*PR);
152 initializeSIFixSGPRCopiesPass(*PR);
153 initializeSIFixVGPRCopiesPass(*PR);
154 initializeSIFoldOperandsPass(*PR);
155 initializeSIPeepholeSDWAPass(*PR);
156 initializeSIShrinkInstructionsPass(*PR);
157 initializeSIOptimizeExecMaskingPreRAPass(*PR);
158 initializeSILoadStoreOptimizerPass(*PR);
159 initializeAMDGPUAlwaysInlinePass(*PR);
160 initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
161 initializeAMDGPUAnnotateUniformValuesPass(*PR);
162 initializeAMDGPUArgumentUsageInfoPass(*PR);
163 initializeAMDGPULowerIntrinsicsPass(*PR);
164 initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
165 initializeAMDGPUPromoteAllocaPass(*PR);
166 initializeAMDGPUCodeGenPreparePass(*PR);
167 initializeAMDGPURewriteOutArgumentsPass(*PR);
168 initializeAMDGPUUnifyMetadataPass(*PR);
169 initializeSIAnnotateControlFlowPass(*PR);
170 initializeSIInsertWaitsPass(*PR);
171 initializeSIInsertWaitcntsPass(*PR);
172 initializeSIWholeQuadModePass(*PR);
173 initializeSILowerControlFlowPass(*PR);
174 initializeSIInsertSkipsPass(*PR);
175 initializeSIMemoryLegalizerPass(*PR);
176 initializeSIDebuggerInsertNopsPass(*PR);
177 initializeSIOptimizeExecMaskingPass(*PR);
178 initializeSIFixWWMLivenessPass(*PR);
179 initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
180 initializeAMDGPUAAWrapperPassPass(*PR);
181 initializeAMDGPUUseNativeCallsPass(*PR);
182 initializeAMDGPUSimplifyLibCallsPass(*PR);
183 initializeAMDGPUInlinerPass(*PR);
186 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
187 return llvm::make_unique<AMDGPUTargetObjectFile>();
190 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
191 return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
194 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
195 return new SIScheduleDAGMI(C);
198 static ScheduleDAGInstrs *
199 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
200 ScheduleDAGMILive *DAG =
201 new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
202 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
203 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
204 DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
208 static ScheduleDAGInstrs *
209 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
210 auto DAG = new GCNIterativeScheduler(C,
211 GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
212 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
213 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
217 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
218 return new GCNIterativeScheduler(C,
219 GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
222 static ScheduleDAGInstrs *
223 createIterativeILPMachineScheduler(MachineSchedContext *C) {
224 auto DAG = new GCNIterativeScheduler(C,
225 GCNIterativeScheduler::SCHEDULE_ILP);
226 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
227 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
228 DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
232 static MachineSchedRegistry
233 R600SchedRegistry("r600", "Run R600's custom scheduler",
234 createR600MachineScheduler);
236 static MachineSchedRegistry
237 SISchedRegistry("si", "Run SI's custom scheduler",
238 createSIMachineScheduler);
240 static MachineSchedRegistry
241 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
242 "Run GCN scheduler to maximize occupancy",
243 createGCNMaxOccupancyMachineScheduler);
245 static MachineSchedRegistry
246 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
247 "Run GCN scheduler to maximize occupancy (experimental)",
248 createIterativeGCNMaxOccupancyMachineScheduler);
250 static MachineSchedRegistry
251 GCNMinRegSchedRegistry("gcn-minreg",
252 "Run GCN iterative scheduler for minimal register usage (experimental)",
253 createMinRegScheduler);
255 static MachineSchedRegistry
256 GCNILPSchedRegistry("gcn-ilp",
257 "Run GCN iterative scheduler for ILP scheduling (experimental)",
258 createIterativeILPMachineScheduler);
260 static StringRef computeDataLayout(const Triple &TT) {
261 if (TT.getArch() == Triple::r600) {
263 if (TT.getEnvironmentName() == "amdgiz" ||
264 TT.getEnvironmentName() == "amdgizcl")
265 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
266 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
267 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
268 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
271 // 32-bit private, local, and region pointers. 64-bit global, constant and
273 if (TT.getEnvironmentName() == "amdgiz" ||
274 TT.getEnvironmentName() == "amdgizcl")
275 return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
276 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
277 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
278 return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
279 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
280 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
284 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
288 if (TT.getArch() == Triple::amdgcn)
294 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
295 // The AMDGPU toolchain only supports generating shared objects, so we
296 // must always use PIC.
300 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
303 return CodeModel::Small;
306 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
307 StringRef CPU, StringRef FS,
308 TargetOptions Options,
309 Optional<Reloc::Model> RM,
310 Optional<CodeModel::Model> CM,
311 CodeGenOpt::Level OptLevel)
312 : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
313 FS, Options, getEffectiveRelocModel(RM),
314 getEffectiveCodeModel(CM), OptLevel),
315 TLOF(createTLOF(getTargetTriple())) {
316 AS = AMDGPU::getAMDGPUAS(TT);
320 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
322 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
324 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
325 Attribute GPUAttr = F.getFnAttribute("target-cpu");
326 return GPUAttr.hasAttribute(Attribute::None) ?
327 getTargetCPU() : GPUAttr.getValueAsString();
330 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
331 Attribute FSAttr = F.getFnAttribute("target-features");
333 return FSAttr.hasAttribute(Attribute::None) ?
334 getTargetFeatureString() :
335 FSAttr.getValueAsString();
338 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
339 return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
340 if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
341 AAR.addAAResult(WrapperPass->getResult());
345 /// Predicate for Internalize pass.
346 static bool mustPreserveGV(const GlobalValue &GV) {
347 if (const Function *F = dyn_cast<Function>(&GV))
348 return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
350 return !GV.use_empty();
353 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
354 Builder.DivergentTarget = true;
356 bool EnableOpt = getOptLevel() > CodeGenOpt::None;
357 bool Internalize = InternalizeSymbols;
358 bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
359 bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
360 bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
362 if (EnableAMDGPUFunctionCalls) {
363 delete Builder.Inliner;
364 Builder.Inliner = createAMDGPUFunctionInliningPass();
368 // If we're generating code, we always have the whole program available. The
369 // relocations expected for externally visible functions aren't supported,
370 // so make sure every non-entry function is hidden.
371 Builder.addExtension(
372 PassManagerBuilder::EP_EnabledOnOptLevel0,
373 [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
374 PM.add(createInternalizePass(mustPreserveGV));
378 Builder.addExtension(
379 PassManagerBuilder::EP_ModuleOptimizerEarly,
380 [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
381 legacy::PassManagerBase &PM) {
383 PM.add(createAMDGPUAAWrapperPass());
384 PM.add(createAMDGPUExternalAAWrapperPass());
386 PM.add(createAMDGPUUnifyMetadataPass());
388 PM.add(createInternalizePass(mustPreserveGV));
389 PM.add(createGlobalDCEPass());
392 PM.add(createAMDGPUAlwaysInlinePass(false));
395 const auto &Opt = Options;
396 Builder.addExtension(
397 PassManagerBuilder::EP_EarlyAsPossible,
398 [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
399 legacy::PassManagerBase &PM) {
401 PM.add(createAMDGPUAAWrapperPass());
402 PM.add(createAMDGPUExternalAAWrapperPass());
404 PM.add(llvm::createAMDGPUUseNativeCallsPass());
406 PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
409 Builder.addExtension(
410 PassManagerBuilder::EP_CGSCCOptimizerLate,
411 [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
412 // Add infer address spaces pass to the opt pipeline after inlining
413 // but before SROA to increase SROA opportunities.
414 PM.add(createInferAddressSpacesPass());
418 //===----------------------------------------------------------------------===//
419 // R600 Target Machine (R600 -> Cayman)
420 //===----------------------------------------------------------------------===//
422 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
423 StringRef CPU, StringRef FS,
424 TargetOptions Options,
425 Optional<Reloc::Model> RM,
426 Optional<CodeModel::Model> CM,
427 CodeGenOpt::Level OL, bool JIT)
428 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
429 setRequiresStructuredCFG(true);
432 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
433 const Function &F) const {
434 StringRef GPU = getGPUName(F);
435 StringRef FS = getFeatureString(F);
437 SmallString<128> SubtargetKey(GPU);
438 SubtargetKey.append(FS);
440 auto &I = SubtargetMap[SubtargetKey];
442 // This needs to be done before we create a new subtarget since any
443 // creation will depend on the TM and the code generation flags on the
444 // function that reside in TargetOptions.
445 resetTargetOptions(F);
446 I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
452 //===----------------------------------------------------------------------===//
453 // GCN Target Machine (SI+)
454 //===----------------------------------------------------------------------===//
456 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
457 StringRef CPU, StringRef FS,
458 TargetOptions Options,
459 Optional<Reloc::Model> RM,
460 Optional<CodeModel::Model> CM,
461 CodeGenOpt::Level OL, bool JIT)
462 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
464 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
465 StringRef GPU = getGPUName(F);
466 StringRef FS = getFeatureString(F);
468 SmallString<128> SubtargetKey(GPU);
469 SubtargetKey.append(FS);
471 auto &I = SubtargetMap[SubtargetKey];
473 // This needs to be done before we create a new subtarget since any
474 // creation will depend on the TM and the code generation flags on the
475 // function that reside in TargetOptions.
476 resetTargetOptions(F);
477 I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
480 I->setScalarizeGlobalBehavior(ScalarizeGlobal);
485 //===----------------------------------------------------------------------===//
487 //===----------------------------------------------------------------------===//
491 class AMDGPUPassConfig : public TargetPassConfig {
493 AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
494 : TargetPassConfig(TM, PM) {
495 // Exceptions and StackMaps are not supported, so these passes will never do
497 disablePass(&StackMapLivenessID);
498 disablePass(&FuncletLayoutID);
501 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
502 return getTM<AMDGPUTargetMachine>();
506 createMachineScheduler(MachineSchedContext *C) const override {
507 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
508 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
509 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
513 void addEarlyCSEOrGVNPass();
514 void addStraightLineScalarOptimizationPasses();
515 void addIRPasses() override;
516 void addCodeGenPrepare() override;
517 bool addPreISel() override;
518 bool addInstSelector() override;
519 bool addGCPasses() override;
522 class R600PassConfig final : public AMDGPUPassConfig {
524 R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
525 : AMDGPUPassConfig(TM, PM) {}
527 ScheduleDAGInstrs *createMachineScheduler(
528 MachineSchedContext *C) const override {
529 return createR600MachineScheduler(C);
532 bool addPreISel() override;
533 bool addInstSelector() override;
534 void addPreRegAlloc() override;
535 void addPreSched2() override;
536 void addPreEmitPass() override;
539 class GCNPassConfig final : public AMDGPUPassConfig {
541 GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
542 : AMDGPUPassConfig(TM, PM) {
543 // It is necessary to know the register usage of the entire call graph. We
544 // allow calls without EnableAMDGPUFunctionCalls if they are marked
545 // noinline, so this is always required.
546 setRequiresCodeGenSCCOrder(true);
549 GCNTargetMachine &getGCNTargetMachine() const {
550 return getTM<GCNTargetMachine>();
554 createMachineScheduler(MachineSchedContext *C) const override;
556 bool addPreISel() override;
557 void addMachineSSAOptimization() override;
558 bool addILPOpts() override;
559 bool addInstSelector() override;
560 bool addIRTranslator() override;
561 bool addLegalizeMachineIR() override;
562 bool addRegBankSelect() override;
563 bool addGlobalInstructionSelect() override;
564 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
565 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
566 void addPreRegAlloc() override;
567 void addPostRegAlloc() override;
568 void addPreSched2() override;
569 void addPreEmitPass() override;
572 } // end anonymous namespace
575 AMDGPUTargetMachine::getTargetTransformInfo(const Function &F) {
576 return TargetTransformInfo(AMDGPUTTIImpl(this, F));
579 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
580 if (getOptLevel() == CodeGenOpt::Aggressive)
581 addPass(createGVNPass());
583 addPass(createEarlyCSEPass());
586 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
587 addPass(createSeparateConstOffsetFromGEPPass());
588 addPass(createSpeculativeExecutionPass());
589 // ReassociateGEPs exposes more opportunites for SLSR. See
590 // the example in reassociate-geps-and-slsr.ll.
591 addPass(createStraightLineStrengthReducePass());
592 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
593 // EarlyCSE can reuse.
594 addEarlyCSEOrGVNPass();
595 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
596 addPass(createNaryReassociatePass());
597 // NaryReassociate on GEPs creates redundant common expressions, so run
598 // EarlyCSE after it.
599 addPass(createEarlyCSEPass());
602 void AMDGPUPassConfig::addIRPasses() {
603 const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
605 // There is no reason to run these.
606 disablePass(&StackMapLivenessID);
607 disablePass(&FuncletLayoutID);
608 disablePass(&PatchableFunctionID);
610 addPass(createAMDGPULowerIntrinsicsPass());
612 if (TM.getTargetTriple().getArch() == Triple::r600 ||
613 !EnableAMDGPUFunctionCalls) {
614 // Function calls are not supported, so make sure we inline everything.
615 addPass(createAMDGPUAlwaysInlinePass());
616 addPass(createAlwaysInlinerLegacyPass());
617 // We need to add the barrier noop pass, otherwise adding the function
618 // inlining pass will cause all of the PassConfigs passes to be run
619 // one function at a time, which means if we have a nodule with two
620 // functions, then we will generate code for the first function
621 // without ever running any passes on the second.
622 addPass(createBarrierNoopPass());
625 if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
626 // TODO: May want to move later or split into an early and late one.
628 addPass(createAMDGPUCodeGenPreparePass());
631 // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
632 addPass(createAMDGPUOpenCLImageTypeLoweringPass());
634 // Replace OpenCL enqueued block function pointers with global variables.
635 addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
637 if (TM.getOptLevel() > CodeGenOpt::None) {
638 addPass(createInferAddressSpacesPass());
639 addPass(createAMDGPUPromoteAlloca());
642 addPass(createSROAPass());
644 addStraightLineScalarOptimizationPasses();
646 if (EnableAMDGPUAliasAnalysis) {
647 addPass(createAMDGPUAAWrapperPass());
648 addPass(createExternalAAWrapperPass([](Pass &P, Function &,
650 if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
651 AAR.addAAResult(WrapperPass->getResult());
656 TargetPassConfig::addIRPasses();
658 // EarlyCSE is not always strong enough to clean up what LSR produces. For
659 // example, GVN can combine
666 // %0 = shl nsw %a, 2
669 // but EarlyCSE can do neither of them.
670 if (getOptLevel() != CodeGenOpt::None)
671 addEarlyCSEOrGVNPass();
674 void AMDGPUPassConfig::addCodeGenPrepare() {
675 TargetPassConfig::addCodeGenPrepare();
677 if (EnableLoadStoreVectorizer)
678 addPass(createLoadStoreVectorizerPass());
681 bool AMDGPUPassConfig::addPreISel() {
682 addPass(createFlattenCFGPass());
686 bool AMDGPUPassConfig::addInstSelector() {
687 addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
691 bool AMDGPUPassConfig::addGCPasses() {
692 // Do nothing. GC is not supported.
696 //===----------------------------------------------------------------------===//
698 //===----------------------------------------------------------------------===//
700 bool R600PassConfig::addPreISel() {
701 AMDGPUPassConfig::addPreISel();
703 if (EnableR600StructurizeCFG)
704 addPass(createStructurizeCFGPass());
708 bool R600PassConfig::addInstSelector() {
709 addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
713 void R600PassConfig::addPreRegAlloc() {
714 addPass(createR600VectorRegMerger());
717 void R600PassConfig::addPreSched2() {
718 addPass(createR600EmitClauseMarkers(), false);
719 if (EnableR600IfConvert)
720 addPass(&IfConverterID, false);
721 addPass(createR600ClauseMergePass(), false);
724 void R600PassConfig::addPreEmitPass() {
725 addPass(createAMDGPUCFGStructurizerPass(), false);
726 addPass(createR600ExpandSpecialInstrsPass(), false);
727 addPass(&FinalizeMachineBundlesID, false);
728 addPass(createR600Packetizer(), false);
729 addPass(createR600ControlFlowFinalizer(), false);
732 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
733 return new R600PassConfig(*this, PM);
736 //===----------------------------------------------------------------------===//
738 //===----------------------------------------------------------------------===//
740 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
741 MachineSchedContext *C) const {
742 const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
743 if (ST.enableSIScheduler())
744 return createSIMachineScheduler(C);
745 return createGCNMaxOccupancyMachineScheduler(C);
748 bool GCNPassConfig::addPreISel() {
749 AMDGPUPassConfig::addPreISel();
751 // FIXME: We need to run a pass to propagate the attributes when calls are
753 addPass(createAMDGPUAnnotateKernelFeaturesPass());
755 // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
756 // regions formed by them.
757 addPass(&AMDGPUUnifyDivergentExitNodesID);
758 if (!LateCFGStructurize) {
759 addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
761 addPass(createSinkingPass());
762 addPass(createAMDGPUAnnotateUniformValues());
763 if (!LateCFGStructurize) {
764 addPass(createSIAnnotateControlFlowPass());
770 void GCNPassConfig::addMachineSSAOptimization() {
771 TargetPassConfig::addMachineSSAOptimization();
773 // We want to fold operands after PeepholeOptimizer has run (or as part of
774 // it), because it will eliminate extra copies making it easier to fold the
775 // real source operand. We want to eliminate dead instructions after, so that
776 // we see fewer uses of the copies. We then need to clean up the dead
777 // instructions leftover after the operands are folded as well.
779 // XXX - Can we get away without running DeadMachineInstructionElim again?
780 addPass(&SIFoldOperandsID);
781 addPass(&DeadMachineInstructionElimID);
782 addPass(&SILoadStoreOptimizerID);
783 if (EnableSDWAPeephole) {
784 addPass(&SIPeepholeSDWAID);
785 addPass(&MachineLICMID);
786 addPass(&MachineCSEID);
787 addPass(&SIFoldOperandsID);
788 addPass(&DeadMachineInstructionElimID);
790 addPass(createSIShrinkInstructionsPass());
793 bool GCNPassConfig::addILPOpts() {
794 if (EnableEarlyIfConversion)
795 addPass(&EarlyIfConverterID);
797 TargetPassConfig::addILPOpts();
801 bool GCNPassConfig::addInstSelector() {
802 AMDGPUPassConfig::addInstSelector();
803 addPass(createSILowerI1CopiesPass());
804 addPass(&SIFixSGPRCopiesID);
808 bool GCNPassConfig::addIRTranslator() {
809 addPass(new IRTranslator());
813 bool GCNPassConfig::addLegalizeMachineIR() {
814 addPass(new Legalizer());
818 bool GCNPassConfig::addRegBankSelect() {
819 addPass(new RegBankSelect());
823 bool GCNPassConfig::addGlobalInstructionSelect() {
824 addPass(new InstructionSelect());
828 void GCNPassConfig::addPreRegAlloc() {
829 if (LateCFGStructurize) {
830 addPass(createAMDGPUMachineCFGStructurizerPass());
832 addPass(createSIWholeQuadModePass());
835 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
836 // FIXME: We have to disable the verifier here because of PHIElimination +
837 // TwoAddressInstructions disabling it.
839 // This must be run immediately after phi elimination and before
840 // TwoAddressInstructions, otherwise the processing of the tied operand of
841 // SI_ELSE will introduce a copy of the tied operand source after the else.
842 insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
844 // This must be run after SILowerControlFlow, since it needs to use the
845 // machine-level CFG, but before register allocation.
846 insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
848 TargetPassConfig::addFastRegAlloc(RegAllocPass);
851 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
852 insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
854 // This must be run immediately after phi elimination and before
855 // TwoAddressInstructions, otherwise the processing of the tied operand of
856 // SI_ELSE will introduce a copy of the tied operand source after the else.
857 insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
859 // This must be run after SILowerControlFlow, since it needs to use the
860 // machine-level CFG, but before register allocation.
861 insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
863 TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
866 void GCNPassConfig::addPostRegAlloc() {
867 addPass(&SIFixVGPRCopiesID);
868 addPass(&SIOptimizeExecMaskingID);
869 TargetPassConfig::addPostRegAlloc();
872 void GCNPassConfig::addPreSched2() {
875 void GCNPassConfig::addPreEmitPass() {
876 // The hazard recognizer that runs as part of the post-ra scheduler does not
877 // guarantee to be able handle all hazards correctly. This is because if there
878 // are multiple scheduling regions in a basic block, the regions are scheduled
879 // bottom up, so when we begin to schedule a region we don't know what
880 // instructions were emitted directly before it.
882 // Here we add a stand-alone hazard recognizer pass which can handle all
884 addPass(&PostRAHazardRecognizerID);
886 if (EnableSIInsertWaitcntsPass)
887 addPass(createSIInsertWaitcntsPass());
889 addPass(createSIInsertWaitsPass());
890 addPass(createSIShrinkInstructionsPass());
891 addPass(&SIInsertSkipsPassID);
892 addPass(createSIMemoryLegalizerPass());
893 addPass(createSIDebuggerInsertNopsPass());
894 addPass(&BranchRelaxationPassID);
897 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
898 return new GCNPassConfig(*this, PM);