1 //===- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // This file implements a TargetTransformInfo analysis pass specific to the
12 // AMDGPU target machine. It uses the target's detailed information to provide
13 // more precise answers to certain TTI queries, while letting the target
14 // independent and default TTI implementations handle the rest.
16 //===----------------------------------------------------------------------===//
18 #include "AMDGPUTargetTransformInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/ISDOpcodes.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/Argument.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/BasicBlock.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Instruction.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Module.h"
38 #include "llvm/IR/PatternMatch.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/IR/Value.h"
41 #include "llvm/MC/SubtargetFeature.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/MachineValueType.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetMachine.h"
56 #define DEBUG_TYPE "AMDGPUtti"
58 static cl::opt<unsigned> UnrollThresholdPrivate(
59 "amdgpu-unroll-threshold-private",
60 cl::desc("Unroll threshold for AMDGPU if private memory used in a loop"),
61 cl::init(2500), cl::Hidden);
63 static cl::opt<unsigned> UnrollThresholdLocal(
64 "amdgpu-unroll-threshold-local",
65 cl::desc("Unroll threshold for AMDGPU if local memory used in a loop"),
66 cl::init(1000), cl::Hidden);
68 static cl::opt<unsigned> UnrollThresholdIf(
69 "amdgpu-unroll-threshold-if",
70 cl::desc("Unroll threshold increment for AMDGPU for each if statement inside loop"),
71 cl::init(150), cl::Hidden);
73 static bool dependsOnLocalPhi(const Loop *L, const Value *Cond,
75 const Instruction *I = dyn_cast<Instruction>(Cond);
79 for (const Value *V : I->operand_values()) {
82 if (const PHINode *PHI = dyn_cast<PHINode>(V)) {
83 if (llvm::none_of(L->getSubLoops(), [PHI](const Loop* SubLoop) {
84 return SubLoop->contains(PHI); }))
86 } else if (Depth < 10 && dependsOnLocalPhi(L, V, Depth+1))
92 void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
93 TTI::UnrollingPreferences &UP) {
94 UP.Threshold = 300; // Twice the default.
95 UP.MaxCount = std::numeric_limits<unsigned>::max();
98 // TODO: Do we want runtime unrolling?
100 // Maximum alloca size than can fit registers. Reserve 16 registers.
101 const unsigned MaxAlloca = (256 - 16) * 4;
102 unsigned ThresholdPrivate = UnrollThresholdPrivate;
103 unsigned ThresholdLocal = UnrollThresholdLocal;
104 unsigned MaxBoost = std::max(ThresholdPrivate, ThresholdLocal);
105 for (const BasicBlock *BB : L->getBlocks()) {
106 const DataLayout &DL = BB->getModule()->getDataLayout();
107 unsigned LocalGEPsSeen = 0;
109 if (llvm::any_of(L->getSubLoops(), [BB](const Loop* SubLoop) {
110 return SubLoop->contains(BB); }))
111 continue; // Block belongs to an inner loop.
113 for (const Instruction &I : *BB) {
114 // Unroll a loop which contains an "if" statement whose condition
115 // defined by a PHI belonging to the loop. This may help to eliminate
116 // if region and potentially even PHI itself, saving on both divergence
117 // and registers used for the PHI.
118 // Add a small bonus for each of such "if" statements.
119 if (const BranchInst *Br = dyn_cast<BranchInst>(&I)) {
120 if (UP.Threshold < MaxBoost && Br->isConditional()) {
121 if (L->isLoopExiting(Br->getSuccessor(0)) ||
122 L->isLoopExiting(Br->getSuccessor(1)))
124 if (dependsOnLocalPhi(L, Br->getCondition())) {
125 UP.Threshold += UnrollThresholdIf;
126 LLVM_DEBUG(dbgs() << "Set unroll threshold " << UP.Threshold
128 << *L << " due to " << *Br << '\n');
129 if (UP.Threshold >= MaxBoost)
136 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I);
140 unsigned AS = GEP->getAddressSpace();
141 unsigned Threshold = 0;
142 if (AS == AMDGPUAS::PRIVATE_ADDRESS)
143 Threshold = ThresholdPrivate;
144 else if (AS == AMDGPUAS::LOCAL_ADDRESS)
145 Threshold = ThresholdLocal;
149 if (UP.Threshold >= Threshold)
152 if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
153 const Value *Ptr = GEP->getPointerOperand();
154 const AllocaInst *Alloca =
155 dyn_cast<AllocaInst>(GetUnderlyingObject(Ptr, DL));
156 if (!Alloca || !Alloca->isStaticAlloca())
158 Type *Ty = Alloca->getAllocatedType();
159 unsigned AllocaSize = Ty->isSized() ? DL.getTypeAllocSize(Ty) : 0;
160 if (AllocaSize > MaxAlloca)
162 } else if (AS == AMDGPUAS::LOCAL_ADDRESS) {
164 // Inhibit unroll for local memory if we have seen addressing not to
165 // a variable, most likely we will be unable to combine it.
166 // Do not unroll too deep inner loops for local memory to give a chance
167 // to unroll an outer loop for a more important reason.
168 if (LocalGEPsSeen > 1 || L->getLoopDepth() > 2 ||
169 (!isa<GlobalVariable>(GEP->getPointerOperand()) &&
170 !isa<Argument>(GEP->getPointerOperand())))
174 // Check if GEP depends on a value defined by this loop itself.
175 bool HasLoopDef = false;
176 for (const Value *Op : GEP->operands()) {
177 const Instruction *Inst = dyn_cast<Instruction>(Op);
178 if (!Inst || L->isLoopInvariant(Op))
181 if (llvm::any_of(L->getSubLoops(), [Inst](const Loop* SubLoop) {
182 return SubLoop->contains(Inst); }))
190 // We want to do whatever we can to limit the number of alloca
191 // instructions that make it through to the code generator. allocas
192 // require us to use indirect addressing, which is slow and prone to
193 // compiler bugs. If this loop does an address calculation on an
194 // alloca ptr, then we want to use a higher than normal loop unroll
195 // threshold. This will give SROA a better chance to eliminate these
198 // We also want to have more unrolling for local memory to let ds
199 // instructions with different offsets combine.
201 // Don't use the maximum allowed value here as it will make some
202 // programs way too big.
203 UP.Threshold = Threshold;
204 LLVM_DEBUG(dbgs() << "Set unroll threshold " << Threshold
206 << *L << " due to " << *GEP << '\n');
207 if (UP.Threshold >= MaxBoost)
213 unsigned GCNTTIImpl::getHardwareNumberOfRegisters(bool Vec) const {
214 // The concept of vector registers doesn't really exist. Some packed vector
215 // operations operate on the normal 32-bit registers.
219 unsigned GCNTTIImpl::getNumberOfRegisters(bool Vec) const {
220 // This is really the number of registers to fill when vectorizing /
221 // interleaving loops, so we lie to avoid trying to use all registers.
222 return getHardwareNumberOfRegisters(Vec) >> 3;
225 unsigned GCNTTIImpl::getRegisterBitWidth(bool Vector) const {
229 unsigned GCNTTIImpl::getMinVectorRegisterBitWidth() const {
233 unsigned GCNTTIImpl::getLoadVectorFactor(unsigned VF, unsigned LoadSize,
234 unsigned ChainSizeInBytes,
235 VectorType *VecTy) const {
236 unsigned VecRegBitWidth = VF * LoadSize;
237 if (VecRegBitWidth > 128 && VecTy->getScalarSizeInBits() < 32)
238 // TODO: Support element-size less than 32bit?
239 return 128 / LoadSize;
244 unsigned GCNTTIImpl::getStoreVectorFactor(unsigned VF, unsigned StoreSize,
245 unsigned ChainSizeInBytes,
246 VectorType *VecTy) const {
247 unsigned VecRegBitWidth = VF * StoreSize;
248 if (VecRegBitWidth > 128)
249 return 128 / StoreSize;
254 unsigned GCNTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
255 if (AddrSpace == AMDGPUAS::GLOBAL_ADDRESS ||
256 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
257 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
261 if (AddrSpace == AMDGPUAS::FLAT_ADDRESS ||
262 AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
263 AddrSpace == AMDGPUAS::REGION_ADDRESS)
266 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
267 return 8 * ST->getMaxPrivateElementSize();
269 llvm_unreachable("unhandled address space");
272 bool GCNTTIImpl::isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
274 unsigned AddrSpace) const {
275 // We allow vectorization of flat stores, even though we may need to decompose
276 // them later if they may access private memory. We don't have enough context
277 // here, and legalization can handle it.
278 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
279 return (Alignment >= 4 || ST->hasUnalignedScratchAccess()) &&
280 ChainSizeInBytes <= ST->getMaxPrivateElementSize();
285 bool GCNTTIImpl::isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
287 unsigned AddrSpace) const {
288 return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
291 bool GCNTTIImpl::isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
293 unsigned AddrSpace) const {
294 return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
297 unsigned GCNTTIImpl::getMaxInterleaveFactor(unsigned VF) {
298 // Disable unrolling if the loop is not vectorized.
299 // TODO: Enable this again.
306 bool GCNTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
307 MemIntrinsicInfo &Info) const {
308 switch (Inst->getIntrinsicID()) {
309 case Intrinsic::amdgcn_atomic_inc:
310 case Intrinsic::amdgcn_atomic_dec:
311 case Intrinsic::amdgcn_ds_ordered_add:
312 case Intrinsic::amdgcn_ds_ordered_swap:
313 case Intrinsic::amdgcn_ds_fadd:
314 case Intrinsic::amdgcn_ds_fmin:
315 case Intrinsic::amdgcn_ds_fmax: {
316 auto *Ordering = dyn_cast<ConstantInt>(Inst->getArgOperand(2));
317 auto *Volatile = dyn_cast<ConstantInt>(Inst->getArgOperand(4));
318 if (!Ordering || !Volatile)
319 return false; // Invalid.
321 unsigned OrderingVal = Ordering->getZExtValue();
322 if (OrderingVal > static_cast<unsigned>(AtomicOrdering::SequentiallyConsistent))
325 Info.PtrVal = Inst->getArgOperand(0);
326 Info.Ordering = static_cast<AtomicOrdering>(OrderingVal);
328 Info.WriteMem = true;
329 Info.IsVolatile = !Volatile->isNullValue();
337 int GCNTTIImpl::getArithmeticInstrCost(
338 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
339 TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
340 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args ) {
341 EVT OrigTy = TLI->getValueType(DL, Ty);
342 if (!OrigTy.isSimple()) {
343 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
344 Opd1PropInfo, Opd2PropInfo);
347 // Legalize the type.
348 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
349 int ISD = TLI->InstructionOpcodeToISD(Opcode);
351 // Because we don't have any legal vector operations, but the legal types, we
352 // need to account for split vectors.
353 unsigned NElts = LT.second.isVector() ?
354 LT.second.getVectorNumElements() : 1;
356 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy;
363 return get64BitInstrCost() * LT.first * NElts;
366 return getFullRateInstrCost() * LT.first * NElts;
372 if (SLT == MVT::i64){
373 // and, or and xor are typically split into 2 VALU instructions.
374 return 2 * getFullRateInstrCost() * LT.first * NElts;
377 return LT.first * NElts * getFullRateInstrCost();
379 const int QuarterRateCost = getQuarterRateInstrCost();
380 if (SLT == MVT::i64) {
381 const int FullRateCost = getFullRateInstrCost();
382 return (4 * QuarterRateCost + (2 * 2) * FullRateCost) * LT.first * NElts;
386 return QuarterRateCost * NElts * LT.first;
392 return LT.first * NElts * get64BitInstrCost();
394 if (SLT == MVT::f32 || SLT == MVT::f16)
395 return LT.first * NElts * getFullRateInstrCost();
399 // FIXME: frem should be handled separately. The fdiv in it is most of it,
400 // but the current lowering is also not entirely correct.
401 if (SLT == MVT::f64) {
402 int Cost = 4 * get64BitInstrCost() + 7 * getQuarterRateInstrCost();
403 // Add cost of workaround.
404 if (ST->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
405 Cost += 3 * getFullRateInstrCost();
407 return LT.first * Cost * NElts;
410 if (!Args.empty() && match(Args[0], PatternMatch::m_FPOne())) {
411 // TODO: This is more complicated, unsafe flags etc.
412 if ((SLT == MVT::f32 && !ST->hasFP32Denormals()) ||
413 (SLT == MVT::f16 && ST->has16BitInsts())) {
414 return LT.first * getQuarterRateInstrCost() * NElts;
418 if (SLT == MVT::f16 && ST->has16BitInsts()) {
424 int Cost = 4 * getFullRateInstrCost() + 2 * getQuarterRateInstrCost();
425 return LT.first * Cost * NElts;
428 if (SLT == MVT::f32 || SLT == MVT::f16) {
429 int Cost = 7 * getFullRateInstrCost() + 1 * getQuarterRateInstrCost();
431 if (!ST->hasFP32Denormals()) {
433 Cost += 2 * getFullRateInstrCost();
436 return LT.first * NElts * Cost;
443 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
444 Opd1PropInfo, Opd2PropInfo);
447 unsigned GCNTTIImpl::getCFInstrCost(unsigned Opcode) {
448 // XXX - For some reason this isn't called for switch.
450 case Instruction::Br:
451 case Instruction::Ret:
454 return BaseT::getCFInstrCost(Opcode);
458 int GCNTTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
460 EVT OrigTy = TLI->getValueType(DL, Ty);
462 // Computes cost on targets that have packed math instructions(which support
463 // 16-bit types only).
465 !ST->hasVOP3PInsts() ||
466 OrigTy.getScalarSizeInBits() != 16)
467 return BaseT::getArithmeticReductionCost(Opcode, Ty, IsPairwise);
469 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
470 return LT.first * getFullRateInstrCost();
473 int GCNTTIImpl::getMinMaxReductionCost(Type *Ty, Type *CondTy,
476 EVT OrigTy = TLI->getValueType(DL, Ty);
478 // Computes cost on targets that have packed math instructions(which support
479 // 16-bit types only).
481 !ST->hasVOP3PInsts() ||
482 OrigTy.getScalarSizeInBits() != 16)
483 return BaseT::getMinMaxReductionCost(Ty, CondTy, IsPairwise, IsUnsigned);
485 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
486 return LT.first * getHalfRateInstrCost();
489 int GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
492 case Instruction::ExtractElement:
493 case Instruction::InsertElement: {
495 = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType());
497 if (EltSize == 16 && Index == 0 && ST->has16BitInsts())
499 return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
502 // Extracts are just reads of a subregister, so are free. Inserts are
503 // considered free because we don't want to have any cost for scalarizing
504 // operations, and we don't have to copy into a different register class.
506 // Dynamic indexing isn't free and is best avoided.
507 return Index == ~0u ? 2 : 0;
510 return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
516 static bool isArgPassedInSGPR(const Argument *A) {
517 const Function *F = A->getParent();
519 // Arguments to compute shaders are never a source of divergence.
520 CallingConv::ID CC = F->getCallingConv();
522 case CallingConv::AMDGPU_KERNEL:
523 case CallingConv::SPIR_KERNEL:
525 case CallingConv::AMDGPU_VS:
526 case CallingConv::AMDGPU_LS:
527 case CallingConv::AMDGPU_HS:
528 case CallingConv::AMDGPU_ES:
529 case CallingConv::AMDGPU_GS:
530 case CallingConv::AMDGPU_PS:
531 case CallingConv::AMDGPU_CS:
532 // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
533 // Everything else is in VGPRs.
534 return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
535 F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
537 // TODO: Should calls support inreg for SGPR inputs?
542 /// \returns true if the result of the value could potentially be
543 /// different across workitems in a wavefront.
544 bool GCNTTIImpl::isSourceOfDivergence(const Value *V) const {
545 if (const Argument *A = dyn_cast<Argument>(V))
546 return !isArgPassedInSGPR(A);
548 // Loads from the private and flat address spaces are divergent, because
549 // threads can execute the load instruction with the same inputs and get
550 // different results.
552 // All other loads are not divergent, because if threads issue loads with the
553 // same arguments, they will always get the same result.
554 if (const LoadInst *Load = dyn_cast<LoadInst>(V))
555 return Load->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
556 Load->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
558 // Atomics are divergent because they are executed sequentially: when an
559 // atomic operation refers to the same address in each thread, then each
560 // thread after the first sees the value written by the previous thread as
562 if (isa<AtomicRMWInst>(V) || isa<AtomicCmpXchgInst>(V))
565 if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V))
566 return AMDGPU::isIntrinsicSourceOfDivergence(Intrinsic->getIntrinsicID());
568 // Assume all function calls are a source of divergence.
569 if (isa<CallInst>(V) || isa<InvokeInst>(V))
575 bool GCNTTIImpl::isAlwaysUniform(const Value *V) const {
576 if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
577 switch (Intrinsic->getIntrinsicID()) {
580 case Intrinsic::amdgcn_readfirstlane:
581 case Intrinsic::amdgcn_readlane:
588 unsigned GCNTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
590 if (ST->hasVOP3PInsts()) {
591 VectorType *VT = cast<VectorType>(Tp);
592 if (VT->getNumElements() == 2 &&
593 DL.getTypeSizeInBits(VT->getElementType()) == 16) {
594 // With op_sel VOP3P instructions freely can access the low half or high
595 // half of a register, so any swizzle is free.
598 case TTI::SK_Broadcast:
599 case TTI::SK_Reverse:
600 case TTI::SK_PermuteSingleSrc:
608 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
611 bool GCNTTIImpl::areInlineCompatible(const Function *Caller,
612 const Function *Callee) const {
613 const TargetMachine &TM = getTLI()->getTargetMachine();
614 const FeatureBitset &CallerBits =
615 TM.getSubtargetImpl(*Caller)->getFeatureBits();
616 const FeatureBitset &CalleeBits =
617 TM.getSubtargetImpl(*Callee)->getFeatureBits();
619 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
620 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
621 return ((RealCallerBits & RealCalleeBits) == RealCalleeBits);
624 void GCNTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
625 TTI::UnrollingPreferences &UP) {
626 CommonTTI.getUnrollingPreferences(L, SE, UP);
629 unsigned R600TTIImpl::getHardwareNumberOfRegisters(bool Vec) const {
630 return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
633 unsigned R600TTIImpl::getNumberOfRegisters(bool Vec) const {
634 return getHardwareNumberOfRegisters(Vec);
637 unsigned R600TTIImpl::getRegisterBitWidth(bool Vector) const {
641 unsigned R600TTIImpl::getMinVectorRegisterBitWidth() const {
645 unsigned R600TTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
646 if (AddrSpace == AMDGPUAS::GLOBAL_ADDRESS ||
647 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS)
649 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
650 AddrSpace == AMDGPUAS::REGION_ADDRESS)
652 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
655 if ((AddrSpace == AMDGPUAS::PARAM_D_ADDRESS ||
656 AddrSpace == AMDGPUAS::PARAM_I_ADDRESS ||
657 (AddrSpace >= AMDGPUAS::CONSTANT_BUFFER_0 &&
658 AddrSpace <= AMDGPUAS::CONSTANT_BUFFER_15)))
660 llvm_unreachable("unhandled address space");
663 bool R600TTIImpl::isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
665 unsigned AddrSpace) const {
666 // We allow vectorization of flat stores, even though we may need to decompose
667 // them later if they may access private memory. We don't have enough context
668 // here, and legalization can handle it.
669 return (AddrSpace != AMDGPUAS::PRIVATE_ADDRESS);
672 bool R600TTIImpl::isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
674 unsigned AddrSpace) const {
675 return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
678 bool R600TTIImpl::isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
680 unsigned AddrSpace) const {
681 return isLegalToVectorizeMemChain(ChainSizeInBytes, Alignment, AddrSpace);
684 unsigned R600TTIImpl::getMaxInterleaveFactor(unsigned VF) {
685 // Disable unrolling if the loop is not vectorized.
686 // TODO: Enable this again.
693 unsigned R600TTIImpl::getCFInstrCost(unsigned Opcode) {
694 // XXX - For some reason this isn't called for switch.
696 case Instruction::Br:
697 case Instruction::Ret:
700 return BaseT::getCFInstrCost(Opcode);
704 int R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
707 case Instruction::ExtractElement:
708 case Instruction::InsertElement: {
710 = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType());
712 return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
715 // Extracts are just reads of a subregister, so are free. Inserts are
716 // considered free because we don't want to have any cost for scalarizing
717 // operations, and we don't have to copy into a different register class.
719 // Dynamic indexing isn't free and is best avoided.
720 return Index == ~0u ? 2 : 0;
723 return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
727 void R600TTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
728 TTI::UnrollingPreferences &UP) {
729 CommonTTI.getUnrollingPreferences(L, SE, UP);