1 //===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "AMDKernelCodeT.h"
11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
13 #include "SIDefines.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "Utils/AMDKernelCodeTUtils.h"
16 #include "Utils/AMDGPUAsmUtils.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineValueType.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
36 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
37 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
38 #include "llvm/MC/MCRegisterInfo.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSubtargetInfo.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/ELF.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Support/SMLoc.h"
48 #include "llvm/Support/TargetRegistry.h"
59 using namespace llvm::AMDGPU;
63 class AMDGPUAsmParser;
65 enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_TTMP, IS_SPECIAL };
67 //===----------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
71 class AMDGPUOperand : public MCParsedAsmOperand {
79 SMLoc StartLoc, EndLoc;
80 const AMDGPUAsmParser *AsmParser;
83 AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)
84 : MCParsedAsmOperand(), Kind(Kind_), AsmParser(AsmParser_) {}
86 typedef std::unique_ptr<AMDGPUOperand> Ptr;
93 bool hasFPModifiers() const { return Abs || Neg; }
94 bool hasIntModifiers() const { return Sext; }
95 bool hasModifiers() const { return hasFPModifiers() || hasIntModifiers(); }
97 int64_t getFPModifiersOperand() const {
99 Operand |= Abs ? SISrcMods::ABS : 0;
100 Operand |= Neg ? SISrcMods::NEG : 0;
104 int64_t getIntModifiersOperand() const {
106 Operand |= Sext ? SISrcMods::SEXT : 0;
110 int64_t getModifiersOperand() const {
111 assert(!(hasFPModifiers() && hasIntModifiers())
112 && "fp and int modifiers should not be used simultaneously");
113 if (hasFPModifiers()) {
114 return getFPModifiersOperand();
115 } else if (hasIntModifiers()) {
116 return getIntModifiersOperand();
122 friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);
192 bool isToken() const override {
196 if (Kind != Expression || !Expr)
199 // When parsing operands, we can't always tell if something was meant to be
200 // a token, like 'gds', or an expression that references a global variable.
201 // In this case, we assume the string is an expression, and if we need to
202 // interpret is a token, then we treat the symbol name as the token.
203 return isa<MCSymbolRefExpr>(Expr);
206 bool isImm() const override {
207 return Kind == Immediate;
210 bool isInlinableImm(MVT type) const;
211 bool isLiteralImm(MVT type) const;
213 bool isRegKind() const {
214 return Kind == Register;
217 bool isReg() const override {
218 return isRegKind() && !hasModifiers();
221 bool isRegOrImmWithInputMods(MVT type) const {
222 return isRegKind() || isInlinableImm(type);
225 bool isRegOrImmWithInt16InputMods() const {
226 return isRegOrImmWithInputMods(MVT::i16);
229 bool isRegOrImmWithInt32InputMods() const {
230 return isRegOrImmWithInputMods(MVT::i32);
233 bool isRegOrImmWithInt64InputMods() const {
234 return isRegOrImmWithInputMods(MVT::i64);
237 bool isRegOrImmWithFP16InputMods() const {
238 return isRegOrImmWithInputMods(MVT::f16);
241 bool isRegOrImmWithFP32InputMods() const {
242 return isRegOrImmWithInputMods(MVT::f32);
245 bool isRegOrImmWithFP64InputMods() const {
246 return isRegOrImmWithInputMods(MVT::f64);
249 bool isVReg() const {
250 return isRegClass(AMDGPU::VGPR_32RegClassID) ||
251 isRegClass(AMDGPU::VReg_64RegClassID) ||
252 isRegClass(AMDGPU::VReg_96RegClassID) ||
253 isRegClass(AMDGPU::VReg_128RegClassID) ||
254 isRegClass(AMDGPU::VReg_256RegClassID) ||
255 isRegClass(AMDGPU::VReg_512RegClassID);
258 bool isVReg32OrOff() const {
259 return isOff() || isRegClass(AMDGPU::VGPR_32RegClassID);
262 bool isImmTy(ImmTy ImmT) const {
263 return isImm() && Imm.Type == ImmT;
266 bool isImmModifier() const {
267 return isImm() && Imm.Type != ImmTyNone;
270 bool isClampSI() const { return isImmTy(ImmTyClampSI); }
271 bool isOModSI() const { return isImmTy(ImmTyOModSI); }
272 bool isDMask() const { return isImmTy(ImmTyDMask); }
273 bool isUNorm() const { return isImmTy(ImmTyUNorm); }
274 bool isDA() const { return isImmTy(ImmTyDA); }
275 bool isR128() const { return isImmTy(ImmTyUNorm); }
276 bool isLWE() const { return isImmTy(ImmTyLWE); }
277 bool isOff() const { return isImmTy(ImmTyOff); }
278 bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
279 bool isExpVM() const { return isImmTy(ImmTyExpVM); }
280 bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }
281 bool isOffen() const { return isImmTy(ImmTyOffen); }
282 bool isIdxen() const { return isImmTy(ImmTyIdxen); }
283 bool isAddr64() const { return isImmTy(ImmTyAddr64); }
284 bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }
285 bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<16>(getImm()); }
286 bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
287 bool isGDS() const { return isImmTy(ImmTyGDS); }
288 bool isGLC() const { return isImmTy(ImmTyGLC); }
289 bool isSLC() const { return isImmTy(ImmTySLC); }
290 bool isTFE() const { return isImmTy(ImmTyTFE); }
291 bool isBankMask() const { return isImmTy(ImmTyDppBankMask); }
292 bool isRowMask() const { return isImmTy(ImmTyDppRowMask); }
293 bool isBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }
294 bool isSDWADstSel() const { return isImmTy(ImmTySdwaDstSel); }
295 bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); }
296 bool isSDWASrc1Sel() const { return isImmTy(ImmTySdwaSrc1Sel); }
297 bool isSDWADstUnused() const { return isImmTy(ImmTySdwaDstUnused); }
298 bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }
299 bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }
300 bool isAttrChan() const { return isImmTy(ImmTyAttrChan); }
301 bool isOpSel() const { return isImmTy(ImmTyOpSel); }
302 bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
303 bool isNegLo() const { return isImmTy(ImmTyNegLo); }
304 bool isNegHi() const { return isImmTy(ImmTyNegHi); }
307 return isClampSI() || isOModSI();
310 bool isRegOrImm() const {
311 return isReg() || isImm();
314 bool isRegClass(unsigned RCID) const;
316 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {
317 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers();
320 bool isSCSrcB16() const {
321 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16);
324 bool isSCSrcV2B16() const {
328 bool isSCSrcB32() const {
329 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);
332 bool isSCSrcB64() const {
333 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);
336 bool isSCSrcF16() const {
337 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);
340 bool isSCSrcV2F16() const {
344 bool isSCSrcF32() const {
345 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);
348 bool isSCSrcF64() const {
349 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);
352 bool isSSrcB32() const {
353 return isSCSrcB32() || isLiteralImm(MVT::i32) || isExpr();
356 bool isSSrcB16() const {
357 return isSCSrcB16() || isLiteralImm(MVT::i16);
360 bool isSSrcV2B16() const {
361 llvm_unreachable("cannot happen");
365 bool isSSrcB64() const {
366 // TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
368 return isSCSrcB64() || isLiteralImm(MVT::i64);
371 bool isSSrcF32() const {
372 return isSCSrcB32() || isLiteralImm(MVT::f32) || isExpr();
375 bool isSSrcF64() const {
376 return isSCSrcB64() || isLiteralImm(MVT::f64);
379 bool isSSrcF16() const {
380 return isSCSrcB16() || isLiteralImm(MVT::f16);
383 bool isSSrcV2F16() const {
384 llvm_unreachable("cannot happen");
388 bool isVCSrcB32() const {
389 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32);
392 bool isVCSrcB64() const {
393 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);
396 bool isVCSrcB16() const {
397 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16);
400 bool isVCSrcV2B16() const {
404 bool isVCSrcF32() const {
405 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32);
408 bool isVCSrcF64() const {
409 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
412 bool isVCSrcF16() const {
413 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);
416 bool isVCSrcV2F16() const {
420 bool isVSrcB32() const {
421 return isVCSrcF32() || isLiteralImm(MVT::i32);
424 bool isVSrcB64() const {
425 return isVCSrcF64() || isLiteralImm(MVT::i64);
428 bool isVSrcB16() const {
429 return isVCSrcF16() || isLiteralImm(MVT::i16);
432 bool isVSrcV2B16() const {
433 llvm_unreachable("cannot happen");
437 bool isVSrcF32() const {
438 return isVCSrcF32() || isLiteralImm(MVT::f32);
441 bool isVSrcF64() const {
442 return isVCSrcF64() || isLiteralImm(MVT::f64);
445 bool isVSrcF16() const {
446 return isVCSrcF16() || isLiteralImm(MVT::f16);
449 bool isVSrcV2F16() const {
450 llvm_unreachable("cannot happen");
454 bool isKImmFP32() const {
455 return isLiteralImm(MVT::f32);
458 bool isKImmFP16() const {
459 return isLiteralImm(MVT::f16);
462 bool isMem() const override {
466 bool isExpr() const {
467 return Kind == Expression;
470 bool isSoppBrTarget() const {
471 return isExpr() || isImm();
474 bool isSWaitCnt() const;
475 bool isHwreg() const;
476 bool isSendMsg() const;
477 bool isSMRDOffset8() const;
478 bool isSMRDOffset20() const;
479 bool isSMRDLiteralOffset() const;
480 bool isDPPCtrl() const;
481 bool isGPRIdxMode() const;
483 StringRef getExpressionAsToken() const {
485 const MCSymbolRefExpr *S = cast<MCSymbolRefExpr>(Expr);
486 return S->getSymbol().getName();
489 StringRef getToken() const {
492 if (Kind == Expression)
493 return getExpressionAsToken();
495 return StringRef(Tok.Data, Tok.Length);
498 int64_t getImm() const {
503 ImmTy getImmTy() const {
508 unsigned getReg() const override {
512 SMLoc getStartLoc() const override {
516 SMLoc getEndLoc() const override {
520 Modifiers getModifiers() const {
521 assert(isRegKind() || isImmTy(ImmTyNone));
522 return isRegKind() ? Reg.Mods : Imm.Mods;
525 void setModifiers(Modifiers Mods) {
526 assert(isRegKind() || isImmTy(ImmTyNone));
533 bool hasModifiers() const {
534 return getModifiers().hasModifiers();
537 bool hasFPModifiers() const {
538 return getModifiers().hasFPModifiers();
541 bool hasIntModifiers() const {
542 return getModifiers().hasIntModifiers();
545 uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const;
547 void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;
549 void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;
551 template <unsigned Bitwidth>
552 void addKImmFPOperands(MCInst &Inst, unsigned N) const;
554 void addKImmFP16Operands(MCInst &Inst, unsigned N) const {
555 addKImmFPOperands<16>(Inst, N);
558 void addKImmFP32Operands(MCInst &Inst, unsigned N) const {
559 addKImmFPOperands<32>(Inst, N);
562 void addRegOperands(MCInst &Inst, unsigned N) const;
564 void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
566 addRegOperands(Inst, N);
568 Inst.addOperand(MCOperand::createExpr(Expr));
570 addImmOperands(Inst, N);
573 void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {
574 Modifiers Mods = getModifiers();
575 Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));
577 addRegOperands(Inst, N);
579 addImmOperands(Inst, N, false);
583 void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const {
584 assert(!hasIntModifiers());
585 addRegOrImmWithInputModsOperands(Inst, N);
588 void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const {
589 assert(!hasFPModifiers());
590 addRegOrImmWithInputModsOperands(Inst, N);
593 void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
594 Modifiers Mods = getModifiers();
595 Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));
597 addRegOperands(Inst, N);
600 void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const {
601 assert(!hasIntModifiers());
602 addRegWithInputModsOperands(Inst, N);
605 void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const {
606 assert(!hasFPModifiers());
607 addRegWithInputModsOperands(Inst, N);
610 void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
612 addImmOperands(Inst, N);
615 Inst.addOperand(MCOperand::createExpr(Expr));
619 static void printImmTy(raw_ostream& OS, ImmTy Type) {
621 case ImmTyNone: OS << "None"; break;
622 case ImmTyGDS: OS << "GDS"; break;
623 case ImmTyOffen: OS << "Offen"; break;
624 case ImmTyIdxen: OS << "Idxen"; break;
625 case ImmTyAddr64: OS << "Addr64"; break;
626 case ImmTyOffset: OS << "Offset"; break;
627 case ImmTyOffset0: OS << "Offset0"; break;
628 case ImmTyOffset1: OS << "Offset1"; break;
629 case ImmTyGLC: OS << "GLC"; break;
630 case ImmTySLC: OS << "SLC"; break;
631 case ImmTyTFE: OS << "TFE"; break;
632 case ImmTyClampSI: OS << "ClampSI"; break;
633 case ImmTyOModSI: OS << "OModSI"; break;
634 case ImmTyDppCtrl: OS << "DppCtrl"; break;
635 case ImmTyDppRowMask: OS << "DppRowMask"; break;
636 case ImmTyDppBankMask: OS << "DppBankMask"; break;
637 case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break;
638 case ImmTySdwaDstSel: OS << "SdwaDstSel"; break;
639 case ImmTySdwaSrc0Sel: OS << "SdwaSrc0Sel"; break;
640 case ImmTySdwaSrc1Sel: OS << "SdwaSrc1Sel"; break;
641 case ImmTySdwaDstUnused: OS << "SdwaDstUnused"; break;
642 case ImmTyDMask: OS << "DMask"; break;
643 case ImmTyUNorm: OS << "UNorm"; break;
644 case ImmTyDA: OS << "DA"; break;
645 case ImmTyR128: OS << "R128"; break;
646 case ImmTyLWE: OS << "LWE"; break;
647 case ImmTyOff: OS << "Off"; break;
648 case ImmTyExpTgt: OS << "ExpTgt"; break;
649 case ImmTyExpCompr: OS << "ExpCompr"; break;
650 case ImmTyExpVM: OS << "ExpVM"; break;
651 case ImmTyHwreg: OS << "Hwreg"; break;
652 case ImmTySendMsg: OS << "SendMsg"; break;
653 case ImmTyInterpSlot: OS << "InterpSlot"; break;
654 case ImmTyInterpAttr: OS << "InterpAttr"; break;
655 case ImmTyAttrChan: OS << "AttrChan"; break;
656 case ImmTyOpSel: OS << "OpSel"; break;
657 case ImmTyOpSelHi: OS << "OpSelHi"; break;
658 case ImmTyNegLo: OS << "NegLo"; break;
659 case ImmTyNegHi: OS << "NegHi"; break;
663 void print(raw_ostream &OS) const override {
666 OS << "<register " << getReg() << " mods: " << Reg.Mods << '>';
669 OS << '<' << getImm();
670 if (getImmTy() != ImmTyNone) {
671 OS << " type: "; printImmTy(OS, getImmTy());
673 OS << " mods: " << Imm.Mods << '>';
676 OS << '\'' << getToken() << '\'';
679 OS << "<expr " << *Expr << '>';
684 static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,
685 int64_t Val, SMLoc Loc,
686 ImmTy Type = ImmTyNone,
687 bool IsFPImm = false) {
688 auto Op = llvm::make_unique<AMDGPUOperand>(Immediate, AsmParser);
690 Op->Imm.IsFPImm = IsFPImm;
692 Op->Imm.Mods = Modifiers();
698 static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,
699 StringRef Str, SMLoc Loc,
700 bool HasExplicitEncodingSize = true) {
701 auto Res = llvm::make_unique<AMDGPUOperand>(Token, AsmParser);
702 Res->Tok.Data = Str.data();
703 Res->Tok.Length = Str.size();
709 static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,
710 unsigned RegNo, SMLoc S,
713 auto Op = llvm::make_unique<AMDGPUOperand>(Register, AsmParser);
714 Op->Reg.RegNo = RegNo;
715 Op->Reg.Mods = Modifiers();
716 Op->Reg.IsForcedVOP3 = ForceVOP3;
722 static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,
723 const class MCExpr *Expr, SMLoc S) {
724 auto Op = llvm::make_unique<AMDGPUOperand>(Expression, AsmParser);
732 raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) {
733 OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;
737 //===----------------------------------------------------------------------===//
739 //===----------------------------------------------------------------------===//
741 // Holds info related to the current kernel, e.g. count of SGPRs used.
742 // Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next
743 // .amdgpu_hsa_kernel or at EOF.
744 class KernelScopeInfo {
745 int SgprIndexUnusedMin = -1;
746 int VgprIndexUnusedMin = -1;
747 MCContext *Ctx = nullptr;
749 void usesSgprAt(int i) {
750 if (i >= SgprIndexUnusedMin) {
751 SgprIndexUnusedMin = ++i;
753 MCSymbol * const Sym = Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count"));
754 Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx));
759 void usesVgprAt(int i) {
760 if (i >= VgprIndexUnusedMin) {
761 VgprIndexUnusedMin = ++i;
763 MCSymbol * const Sym = Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));
764 Sym->setVariableValue(MCConstantExpr::create(VgprIndexUnusedMin, *Ctx));
770 KernelScopeInfo() = default;
772 void initialize(MCContext &Context) {
774 usesSgprAt(SgprIndexUnusedMin = -1);
775 usesVgprAt(VgprIndexUnusedMin = -1);
778 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) {
780 case IS_SGPR: usesSgprAt(DwordRegIndex + RegWidth - 1); break;
781 case IS_VGPR: usesVgprAt(DwordRegIndex + RegWidth - 1); break;
787 class AMDGPUAsmParser : public MCTargetAsmParser {
788 const MCInstrInfo &MII;
791 unsigned ForcedEncodingSize = 0;
792 bool ForcedDPP = false;
793 bool ForcedSDWA = false;
794 KernelScopeInfo KernelScope;
796 /// @name Auto-generated Match Functions
799 #define GET_ASSEMBLER_HEADER
800 #include "AMDGPUGenAsmMatcher.inc"
805 bool ParseAsAbsoluteExpression(uint32_t &Ret);
806 bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
807 bool ParseDirectiveHSACodeObjectVersion();
808 bool ParseDirectiveHSACodeObjectISA();
809 bool ParseDirectiveCodeObjectMetadata();
810 bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
811 bool ParseDirectiveAMDKernelCodeT();
812 bool ParseSectionDirectiveHSAText();
813 bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
814 bool ParseDirectiveAMDGPUHsaKernel();
815 bool ParseDirectiveAMDGPUHsaModuleGlobal();
816 bool ParseDirectiveAMDGPUHsaProgramGlobal();
817 bool ParseSectionDirectiveHSADataGlobalAgent();
818 bool ParseSectionDirectiveHSADataGlobalProgram();
819 bool ParseSectionDirectiveHSARodataReadonlyAgent();
820 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
821 RegisterKind RegKind, unsigned Reg1,
823 bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg,
824 unsigned& RegNum, unsigned& RegWidth,
825 unsigned *DwordRegIndex);
826 void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
827 bool IsAtomic, bool IsAtomicReturn);
828 void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
829 bool IsGdsHardcoded);
832 enum AMDGPUMatchResultTy {
833 Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
836 typedef std::map<AMDGPUOperand::ImmTy, unsigned> OptionalImmIndexMap;
838 AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
839 const MCInstrInfo &MII,
840 const MCTargetOptions &Options)
841 : MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser) {
842 MCAsmParserExtension::Initialize(Parser);
844 if (getFeatureBits().none()) {
845 // Set default features.
846 copySTI().ToggleFeature("SOUTHERN_ISLANDS");
849 setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));
852 // TODO: make those pre-defined variables read-only.
853 // Currently there is none suitable machinery in the core llvm-mc for this.
854 // MCSymbol::isRedefinable is intended for another purpose, and
855 // AsmParser::parseDirectiveSet() cannot be specialized for specific target.
856 AMDGPU::IsaInfo::IsaVersion ISA =
857 AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
858 MCContext &Ctx = getContext();
860 Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));
861 Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
862 Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));
863 Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
864 Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));
865 Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
867 KernelScope.initialize(getContext());
871 return AMDGPU::isSI(getSTI());
875 return AMDGPU::isCI(getSTI());
879 return AMDGPU::isVI(getSTI());
882 bool hasInv2PiInlineImm() const {
883 return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
886 bool hasSGPR102_SGPR103() const {
890 AMDGPUTargetStreamer &getTargetStreamer() {
891 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
892 return static_cast<AMDGPUTargetStreamer &>(TS);
895 const MCRegisterInfo *getMRI() const {
896 // We need this const_cast because for some reason getContext() is not const
898 return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo();
901 const MCInstrInfo *getMII() const {
905 const FeatureBitset &getFeatureBits() const {
906 return getSTI().getFeatureBits();
909 void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }
910 void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }
911 void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }
913 unsigned getForcedEncodingSize() const { return ForcedEncodingSize; }
914 bool isForcedVOP3() const { return ForcedEncodingSize == 64; }
915 bool isForcedDPP() const { return ForcedDPP; }
916 bool isForcedSDWA() const { return ForcedSDWA; }
917 ArrayRef<unsigned> getMatchedVariants() const;
919 std::unique_ptr<AMDGPUOperand> parseRegister();
920 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
921 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
922 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
923 unsigned Kind) override;
924 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
925 OperandVector &Operands, MCStreamer &Out,
927 bool MatchingInlineAsm) override;
928 bool ParseDirective(AsmToken DirectiveID) override;
929 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
930 StringRef parseMnemonicSuffix(StringRef Name);
931 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
932 SMLoc NameLoc, OperandVector &Operands) override;
933 //bool ProcessInstruction(MCInst &Inst);
935 OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int);
938 parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
939 AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
940 bool (*ConvertResult)(int64_t &) = nullptr);
942 OperandMatchResultTy parseOperandArrayWithPrefix(
944 OperandVector &Operands,
945 AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
946 bool (*ConvertResult)(int64_t&) = nullptr);
949 parseNamedBit(const char *Name, OperandVector &Operands,
950 AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);
951 OperandMatchResultTy parseStringWithPrefix(StringRef Prefix,
954 bool parseAbsoluteExpr(int64_t &Val, bool AbsMod = false);
955 OperandMatchResultTy parseImm(OperandVector &Operands, bool AbsMod = false);
956 OperandMatchResultTy parseReg(OperandVector &Operands);
957 OperandMatchResultTy parseRegOrImm(OperandVector &Operands, bool AbsMod = false);
958 OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands, bool AllowImm = true);
959 OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands, bool AllowImm = true);
960 OperandMatchResultTy parseRegWithFPInputMods(OperandVector &Operands);
961 OperandMatchResultTy parseRegWithIntInputMods(OperandVector &Operands);
962 OperandMatchResultTy parseVReg32OrOff(OperandVector &Operands);
964 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
965 void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); }
966 void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); }
967 void cvtExp(MCInst &Inst, const OperandVector &Operands);
969 bool parseCnt(int64_t &IntVal);
970 OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
971 OperandMatchResultTy parseHwreg(OperandVector &Operands);
974 struct OperandInfoTy {
977 OperandInfoTy(int64_t Id_) : Id(Id_), IsSymbolic(false) { }
980 bool parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId);
981 bool parseHwregConstruct(OperandInfoTy &HwReg, int64_t &Offset, int64_t &Width);
984 OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
986 bool validateOperandLimitations(const MCInst &Inst);
987 bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
988 bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
989 unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
990 bool isSGPR(unsigned Reg);
993 OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
995 OperandMatchResultTy parseExpTgt(OperandVector &Operands);
996 OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
997 OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
998 OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
999 OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
1001 void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
1002 void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
1003 void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
1004 AMDGPUOperand::Ptr defaultGLC() const;
1005 AMDGPUOperand::Ptr defaultSLC() const;
1006 AMDGPUOperand::Ptr defaultTFE() const;
1008 AMDGPUOperand::Ptr defaultDMask() const;
1009 AMDGPUOperand::Ptr defaultUNorm() const;
1010 AMDGPUOperand::Ptr defaultDA() const;
1011 AMDGPUOperand::Ptr defaultR128() const;
1012 AMDGPUOperand::Ptr defaultLWE() const;
1013 AMDGPUOperand::Ptr defaultSMRDOffset8() const;
1014 AMDGPUOperand::Ptr defaultSMRDOffset20() const;
1015 AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
1017 OperandMatchResultTy parseOModOperand(OperandVector &Operands);
1019 void cvtId(MCInst &Inst, const OperandVector &Operands);
1020 void cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands);
1022 void cvtVOP3Impl(MCInst &Inst,
1023 const OperandVector &Operands,
1024 OptionalImmIndexMap &OptionalIdx);
1025 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1026 void cvtVOP3OMod(MCInst &Inst, const OperandVector &Operands);
1027 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1029 void cvtMIMG(MCInst &Inst, const OperandVector &Operands);
1030 void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
1032 OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
1033 AMDGPUOperand::Ptr defaultRowMask() const;
1034 AMDGPUOperand::Ptr defaultBankMask() const;
1035 AMDGPUOperand::Ptr defaultBoundCtrl() const;
1036 void cvtDPP(MCInst &Inst, const OperandVector &Operands);
1038 OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
1039 AMDGPUOperand::ImmTy Type);
1040 OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
1041 void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1042 void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1043 void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1044 void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1045 uint64_t BasicInstType);
1048 struct OptionalOperand {
1050 AMDGPUOperand::ImmTy Type;
1052 bool (*ConvertResult)(int64_t&);
1055 } // end anonymous namespace
1057 // May be called with integer type with equivalent bitwidth.
1058 static const fltSemantics *getFltSemantics(unsigned Size) {
1061 return &APFloat::IEEEsingle();
1063 return &APFloat::IEEEdouble();
1065 return &APFloat::IEEEhalf();
1067 llvm_unreachable("unsupported fp type");
1071 static const fltSemantics *getFltSemantics(MVT VT) {
1072 return getFltSemantics(VT.getSizeInBits() / 8);
1075 static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
1076 switch (OperandType) {
1077 case AMDGPU::OPERAND_REG_IMM_INT32:
1078 case AMDGPU::OPERAND_REG_IMM_FP32:
1079 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
1080 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
1081 return &APFloat::IEEEsingle();
1082 case AMDGPU::OPERAND_REG_IMM_INT64:
1083 case AMDGPU::OPERAND_REG_IMM_FP64:
1084 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
1085 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
1086 return &APFloat::IEEEdouble();
1087 case AMDGPU::OPERAND_REG_IMM_INT16:
1088 case AMDGPU::OPERAND_REG_IMM_FP16:
1089 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
1090 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
1091 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1092 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
1093 return &APFloat::IEEEhalf();
1095 llvm_unreachable("unsupported fp type");
1099 //===----------------------------------------------------------------------===//
1101 //===----------------------------------------------------------------------===//
1103 static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) {
1106 // Convert literal to single precision
1107 APFloat::opStatus Status = FPLiteral.convert(*getFltSemantics(VT),
1108 APFloat::rmNearestTiesToEven,
1110 // We allow precision lost but not overflow or underflow
1111 if (Status != APFloat::opOK &&
1113 ((Status & APFloat::opOverflow) != 0 ||
1114 (Status & APFloat::opUnderflow) != 0)) {
1121 bool AMDGPUOperand::isInlinableImm(MVT type) const {
1122 if (!isImmTy(ImmTyNone)) {
1123 // Only plain immediates are inlinable (e.g. "clamp" attribute is not)
1126 // TODO: We should avoid using host float here. It would be better to
1127 // check the float bit values which is what a few other places do.
1128 // We've had bot failures before due to weird NaN support on mips hosts.
1130 APInt Literal(64, Imm.Val);
1132 if (Imm.IsFPImm) { // We got fp literal token
1133 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
1134 return AMDGPU::isInlinableLiteral64(Imm.Val,
1135 AsmParser->hasInv2PiInlineImm());
1138 APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));
1139 if (!canLosslesslyConvertToFPType(FPLiteral, type))
1142 if (type.getScalarSizeInBits() == 16) {
1143 return AMDGPU::isInlinableLiteral16(
1144 static_cast<int16_t>(FPLiteral.bitcastToAPInt().getZExtValue()),
1145 AsmParser->hasInv2PiInlineImm());
1148 // Check if single precision literal is inlinable
1149 return AMDGPU::isInlinableLiteral32(
1150 static_cast<int32_t>(FPLiteral.bitcastToAPInt().getZExtValue()),
1151 AsmParser->hasInv2PiInlineImm());
1154 // We got int literal token.
1155 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
1156 return AMDGPU::isInlinableLiteral64(Imm.Val,
1157 AsmParser->hasInv2PiInlineImm());
1160 if (type.getScalarSizeInBits() == 16) {
1161 return AMDGPU::isInlinableLiteral16(
1162 static_cast<int16_t>(Literal.getLoBits(16).getSExtValue()),
1163 AsmParser->hasInv2PiInlineImm());
1166 return AMDGPU::isInlinableLiteral32(
1167 static_cast<int32_t>(Literal.getLoBits(32).getZExtValue()),
1168 AsmParser->hasInv2PiInlineImm());
1171 bool AMDGPUOperand::isLiteralImm(MVT type) const {
1172 // Check that this imediate can be added as literal
1173 if (!isImmTy(ImmTyNone)) {
1178 // We got int literal token.
1180 if (type == MVT::f64 && hasFPModifiers()) {
1181 // Cannot apply fp modifiers to int literals preserving the same semantics
1182 // for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity,
1183 // disable these cases.
1187 unsigned Size = type.getSizeInBits();
1191 // FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP
1193 return isUIntN(Size, Imm.Val) || isIntN(Size, Imm.Val);
1196 // We got fp literal token
1197 if (type == MVT::f64) { // Expected 64-bit fp operand
1198 // We would set low 64-bits of literal to zeroes but we accept this literals
1202 if (type == MVT::i64) { // Expected 64-bit int operand
1203 // We don't allow fp literals in 64-bit integer instructions. It is
1204 // unclear how we should encode them.
1208 APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));
1209 return canLosslesslyConvertToFPType(FPLiteral, type);
1212 bool AMDGPUOperand::isRegClass(unsigned RCID) const {
1213 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
1216 uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
1218 assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
1219 assert(Size == 2 || Size == 4 || Size == 8);
1221 const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));
1233 void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
1235 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
1236 Inst.getNumOperands())) {
1237 addLiteralImmOperand(Inst, Imm.Val,
1239 isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
1241 assert(!isImmTy(ImmTyNone) || !hasModifiers());
1242 Inst.addOperand(MCOperand::createImm(Imm.Val));
1246 void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {
1247 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
1248 auto OpNum = Inst.getNumOperands();
1249 // Check that this operand accepts literals
1250 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));
1252 if (ApplyModifiers) {
1253 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));
1254 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);
1255 Val = applyInputFPModifiers(Val, Size);
1258 APInt Literal(64, Val);
1259 uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType;
1261 if (Imm.IsFPImm) { // We got fp literal token
1263 case AMDGPU::OPERAND_REG_IMM_INT64:
1264 case AMDGPU::OPERAND_REG_IMM_FP64:
1265 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
1266 case AMDGPU::OPERAND_REG_INLINE_C_FP64: {
1267 if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
1268 AsmParser->hasInv2PiInlineImm())) {
1269 Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
1274 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand
1275 // For fp operands we check if low 32 bits are zeros
1276 if (Literal.getLoBits(32) != 0) {
1277 const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(Inst.getLoc(),
1278 "Can't encode literal as exact 64-bit floating-point operand. "
1279 "Low 32-bits will be set to zero");
1282 Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue()));
1286 // We don't allow fp literals in 64-bit integer instructions. It is
1287 // unclear how we should encode them. This case should be checked earlier
1288 // in predicate methods (isLiteralImm())
1289 llvm_unreachable("fp literal in 64-bit integer instruction.");
1291 case AMDGPU::OPERAND_REG_IMM_INT32:
1292 case AMDGPU::OPERAND_REG_IMM_FP32:
1293 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
1294 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
1295 case AMDGPU::OPERAND_REG_IMM_INT16:
1296 case AMDGPU::OPERAND_REG_IMM_FP16:
1297 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
1298 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
1299 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1300 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
1302 APFloat FPLiteral(APFloat::IEEEdouble(), Literal);
1303 // Convert literal to single precision
1304 FPLiteral.convert(*getOpFltSemantics(OpTy),
1305 APFloat::rmNearestTiesToEven, &lost);
1306 // We allow precision lost but not overflow or underflow. This should be
1307 // checked earlier in isLiteralImm()
1309 uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();
1310 if (OpTy == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 ||
1311 OpTy == AMDGPU::OPERAND_REG_INLINE_C_V2FP16) {
1312 ImmVal |= (ImmVal << 16);
1315 Inst.addOperand(MCOperand::createImm(ImmVal));
1319 llvm_unreachable("invalid operand size");
1325 // We got int literal token.
1326 // Only sign extend inline immediates.
1327 // FIXME: No errors on truncation
1329 case AMDGPU::OPERAND_REG_IMM_INT32:
1330 case AMDGPU::OPERAND_REG_IMM_FP32:
1331 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
1332 case AMDGPU::OPERAND_REG_INLINE_C_FP32: {
1333 if (isInt<32>(Val) &&
1334 AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val),
1335 AsmParser->hasInv2PiInlineImm())) {
1336 Inst.addOperand(MCOperand::createImm(Val));
1340 Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));
1343 case AMDGPU::OPERAND_REG_IMM_INT64:
1344 case AMDGPU::OPERAND_REG_IMM_FP64:
1345 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
1346 case AMDGPU::OPERAND_REG_INLINE_C_FP64: {
1347 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
1348 Inst.addOperand(MCOperand::createImm(Val));
1352 Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
1355 case AMDGPU::OPERAND_REG_IMM_INT16:
1356 case AMDGPU::OPERAND_REG_IMM_FP16:
1357 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
1358 case AMDGPU::OPERAND_REG_INLINE_C_FP16: {
1359 if (isInt<16>(Val) &&
1360 AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val),
1361 AsmParser->hasInv2PiInlineImm())) {
1362 Inst.addOperand(MCOperand::createImm(Val));
1366 Inst.addOperand(MCOperand::createImm(Val & 0xffff));
1369 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1370 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
1371 auto LiteralVal = static_cast<uint16_t>(Literal.getLoBits(16).getZExtValue());
1372 assert(AMDGPU::isInlinableLiteral16(LiteralVal,
1373 AsmParser->hasInv2PiInlineImm()));
1375 uint32_t ImmVal = static_cast<uint32_t>(LiteralVal) << 16 |
1376 static_cast<uint32_t>(LiteralVal);
1377 Inst.addOperand(MCOperand::createImm(ImmVal));
1381 llvm_unreachable("invalid operand size");
1385 template <unsigned Bitwidth>
1386 void AMDGPUOperand::addKImmFPOperands(MCInst &Inst, unsigned N) const {
1387 APInt Literal(64, Imm.Val);
1390 // We got int literal token.
1391 Inst.addOperand(MCOperand::createImm(Literal.getLoBits(Bitwidth).getZExtValue()));
1396 APFloat FPLiteral(APFloat::IEEEdouble(), Literal);
1397 FPLiteral.convert(*getFltSemantics(Bitwidth / 8),
1398 APFloat::rmNearestTiesToEven, &Lost);
1399 Inst.addOperand(MCOperand::createImm(FPLiteral.bitcastToAPInt().getZExtValue()));
1402 void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {
1403 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));
1406 //===----------------------------------------------------------------------===//
1408 //===----------------------------------------------------------------------===//
1410 static int getRegClass(RegisterKind Is, unsigned RegWidth) {
1411 if (Is == IS_VGPR) {
1414 case 1: return AMDGPU::VGPR_32RegClassID;
1415 case 2: return AMDGPU::VReg_64RegClassID;
1416 case 3: return AMDGPU::VReg_96RegClassID;
1417 case 4: return AMDGPU::VReg_128RegClassID;
1418 case 8: return AMDGPU::VReg_256RegClassID;
1419 case 16: return AMDGPU::VReg_512RegClassID;
1421 } else if (Is == IS_TTMP) {
1424 case 1: return AMDGPU::TTMP_32RegClassID;
1425 case 2: return AMDGPU::TTMP_64RegClassID;
1426 case 4: return AMDGPU::TTMP_128RegClassID;
1428 } else if (Is == IS_SGPR) {
1431 case 1: return AMDGPU::SGPR_32RegClassID;
1432 case 2: return AMDGPU::SGPR_64RegClassID;
1433 case 4: return AMDGPU::SGPR_128RegClassID;
1434 case 8: return AMDGPU::SReg_256RegClassID;
1435 case 16: return AMDGPU::SReg_512RegClassID;
1441 static unsigned getSpecialRegForName(StringRef RegName) {
1442 return StringSwitch<unsigned>(RegName)
1443 .Case("exec", AMDGPU::EXEC)
1444 .Case("vcc", AMDGPU::VCC)
1445 .Case("flat_scratch", AMDGPU::FLAT_SCR)
1446 .Case("m0", AMDGPU::M0)
1447 .Case("scc", AMDGPU::SCC)
1448 .Case("tba", AMDGPU::TBA)
1449 .Case("tma", AMDGPU::TMA)
1450 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
1451 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
1452 .Case("vcc_lo", AMDGPU::VCC_LO)
1453 .Case("vcc_hi", AMDGPU::VCC_HI)
1454 .Case("exec_lo", AMDGPU::EXEC_LO)
1455 .Case("exec_hi", AMDGPU::EXEC_HI)
1456 .Case("tma_lo", AMDGPU::TMA_LO)
1457 .Case("tma_hi", AMDGPU::TMA_HI)
1458 .Case("tba_lo", AMDGPU::TBA_LO)
1459 .Case("tba_hi", AMDGPU::TBA_HI)
1463 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1465 auto R = parseRegister();
1466 if (!R) return true;
1468 RegNo = R->getReg();
1469 StartLoc = R->getStartLoc();
1470 EndLoc = R->getEndLoc();
1474 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
1475 RegisterKind RegKind, unsigned Reg1,
1479 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {
1484 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {
1485 Reg = AMDGPU::FLAT_SCR;
1489 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) {
1494 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) {
1499 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) {
1508 if (Reg1 != Reg + RegWidth) {
1514 llvm_unreachable("unexpected register kind");
1518 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
1519 unsigned &RegNum, unsigned &RegWidth,
1520 unsigned *DwordRegIndex) {
1521 if (DwordRegIndex) { *DwordRegIndex = 0; }
1522 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
1523 if (getLexer().is(AsmToken::Identifier)) {
1524 StringRef RegName = Parser.getTok().getString();
1525 if ((Reg = getSpecialRegForName(RegName))) {
1527 RegKind = IS_SPECIAL;
1529 unsigned RegNumIndex = 0;
1530 if (RegName[0] == 'v') {
1533 } else if (RegName[0] == 's') {
1536 } else if (RegName.startswith("ttmp")) {
1537 RegNumIndex = strlen("ttmp");
1542 if (RegName.size() > RegNumIndex) {
1543 // Single 32-bit register: vXX.
1544 if (RegName.substr(RegNumIndex).getAsInteger(10, RegNum))
1549 // Range of registers: v[XX:YY]. ":YY" is optional.
1551 int64_t RegLo, RegHi;
1552 if (getLexer().isNot(AsmToken::LBrac))
1556 if (getParser().parseAbsoluteExpression(RegLo))
1559 const bool isRBrace = getLexer().is(AsmToken::RBrac);
1560 if (!isRBrace && getLexer().isNot(AsmToken::Colon))
1567 if (getParser().parseAbsoluteExpression(RegHi))
1570 if (getLexer().isNot(AsmToken::RBrac))
1574 RegNum = (unsigned) RegLo;
1575 RegWidth = (RegHi - RegLo) + 1;
1578 } else if (getLexer().is(AsmToken::LBrac)) {
1579 // List of consecutive registers: [s0,s1,s2,s3]
1581 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, nullptr))
1585 RegisterKind RegKind1;
1586 unsigned Reg1, RegNum1, RegWidth1;
1588 if (getLexer().is(AsmToken::Comma)) {
1590 } else if (getLexer().is(AsmToken::RBrac)) {
1593 } else if (ParseAMDGPURegister(RegKind1, Reg1, RegNum1, RegWidth1, nullptr)) {
1594 if (RegWidth1 != 1) {
1597 if (RegKind1 != RegKind) {
1600 if (!AddNextRegisterToList(Reg, RegWidth, RegKind1, Reg1, RegNum1)) {
1620 if (RegKind == IS_SGPR || RegKind == IS_TTMP) {
1621 // SGPR and TTMP registers must be aligned. Max required alignment is 4 dwords.
1622 Size = std::min(RegWidth, 4u);
1624 if (RegNum % Size != 0)
1626 if (DwordRegIndex) { *DwordRegIndex = RegNum; }
1627 RegNum = RegNum / Size;
1628 int RCID = getRegClass(RegKind, RegWidth);
1631 const MCRegisterClass RC = TRI->getRegClass(RCID);
1632 if (RegNum >= RC.getNumRegs())
1634 Reg = RC.getRegister(RegNum);
1639 llvm_unreachable("unexpected register kind");
1642 if (!subtargetHasRegister(*TRI, Reg))
1647 std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister() {
1648 const auto &Tok = Parser.getTok();
1649 SMLoc StartLoc = Tok.getLoc();
1650 SMLoc EndLoc = Tok.getEndLoc();
1651 RegisterKind RegKind;
1652 unsigned Reg, RegNum, RegWidth, DwordRegIndex;
1654 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, &DwordRegIndex)) {
1657 KernelScope.usesRegister(RegKind, DwordRegIndex, RegWidth);
1658 return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc, false);
1662 AMDGPUAsmParser::parseAbsoluteExpr(int64_t &Val, bool AbsMod) {
1663 if (AbsMod && getLexer().peekTok().is(AsmToken::Pipe) &&
1664 (getLexer().getKind() == AsmToken::Integer ||
1665 getLexer().getKind() == AsmToken::Real)) {
1667 // This is a workaround for handling operands like these:
1670 // This syntax is not compatible with syntax of standard
1671 // MC expressions (due to the trailing '|').
1676 if (getParser().parsePrimaryExpr(Expr, EndLoc)) {
1680 return !Expr->evaluateAsAbsolute(Val);
1683 return getParser().parseAbsoluteExpression(Val);
1686 OperandMatchResultTy
1687 AMDGPUAsmParser::parseImm(OperandVector &Operands, bool AbsMod) {
1688 // TODO: add syntactic sugar for 1/(2*PI)
1690 if (getLexer().getKind() == AsmToken::Minus) {
1695 SMLoc S = Parser.getTok().getLoc();
1696 switch(getLexer().getKind()) {
1697 case AsmToken::Integer: {
1699 if (parseAbsoluteExpr(IntVal, AbsMod))
1700 return MatchOperand_ParseFail;
1703 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
1704 return MatchOperand_Success;
1706 case AsmToken::Real: {
1708 if (parseAbsoluteExpr(IntVal, AbsMod))
1709 return MatchOperand_ParseFail;
1711 APFloat F(BitsToDouble(IntVal));
1715 AMDGPUOperand::CreateImm(this, F.bitcastToAPInt().getZExtValue(), S,
1716 AMDGPUOperand::ImmTyNone, true));
1717 return MatchOperand_Success;
1720 return Minus ? MatchOperand_ParseFail : MatchOperand_NoMatch;
1724 OperandMatchResultTy
1725 AMDGPUAsmParser::parseReg(OperandVector &Operands) {
1726 if (auto R = parseRegister()) {
1728 R->Reg.IsForcedVOP3 = isForcedVOP3();
1729 Operands.push_back(std::move(R));
1730 return MatchOperand_Success;
1732 return MatchOperand_NoMatch;
1735 OperandMatchResultTy
1736 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool AbsMod) {
1737 auto res = parseImm(Operands, AbsMod);
1738 if (res != MatchOperand_NoMatch) {
1742 return parseReg(Operands);
1745 OperandMatchResultTy
1746 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
1748 bool Negate = false, Negate2 = false, Abs = false, Abs2 = false;
1750 if (getLexer().getKind()== AsmToken::Minus) {
1751 const AsmToken NextToken = getLexer().peekTok();
1753 // Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.
1754 if (NextToken.is(AsmToken::Minus)) {
1755 Error(Parser.getTok().getLoc(), "invalid syntax, expected 'neg' modifier");
1756 return MatchOperand_ParseFail;
1759 // '-' followed by an integer literal N should be interpreted as integer
1760 // negation rather than a floating-point NEG modifier applied to N.
1761 // Beside being contr-intuitive, such use of floating-point NEG modifier
1762 // results in different meaning of integer literals used with VOP1/2/C
1763 // and VOP3, for example:
1764 // v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF
1765 // v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001
1766 // Negative fp literals should be handled likewise for unifomtity
1767 if (!NextToken.is(AsmToken::Integer) && !NextToken.is(AsmToken::Real)) {
1773 if (getLexer().getKind() == AsmToken::Identifier &&
1774 Parser.getTok().getString() == "neg") {
1776 Error(Parser.getTok().getLoc(), "expected register or immediate");
1777 return MatchOperand_ParseFail;
1781 if (getLexer().isNot(AsmToken::LParen)) {
1782 Error(Parser.getTok().getLoc(), "expected left paren after neg");
1783 return MatchOperand_ParseFail;
1788 if (getLexer().getKind() == AsmToken::Identifier &&
1789 Parser.getTok().getString() == "abs") {
1792 if (getLexer().isNot(AsmToken::LParen)) {
1793 Error(Parser.getTok().getLoc(), "expected left paren after abs");
1794 return MatchOperand_ParseFail;
1799 if (getLexer().getKind() == AsmToken::Pipe) {
1801 Error(Parser.getTok().getLoc(), "expected register or immediate");
1802 return MatchOperand_ParseFail;
1808 OperandMatchResultTy Res;
1810 Res = parseRegOrImm(Operands, Abs);
1812 Res = parseReg(Operands);
1814 if (Res != MatchOperand_Success) {
1818 AMDGPUOperand::Modifiers Mods;
1820 if (getLexer().getKind() != AsmToken::Pipe) {
1821 Error(Parser.getTok().getLoc(), "expected vertical bar");
1822 return MatchOperand_ParseFail;
1828 if (getLexer().isNot(AsmToken::RParen)) {
1829 Error(Parser.getTok().getLoc(), "expected closing parentheses");
1830 return MatchOperand_ParseFail;
1838 } else if (Negate2) {
1839 if (getLexer().isNot(AsmToken::RParen)) {
1840 Error(Parser.getTok().getLoc(), "expected closing parentheses");
1841 return MatchOperand_ParseFail;
1847 if (Mods.hasFPModifiers()) {
1848 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
1849 Op.setModifiers(Mods);
1851 return MatchOperand_Success;
1854 OperandMatchResultTy
1855 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
1859 if (getLexer().getKind() == AsmToken::Identifier &&
1860 Parser.getTok().getString() == "sext") {
1863 if (getLexer().isNot(AsmToken::LParen)) {
1864 Error(Parser.getTok().getLoc(), "expected left paren after sext");
1865 return MatchOperand_ParseFail;
1870 OperandMatchResultTy Res;
1872 Res = parseRegOrImm(Operands);
1874 Res = parseReg(Operands);
1876 if (Res != MatchOperand_Success) {
1880 AMDGPUOperand::Modifiers Mods;
1882 if (getLexer().isNot(AsmToken::RParen)) {
1883 Error(Parser.getTok().getLoc(), "expected closing parentheses");
1884 return MatchOperand_ParseFail;
1890 if (Mods.hasIntModifiers()) {
1891 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
1892 Op.setModifiers(Mods);
1895 return MatchOperand_Success;
1898 OperandMatchResultTy
1899 AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {
1900 return parseRegOrImmWithFPInputMods(Operands, false);
1903 OperandMatchResultTy
1904 AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {
1905 return parseRegOrImmWithIntInputMods(Operands, false);
1908 OperandMatchResultTy AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
1909 std::unique_ptr<AMDGPUOperand> Reg = parseRegister();
1911 Operands.push_back(std::move(Reg));
1912 return MatchOperand_Success;
1915 const AsmToken &Tok = Parser.getTok();
1916 if (Tok.getString() == "off") {
1917 Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Tok.getLoc(),
1918 AMDGPUOperand::ImmTyOff, false));
1920 return MatchOperand_Success;
1923 return MatchOperand_NoMatch;
1926 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
1927 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
1929 if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
1930 (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) ||
1931 (isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) ||
1932 (isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )
1933 return Match_InvalidOperand;
1935 if ((TSFlags & SIInstrFlags::VOP3) &&
1936 (TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
1937 getForcedEncodingSize() != 64)
1938 return Match_PreferE32;
1940 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi ||
1941 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
1942 // v_mac_f32/16 allow only dst_sel == DWORD;
1944 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);
1945 const auto &Op = Inst.getOperand(OpNum);
1946 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {
1947 return Match_InvalidOperand;
1951 return Match_Success;
1954 // What asm variants we should check
1955 ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const {
1956 if (getForcedEncodingSize() == 32) {
1957 static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};
1958 return makeArrayRef(Variants);
1961 if (isForcedVOP3()) {
1962 static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};
1963 return makeArrayRef(Variants);
1966 if (isForcedSDWA()) {
1967 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA};
1968 return makeArrayRef(Variants);
1971 if (isForcedDPP()) {
1972 static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};
1973 return makeArrayRef(Variants);
1976 static const unsigned Variants[] = {
1977 AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,
1978 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::DPP
1981 return makeArrayRef(Variants);
1984 unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {
1985 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
1986 const unsigned Num = Desc.getNumImplicitUses();
1987 for (unsigned i = 0; i < Num; ++i) {
1988 unsigned Reg = Desc.ImplicitUses[i];
1990 case AMDGPU::FLAT_SCR:
1998 return AMDGPU::NoRegister;
2001 bool AMDGPUAsmParser::isSGPR(unsigned Reg) {
2002 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
2003 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
2004 const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
2005 return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
2009 // NB: This code is correct only when used to check constant
2010 // bus limitations because GFX7 support no f16 inline constants.
2011 // Note that there are no cases when a GFX7 opcode violates
2012 // constant bus limitations due to the use of an f16 constant.
2013 bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
2014 unsigned OpIdx) const {
2015 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2017 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) {
2021 const MCOperand &MO = Inst.getOperand(OpIdx);
2023 int64_t Val = MO.getImm();
2024 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);
2026 switch (OpSize) { // expected operand size
2028 return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm());
2030 return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm());
2032 const unsigned OperandType = Desc.OpInfo[OpIdx].OperandType;
2033 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 ||
2034 OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16) {
2035 return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm());
2037 return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm());
2041 llvm_unreachable("invalid operand size");
2045 bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
2046 const MCOperand &MO = Inst.getOperand(OpIdx);
2048 return !isInlineConstant(Inst, OpIdx);
2050 return !MO.isReg() || isSGPR(mc2PseudoReg(MO.getReg()));
2053 bool AMDGPUAsmParser::validateOperandLimitations(const MCInst &Inst) {
2054 const unsigned Opcode = Inst.getOpcode();
2055 const MCInstrDesc &Desc = MII.get(Opcode);
2056 unsigned ConstantBusUseCount = 0;
2059 (SIInstrFlags::VOPC |
2060 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 |
2061 SIInstrFlags::VOP3 | SIInstrFlags::VOP3P)) {
2063 // Check special imm operands (used by madmk, etc)
2064 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) {
2065 ++ConstantBusUseCount;
2068 unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);
2069 if (SGPRUsed != AMDGPU::NoRegister) {
2070 ++ConstantBusUseCount;
2073 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
2074 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
2075 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
2077 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
2079 for (int OpIdx : OpIndices) {
2080 if (OpIdx == -1) break;
2082 const MCOperand &MO = Inst.getOperand(OpIdx);
2083 if (usesConstantBus(Inst, OpIdx)) {
2085 const unsigned Reg = mc2PseudoReg(MO.getReg());
2086 // Pairs of registers with a partial intersections like these
2088 // flat_scratch_lo, flat_scratch
2089 // flat_scratch_lo, flat_scratch_hi
2090 // are theoretically valid but they are disabled anyway.
2091 // Note that this code mimics SIInstrInfo::verifyInstruction
2092 if (Reg != SGPRUsed) {
2093 ++ConstantBusUseCount;
2096 } else { // Expression or a literal
2097 ++ConstantBusUseCount;
2103 return ConstantBusUseCount <= 1;
2106 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2107 OperandVector &Operands,
2109 uint64_t &ErrorInfo,
2110 bool MatchingInlineAsm) {
2112 unsigned Result = Match_Success;
2113 for (auto Variant : getMatchedVariants()) {
2115 auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,
2117 // We order match statuses from least to most specific. We use most specific
2118 // status as resulting
2119 // Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature < Match_PreferE32
2120 if ((R == Match_Success) ||
2121 (R == Match_PreferE32) ||
2122 (R == Match_MissingFeature && Result != Match_PreferE32) ||
2123 (R == Match_InvalidOperand && Result != Match_MissingFeature
2124 && Result != Match_PreferE32) ||
2125 (R == Match_MnemonicFail && Result != Match_InvalidOperand
2126 && Result != Match_MissingFeature
2127 && Result != Match_PreferE32)) {
2131 if (R == Match_Success)
2138 if (!validateOperandLimitations(Inst)) {
2140 "invalid operand (violates constant bus restrictions)");
2143 Out.EmitInstruction(Inst, getSTI());
2146 case Match_MissingFeature:
2147 return Error(IDLoc, "instruction not supported on this GPU");
2149 case Match_MnemonicFail:
2150 return Error(IDLoc, "unrecognized instruction mnemonic");
2152 case Match_InvalidOperand: {
2153 SMLoc ErrorLoc = IDLoc;
2154 if (ErrorInfo != ~0ULL) {
2155 if (ErrorInfo >= Operands.size()) {
2156 return Error(IDLoc, "too few operands for instruction");
2158 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
2159 if (ErrorLoc == SMLoc())
2162 return Error(ErrorLoc, "invalid operand for instruction");
2165 case Match_PreferE32:
2166 return Error(IDLoc, "internal error: instruction without _e64 suffix "
2167 "should be encoded as e32");
2169 llvm_unreachable("Implement any new match types added!");
2172 bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
2174 if (getLexer().isNot(AsmToken::Integer) && getLexer().isNot(AsmToken::Identifier)) {
2177 if (getParser().parseAbsoluteExpression(Tmp)) {
2180 Ret = static_cast<uint32_t>(Tmp);
2184 bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
2186 if (ParseAsAbsoluteExpression(Major))
2187 return TokError("invalid major version");
2189 if (getLexer().isNot(AsmToken::Comma))
2190 return TokError("minor version number required, comma expected");
2193 if (ParseAsAbsoluteExpression(Minor))
2194 return TokError("invalid minor version");
2199 bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
2203 if (ParseDirectiveMajorMinor(Major, Minor))
2206 getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);
2210 bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
2214 StringRef VendorName;
2217 // If this directive has no arguments, then use the ISA version for the
2219 if (getLexer().is(AsmToken::EndOfStatement)) {
2220 AMDGPU::IsaInfo::IsaVersion ISA =
2221 AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
2222 getTargetStreamer().EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor,
2228 if (ParseDirectiveMajorMinor(Major, Minor))
2231 if (getLexer().isNot(AsmToken::Comma))
2232 return TokError("stepping version number required, comma expected");
2235 if (ParseAsAbsoluteExpression(Stepping))
2236 return TokError("invalid stepping version");
2238 if (getLexer().isNot(AsmToken::Comma))
2239 return TokError("vendor name required, comma expected");
2242 if (getLexer().isNot(AsmToken::String))
2243 return TokError("invalid vendor name");
2245 VendorName = getLexer().getTok().getStringContents();
2248 if (getLexer().isNot(AsmToken::Comma))
2249 return TokError("arch name required, comma expected");
2252 if (getLexer().isNot(AsmToken::String))
2253 return TokError("invalid arch name");
2255 ArchName = getLexer().getTok().getStringContents();
2258 getTargetStreamer().EmitDirectiveHSACodeObjectISA(Major, Minor, Stepping,
2259 VendorName, ArchName);
2263 bool AMDGPUAsmParser::ParseDirectiveCodeObjectMetadata() {
2264 std::string YamlString;
2265 raw_string_ostream YamlStream(YamlString);
2267 getLexer().setSkipSpace(false);
2269 bool FoundEnd = false;
2270 while (!getLexer().is(AsmToken::Eof)) {
2271 while (getLexer().is(AsmToken::Space)) {
2272 YamlStream << getLexer().getTok().getString();
2276 if (getLexer().is(AsmToken::Identifier)) {
2277 StringRef ID = getLexer().getTok().getIdentifier();
2278 if (ID == AMDGPU::CodeObject::MetadataAssemblerDirectiveEnd) {
2285 YamlStream << Parser.parseStringToEndOfStatement()
2286 << getContext().getAsmInfo()->getSeparatorString();
2288 Parser.eatToEndOfStatement();
2291 getLexer().setSkipSpace(true);
2293 if (getLexer().is(AsmToken::Eof) && !FoundEnd) {
2295 "expected directive .end_amdgpu_code_object_metadata not found");
2300 if (!getTargetStreamer().EmitCodeObjectMetadata(YamlString))
2301 return Error(getParser().getTok().getLoc(), "invalid code object metadata");
2306 bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
2307 amd_kernel_code_t &Header) {
2308 SmallString<40> ErrStr;
2309 raw_svector_ostream Err(ErrStr);
2310 if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {
2311 return TokError(Err.str());
2317 bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
2318 amd_kernel_code_t Header;
2319 AMDGPU::initDefaultAMDKernelCodeT(Header, getFeatureBits());
2322 // Lex EndOfStatement. This is in a while loop, because lexing a comment
2323 // will set the current token to EndOfStatement.
2324 while(getLexer().is(AsmToken::EndOfStatement))
2327 if (getLexer().isNot(AsmToken::Identifier))
2328 return TokError("expected value identifier or .end_amd_kernel_code_t");
2330 StringRef ID = getLexer().getTok().getIdentifier();
2333 if (ID == ".end_amd_kernel_code_t")
2336 if (ParseAMDKernelCodeTValue(ID, Header))
2340 getTargetStreamer().EmitAMDKernelCodeT(Header);
2345 bool AMDGPUAsmParser::ParseSectionDirectiveHSAText() {
2346 getParser().getStreamer().SwitchSection(
2347 AMDGPU::getHSATextSection(getContext()));
2351 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
2352 if (getLexer().isNot(AsmToken::Identifier))
2353 return TokError("expected symbol name");
2355 StringRef KernelName = Parser.getTok().getString();
2357 getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
2358 ELF::STT_AMDGPU_HSA_KERNEL);
2360 KernelScope.initialize(getContext());
2364 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaModuleGlobal() {
2365 if (getLexer().isNot(AsmToken::Identifier))
2366 return TokError("expected symbol name");
2368 StringRef GlobalName = Parser.getTok().getIdentifier();
2370 getTargetStreamer().EmitAMDGPUHsaModuleScopeGlobal(GlobalName);
2375 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaProgramGlobal() {
2376 if (getLexer().isNot(AsmToken::Identifier))
2377 return TokError("expected symbol name");
2379 StringRef GlobalName = Parser.getTok().getIdentifier();
2381 getTargetStreamer().EmitAMDGPUHsaProgramScopeGlobal(GlobalName);
2386 bool AMDGPUAsmParser::ParseSectionDirectiveHSADataGlobalAgent() {
2387 getParser().getStreamer().SwitchSection(
2388 AMDGPU::getHSADataGlobalAgentSection(getContext()));
2392 bool AMDGPUAsmParser::ParseSectionDirectiveHSADataGlobalProgram() {
2393 getParser().getStreamer().SwitchSection(
2394 AMDGPU::getHSADataGlobalProgramSection(getContext()));
2398 bool AMDGPUAsmParser::ParseSectionDirectiveHSARodataReadonlyAgent() {
2399 getParser().getStreamer().SwitchSection(
2400 AMDGPU::getHSARodataReadonlyAgentSection(getContext()));
2404 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
2405 StringRef IDVal = DirectiveID.getString();
2407 if (IDVal == ".hsa_code_object_version")
2408 return ParseDirectiveHSACodeObjectVersion();
2410 if (IDVal == ".hsa_code_object_isa")
2411 return ParseDirectiveHSACodeObjectISA();
2413 if (IDVal == AMDGPU::CodeObject::MetadataAssemblerDirectiveBegin)
2414 return ParseDirectiveCodeObjectMetadata();
2416 if (IDVal == ".amd_kernel_code_t")
2417 return ParseDirectiveAMDKernelCodeT();
2419 if (IDVal == ".hsatext")
2420 return ParseSectionDirectiveHSAText();
2422 if (IDVal == ".amdgpu_hsa_kernel")
2423 return ParseDirectiveAMDGPUHsaKernel();
2425 if (IDVal == ".amdgpu_hsa_module_global")
2426 return ParseDirectiveAMDGPUHsaModuleGlobal();
2428 if (IDVal == ".amdgpu_hsa_program_global")
2429 return ParseDirectiveAMDGPUHsaProgramGlobal();
2431 if (IDVal == ".hsadata_global_agent")
2432 return ParseSectionDirectiveHSADataGlobalAgent();
2434 if (IDVal == ".hsadata_global_program")
2435 return ParseSectionDirectiveHSADataGlobalProgram();
2437 if (IDVal == ".hsarodata_readonly_agent")
2438 return ParseSectionDirectiveHSARodataReadonlyAgent();
2443 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
2444 unsigned RegNo) const {
2451 case AMDGPU::FLAT_SCR:
2452 case AMDGPU::FLAT_SCR_LO:
2453 case AMDGPU::FLAT_SCR_HI:
2460 // VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
2462 for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true);
2471 OperandMatchResultTy
2472 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
2473 // Try to parse with a custom parser
2474 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2476 // If we successfully parsed the operand or if there as an error parsing,
2479 // If we are parsing after we reach EndOfStatement then this means we
2480 // are appending default values to the Operands list. This is only done
2481 // by custom parser, so we shouldn't continue on to the generic parsing.
2482 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
2483 getLexer().is(AsmToken::EndOfStatement))
2486 ResTy = parseRegOrImm(Operands);
2488 if (ResTy == MatchOperand_Success)
2491 if (getLexer().getKind() == AsmToken::Identifier) {
2492 // If this identifier is a symbol, we want to create an expression for it.
2493 // It is a little difficult to distinguish between a symbol name, and
2494 // an instruction flag like 'gds'. In order to do this, we parse
2495 // all tokens as expressions and then treate the symbol name as the token
2496 // string when we want to interpret the operand as a token.
2497 const auto &Tok = Parser.getTok();
2498 SMLoc S = Tok.getLoc();
2499 const MCExpr *Expr = nullptr;
2500 if (!Parser.parseExpression(Expr)) {
2501 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
2502 return MatchOperand_Success;
2505 Operands.push_back(AMDGPUOperand::CreateToken(this, Tok.getString(), Tok.getLoc()));
2507 return MatchOperand_Success;
2509 return MatchOperand_NoMatch;
2512 StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
2513 // Clear any forced encodings from the previous instruction.
2514 setForcedEncodingSize(0);
2515 setForcedDPP(false);
2516 setForcedSDWA(false);
2518 if (Name.endswith("_e64")) {
2519 setForcedEncodingSize(64);
2520 return Name.substr(0, Name.size() - 4);
2521 } else if (Name.endswith("_e32")) {
2522 setForcedEncodingSize(32);
2523 return Name.substr(0, Name.size() - 4);
2524 } else if (Name.endswith("_dpp")) {
2526 return Name.substr(0, Name.size() - 4);
2527 } else if (Name.endswith("_sdwa")) {
2528 setForcedSDWA(true);
2529 return Name.substr(0, Name.size() - 5);
2534 bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
2536 SMLoc NameLoc, OperandVector &Operands) {
2537 // Add the instruction mnemonic
2538 Name = parseMnemonicSuffix(Name);
2539 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));
2541 while (!getLexer().is(AsmToken::EndOfStatement)) {
2542 OperandMatchResultTy Res = parseOperand(Operands, Name);
2544 // Eat the comma or space if there is one.
2545 if (getLexer().is(AsmToken::Comma))
2549 case MatchOperand_Success: break;
2550 case MatchOperand_ParseFail:
2551 Error(getLexer().getLoc(), "failed parsing operand.");
2552 while (!getLexer().is(AsmToken::EndOfStatement)) {
2556 case MatchOperand_NoMatch:
2557 Error(getLexer().getLoc(), "not a valid operand.");
2558 while (!getLexer().is(AsmToken::EndOfStatement)) {
2568 //===----------------------------------------------------------------------===//
2569 // Utility functions
2570 //===----------------------------------------------------------------------===//
2572 OperandMatchResultTy
2573 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int) {
2574 switch(getLexer().getKind()) {
2575 default: return MatchOperand_NoMatch;
2576 case AsmToken::Identifier: {
2577 StringRef Name = Parser.getTok().getString();
2578 if (!Name.equals(Prefix)) {
2579 return MatchOperand_NoMatch;
2583 if (getLexer().isNot(AsmToken::Colon))
2584 return MatchOperand_ParseFail;
2587 if (getLexer().isNot(AsmToken::Integer))
2588 return MatchOperand_ParseFail;
2590 if (getParser().parseAbsoluteExpression(Int))
2591 return MatchOperand_ParseFail;
2595 return MatchOperand_Success;
2598 OperandMatchResultTy
2599 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
2600 AMDGPUOperand::ImmTy ImmTy,
2601 bool (*ConvertResult)(int64_t&)) {
2602 SMLoc S = Parser.getTok().getLoc();
2605 OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value);
2606 if (Res != MatchOperand_Success)
2609 if (ConvertResult && !ConvertResult(Value)) {
2610 return MatchOperand_ParseFail;
2613 Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));
2614 return MatchOperand_Success;
2617 OperandMatchResultTy AMDGPUAsmParser::parseOperandArrayWithPrefix(
2619 OperandVector &Operands,
2620 AMDGPUOperand::ImmTy ImmTy,
2621 bool (*ConvertResult)(int64_t&)) {
2622 StringRef Name = Parser.getTok().getString();
2623 if (!Name.equals(Prefix))
2624 return MatchOperand_NoMatch;
2627 if (getLexer().isNot(AsmToken::Colon))
2628 return MatchOperand_ParseFail;
2631 if (getLexer().isNot(AsmToken::LBrac))
2632 return MatchOperand_ParseFail;
2636 SMLoc S = Parser.getTok().getLoc();
2638 // FIXME: How to verify the number of elements matches the number of src
2640 for (int I = 0; I < 3; ++I) {
2642 if (getLexer().is(AsmToken::RBrac))
2645 if (getLexer().isNot(AsmToken::Comma))
2646 return MatchOperand_ParseFail;
2650 if (getLexer().isNot(AsmToken::Integer))
2651 return MatchOperand_ParseFail;
2654 if (getParser().parseAbsoluteExpression(Op))
2655 return MatchOperand_ParseFail;
2657 if (Op != 0 && Op != 1)
2658 return MatchOperand_ParseFail;
2663 Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));
2664 return MatchOperand_Success;
2667 OperandMatchResultTy
2668 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
2669 AMDGPUOperand::ImmTy ImmTy) {
2671 SMLoc S = Parser.getTok().getLoc();
2673 // We are at the end of the statement, and this is a default argument, so
2674 // use a default value.
2675 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2676 switch(getLexer().getKind()) {
2677 case AsmToken::Identifier: {
2678 StringRef Tok = Parser.getTok().getString();
2682 } else if (Tok.startswith("no") && Tok.endswith(Name)) {
2686 return MatchOperand_NoMatch;
2691 return MatchOperand_NoMatch;
2695 Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));
2696 return MatchOperand_Success;
2699 static void addOptionalImmOperand(
2700 MCInst& Inst, const OperandVector& Operands,
2701 AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,
2702 AMDGPUOperand::ImmTy ImmT,
2703 int64_t Default = 0) {
2704 auto i = OptionalIdx.find(ImmT);
2705 if (i != OptionalIdx.end()) {
2706 unsigned Idx = i->second;
2707 ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);
2709 Inst.addOperand(MCOperand::createImm(Default));
2713 OperandMatchResultTy
2714 AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) {
2715 if (getLexer().isNot(AsmToken::Identifier)) {
2716 return MatchOperand_NoMatch;
2718 StringRef Tok = Parser.getTok().getString();
2719 if (Tok != Prefix) {
2720 return MatchOperand_NoMatch;
2724 if (getLexer().isNot(AsmToken::Colon)) {
2725 return MatchOperand_ParseFail;
2729 if (getLexer().isNot(AsmToken::Identifier)) {
2730 return MatchOperand_ParseFail;
2733 Value = Parser.getTok().getString();
2734 return MatchOperand_Success;
2737 //===----------------------------------------------------------------------===//
2739 //===----------------------------------------------------------------------===//
2741 void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
2742 const OperandVector &Operands) {
2743 OptionalImmIndexMap OptionalIdx;
2745 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
2746 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
2748 // Add the register arguments
2750 Op.addRegOperands(Inst, 1);
2754 // Handle optional arguments
2755 OptionalIdx[Op.getImmTy()] = i;
2758 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset0);
2759 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset1);
2760 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
2762 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
2765 void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
2766 bool IsGdsHardcoded) {
2767 OptionalImmIndexMap OptionalIdx;
2769 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
2770 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
2772 // Add the register arguments
2774 Op.addRegOperands(Inst, 1);
2778 if (Op.isToken() && Op.getToken() == "gds") {
2779 IsGdsHardcoded = true;
2783 // Handle optional arguments
2784 OptionalIdx[Op.getImmTy()] = i;
2787 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
2788 if (!IsGdsHardcoded) {
2789 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
2791 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
2794 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
2795 OptionalImmIndexMap OptionalIdx;
2797 unsigned EnMask = 0;
2800 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
2801 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
2803 // Add the register arguments
2805 EnMask |= (1 << SrcIdx);
2806 Op.addRegOperands(Inst, 1);
2813 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
2817 if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {
2818 Op.addImmOperands(Inst, 1);
2822 if (Op.isToken() && Op.getToken() == "done")
2825 // Handle optional arguments
2826 OptionalIdx[Op.getImmTy()] = i;
2829 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
2830 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
2832 Inst.addOperand(MCOperand::createImm(EnMask));
2835 //===----------------------------------------------------------------------===//
2837 //===----------------------------------------------------------------------===//
2839 bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
2840 StringRef CntName = Parser.getTok().getString();
2844 if (getLexer().isNot(AsmToken::LParen))
2848 if (getLexer().isNot(AsmToken::Integer))
2851 if (getParser().parseAbsoluteExpression(CntVal))
2854 if (getLexer().isNot(AsmToken::RParen))
2858 if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
2861 AMDGPU::IsaInfo::IsaVersion ISA =
2862 AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
2863 if (CntName == "vmcnt")
2864 IntVal = encodeVmcnt(ISA, IntVal, CntVal);
2865 else if (CntName == "expcnt")
2866 IntVal = encodeExpcnt(ISA, IntVal, CntVal);
2867 else if (CntName == "lgkmcnt")
2868 IntVal = encodeLgkmcnt(ISA, IntVal, CntVal);
2875 OperandMatchResultTy
2876 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
2877 AMDGPU::IsaInfo::IsaVersion ISA =
2878 AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
2879 int64_t Waitcnt = getWaitcntBitMask(ISA);
2880 SMLoc S = Parser.getTok().getLoc();
2882 switch(getLexer().getKind()) {
2883 default: return MatchOperand_ParseFail;
2884 case AsmToken::Integer:
2885 // The operand can be an integer value.
2886 if (getParser().parseAbsoluteExpression(Waitcnt))
2887 return MatchOperand_ParseFail;
2890 case AsmToken::Identifier:
2892 if (parseCnt(Waitcnt))
2893 return MatchOperand_ParseFail;
2894 } while(getLexer().isNot(AsmToken::EndOfStatement));
2897 Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));
2898 return MatchOperand_Success;
2901 bool AMDGPUAsmParser::parseHwregConstruct(OperandInfoTy &HwReg, int64_t &Offset,
2903 using namespace llvm::AMDGPU::Hwreg;
2905 if (Parser.getTok().getString() != "hwreg")
2909 if (getLexer().isNot(AsmToken::LParen))
2913 if (getLexer().is(AsmToken::Identifier)) {
2914 HwReg.IsSymbolic = true;
2915 HwReg.Id = ID_UNKNOWN_;
2916 const StringRef tok = Parser.getTok().getString();
2917 for (int i = ID_SYMBOLIC_FIRST_; i < ID_SYMBOLIC_LAST_; ++i) {
2918 if (tok == IdSymbolic[i]) {
2925 HwReg.IsSymbolic = false;
2926 if (getLexer().isNot(AsmToken::Integer))
2928 if (getParser().parseAbsoluteExpression(HwReg.Id))
2932 if (getLexer().is(AsmToken::RParen)) {
2938 if (getLexer().isNot(AsmToken::Comma))
2942 if (getLexer().isNot(AsmToken::Integer))
2944 if (getParser().parseAbsoluteExpression(Offset))
2947 if (getLexer().isNot(AsmToken::Comma))
2951 if (getLexer().isNot(AsmToken::Integer))
2953 if (getParser().parseAbsoluteExpression(Width))
2956 if (getLexer().isNot(AsmToken::RParen))
2963 OperandMatchResultTy AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
2964 using namespace llvm::AMDGPU::Hwreg;
2966 int64_t Imm16Val = 0;
2967 SMLoc S = Parser.getTok().getLoc();
2969 switch(getLexer().getKind()) {
2970 default: return MatchOperand_NoMatch;
2971 case AsmToken::Integer:
2972 // The operand can be an integer value.
2973 if (getParser().parseAbsoluteExpression(Imm16Val))
2974 return MatchOperand_NoMatch;
2975 if (Imm16Val < 0 || !isUInt<16>(Imm16Val)) {
2976 Error(S, "invalid immediate: only 16-bit values are legal");
2977 // Do not return error code, but create an imm operand anyway and proceed
2978 // to the next operand, if any. That avoids unneccessary error messages.
2982 case AsmToken::Identifier: {
2983 OperandInfoTy HwReg(ID_UNKNOWN_);
2984 int64_t Offset = OFFSET_DEFAULT_;
2985 int64_t Width = WIDTH_M1_DEFAULT_ + 1;
2986 if (parseHwregConstruct(HwReg, Offset, Width))
2987 return MatchOperand_ParseFail;
2988 if (HwReg.Id < 0 || !isUInt<ID_WIDTH_>(HwReg.Id)) {
2989 if (HwReg.IsSymbolic)
2990 Error(S, "invalid symbolic name of hardware register");
2992 Error(S, "invalid code of hardware register: only 6-bit values are legal");
2994 if (Offset < 0 || !isUInt<OFFSET_WIDTH_>(Offset))
2995 Error(S, "invalid bit offset: only 5-bit values are legal");
2996 if ((Width-1) < 0 || !isUInt<WIDTH_M1_WIDTH_>(Width-1))
2997 Error(S, "invalid bitfield width: only values from 1 to 32 are legal");
2998 Imm16Val = (HwReg.Id << ID_SHIFT_) | (Offset << OFFSET_SHIFT_) | ((Width-1) << WIDTH_M1_SHIFT_);
3002 Operands.push_back(AMDGPUOperand::CreateImm(this, Imm16Val, S, AMDGPUOperand::ImmTyHwreg));
3003 return MatchOperand_Success;
3006 bool AMDGPUOperand::isSWaitCnt() const {
3010 bool AMDGPUOperand::isHwreg() const {
3011 return isImmTy(ImmTyHwreg);
3014 bool AMDGPUAsmParser::parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId) {
3015 using namespace llvm::AMDGPU::SendMsg;
3017 if (Parser.getTok().getString() != "sendmsg")
3021 if (getLexer().isNot(AsmToken::LParen))
3025 if (getLexer().is(AsmToken::Identifier)) {
3026 Msg.IsSymbolic = true;
3027 Msg.Id = ID_UNKNOWN_;
3028 const std::string tok = Parser.getTok().getString();
3029 for (int i = ID_GAPS_FIRST_; i < ID_GAPS_LAST_; ++i) {
3031 default: continue; // Omit gaps.
3032 case ID_INTERRUPT: case ID_GS: case ID_GS_DONE: case ID_SYSMSG: break;
3034 if (tok == IdSymbolic[i]) {
3041 Msg.IsSymbolic = false;
3042 if (getLexer().isNot(AsmToken::Integer))
3044 if (getParser().parseAbsoluteExpression(Msg.Id))
3046 if (getLexer().is(AsmToken::Integer))
3047 if (getParser().parseAbsoluteExpression(Msg.Id))
3048 Msg.Id = ID_UNKNOWN_;
3050 if (Msg.Id == ID_UNKNOWN_) // Don't know how to parse the rest.
3053 if (!(Msg.Id == ID_GS || Msg.Id == ID_GS_DONE || Msg.Id == ID_SYSMSG)) {
3054 if (getLexer().isNot(AsmToken::RParen))
3060 if (getLexer().isNot(AsmToken::Comma))
3064 assert(Msg.Id == ID_GS || Msg.Id == ID_GS_DONE || Msg.Id == ID_SYSMSG);
3065 Operation.Id = ID_UNKNOWN_;
3066 if (getLexer().is(AsmToken::Identifier)) {
3067 Operation.IsSymbolic = true;
3068 const char* const *S = (Msg.Id == ID_SYSMSG) ? OpSysSymbolic : OpGsSymbolic;
3069 const int F = (Msg.Id == ID_SYSMSG) ? OP_SYS_FIRST_ : OP_GS_FIRST_;
3070 const int L = (Msg.Id == ID_SYSMSG) ? OP_SYS_LAST_ : OP_GS_LAST_;
3071 const StringRef Tok = Parser.getTok().getString();
3072 for (int i = F; i < L; ++i) {
3080 Operation.IsSymbolic = false;
3081 if (getLexer().isNot(AsmToken::Integer))
3083 if (getParser().parseAbsoluteExpression(Operation.Id))
3087 if ((Msg.Id == ID_GS || Msg.Id == ID_GS_DONE) && Operation.Id != OP_GS_NOP) {
3088 // Stream id is optional.
3089 if (getLexer().is(AsmToken::RParen)) {
3094 if (getLexer().isNot(AsmToken::Comma))
3098 if (getLexer().isNot(AsmToken::Integer))
3100 if (getParser().parseAbsoluteExpression(StreamId))
3104 if (getLexer().isNot(AsmToken::RParen))
3110 OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {
3111 if (getLexer().getKind() != AsmToken::Identifier)
3112 return MatchOperand_NoMatch;
3114 StringRef Str = Parser.getTok().getString();
3115 int Slot = StringSwitch<int>(Str)
3121 SMLoc S = Parser.getTok().getLoc();
3123 return MatchOperand_ParseFail;
3126 Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,
3127 AMDGPUOperand::ImmTyInterpSlot));
3128 return MatchOperand_Success;
3131 OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
3132 if (getLexer().getKind() != AsmToken::Identifier)
3133 return MatchOperand_NoMatch;
3135 StringRef Str = Parser.getTok().getString();
3136 if (!Str.startswith("attr"))
3137 return MatchOperand_NoMatch;
3139 StringRef Chan = Str.take_back(2);
3140 int AttrChan = StringSwitch<int>(Chan)
3147 return MatchOperand_ParseFail;
3149 Str = Str.drop_back(2).drop_front(4);
3152 if (Str.getAsInteger(10, Attr))
3153 return MatchOperand_ParseFail;
3155 SMLoc S = Parser.getTok().getLoc();
3158 Error(S, "out of bounds attr");
3159 return MatchOperand_Success;
3162 SMLoc SChan = SMLoc::getFromPointer(Chan.data());
3164 Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,
3165 AMDGPUOperand::ImmTyInterpAttr));
3166 Operands.push_back(AMDGPUOperand::CreateImm(this, AttrChan, SChan,
3167 AMDGPUOperand::ImmTyAttrChan));
3168 return MatchOperand_Success;
3171 void AMDGPUAsmParser::errorExpTgt() {
3172 Error(Parser.getTok().getLoc(), "invalid exp target");
3175 OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
3177 if (Str == "null") {
3179 return MatchOperand_Success;
3182 if (Str.startswith("mrt")) {
3183 Str = Str.drop_front(3);
3184 if (Str == "z") { // == mrtz
3186 return MatchOperand_Success;
3189 if (Str.getAsInteger(10, Val))
3190 return MatchOperand_ParseFail;
3195 return MatchOperand_Success;
3198 if (Str.startswith("pos")) {
3199 Str = Str.drop_front(3);
3200 if (Str.getAsInteger(10, Val))
3201 return MatchOperand_ParseFail;
3207 return MatchOperand_Success;
3210 if (Str.startswith("param")) {
3211 Str = Str.drop_front(5);
3212 if (Str.getAsInteger(10, Val))
3213 return MatchOperand_ParseFail;
3219 return MatchOperand_Success;
3222 if (Str.startswith("invalid_target_")) {
3223 Str = Str.drop_front(15);
3224 if (Str.getAsInteger(10, Val))
3225 return MatchOperand_ParseFail;
3228 return MatchOperand_Success;
3231 return MatchOperand_NoMatch;
3234 OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
3236 StringRef Str = Parser.getTok().getString();
3238 auto Res = parseExpTgtImpl(Str, Val);
3239 if (Res != MatchOperand_Success)
3242 SMLoc S = Parser.getTok().getLoc();
3245 Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S,
3246 AMDGPUOperand::ImmTyExpTgt));
3247 return MatchOperand_Success;
3250 OperandMatchResultTy
3251 AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
3252 using namespace llvm::AMDGPU::SendMsg;
3254 int64_t Imm16Val = 0;
3255 SMLoc S = Parser.getTok().getLoc();
3257 switch(getLexer().getKind()) {
3259 return MatchOperand_NoMatch;
3260 case AsmToken::Integer:
3261 // The operand can be an integer value.
3262 if (getParser().parseAbsoluteExpression(Imm16Val))
3263 return MatchOperand_NoMatch;
3264 if (Imm16Val < 0 || !isUInt<16>(Imm16Val)) {
3265 Error(S, "invalid immediate: only 16-bit values are legal");
3266 // Do not return error code, but create an imm operand anyway and proceed
3267 // to the next operand, if any. That avoids unneccessary error messages.
3270 case AsmToken::Identifier: {
3271 OperandInfoTy Msg(ID_UNKNOWN_);
3272 OperandInfoTy Operation(OP_UNKNOWN_);
3273 int64_t StreamId = STREAM_ID_DEFAULT_;
3274 if (parseSendMsgConstruct(Msg, Operation, StreamId))
3275 return MatchOperand_ParseFail;
3277 // Validate and encode message ID.
3278 if (! ((ID_INTERRUPT <= Msg.Id && Msg.Id <= ID_GS_DONE)
3279 || Msg.Id == ID_SYSMSG)) {
3281 Error(S, "invalid/unsupported symbolic name of message");
3283 Error(S, "invalid/unsupported code of message");
3286 Imm16Val = (Msg.Id << ID_SHIFT_);
3287 // Validate and encode operation ID.
3288 if (Msg.Id == ID_GS || Msg.Id == ID_GS_DONE) {
3289 if (! (OP_GS_FIRST_ <= Operation.Id && Operation.Id < OP_GS_LAST_)) {
3290 if (Operation.IsSymbolic)
3291 Error(S, "invalid symbolic name of GS_OP");
3293 Error(S, "invalid code of GS_OP: only 2-bit values are legal");
3296 if (Operation.Id == OP_GS_NOP
3297 && Msg.Id != ID_GS_DONE) {
3298 Error(S, "invalid GS_OP: NOP is for GS_DONE only");
3301 Imm16Val |= (Operation.Id << OP_SHIFT_);
3303 if (Msg.Id == ID_SYSMSG) {
3304 if (! (OP_SYS_FIRST_ <= Operation.Id && Operation.Id < OP_SYS_LAST_)) {
3305 if (Operation.IsSymbolic)
3306 Error(S, "invalid/unsupported symbolic name of SYSMSG_OP");
3308 Error(S, "invalid/unsupported code of SYSMSG_OP");
3311 Imm16Val |= (Operation.Id << OP_SHIFT_);
3313 // Validate and encode stream ID.
3314 if ((Msg.Id == ID_GS || Msg.Id == ID_GS_DONE) && Operation.Id != OP_GS_NOP) {
3315 if (! (STREAM_ID_FIRST_ <= StreamId && StreamId < STREAM_ID_LAST_)) {
3316 Error(S, "invalid stream id: only 2-bit values are legal");
3319 Imm16Val |= (StreamId << STREAM_ID_SHIFT_);
3325 Operands.push_back(AMDGPUOperand::CreateImm(this, Imm16Val, S, AMDGPUOperand::ImmTySendMsg));
3326 return MatchOperand_Success;
3329 bool AMDGPUOperand::isSendMsg() const {
3330 return isImmTy(ImmTySendMsg);
3333 //===----------------------------------------------------------------------===//
3334 // sopp branch targets
3335 //===----------------------------------------------------------------------===//
3337 OperandMatchResultTy
3338 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
3339 SMLoc S = Parser.getTok().getLoc();
3341 switch (getLexer().getKind()) {
3342 default: return MatchOperand_ParseFail;
3343 case AsmToken::Integer: {
3345 if (getParser().parseAbsoluteExpression(Imm))
3346 return MatchOperand_ParseFail;
3347 Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S));
3348 return MatchOperand_Success;
3351 case AsmToken::Identifier:
3352 Operands.push_back(AMDGPUOperand::CreateExpr(this,
3353 MCSymbolRefExpr::create(getContext().getOrCreateSymbol(
3354 Parser.getTok().getString()), getContext()), S));
3356 return MatchOperand_Success;
3360 //===----------------------------------------------------------------------===//
3362 //===----------------------------------------------------------------------===//
3364 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultGLC() const {
3365 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyGLC);
3368 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSLC() const {
3369 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTySLC);
3372 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultTFE() const {
3373 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyTFE);
3376 void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
3377 const OperandVector &Operands,
3378 bool IsAtomic, bool IsAtomicReturn) {
3379 OptionalImmIndexMap OptionalIdx;
3380 assert(IsAtomicReturn ? IsAtomic : true);
3382 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
3383 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
3385 // Add the register arguments
3387 Op.addRegOperands(Inst, 1);
3391 // Handle the case where soffset is an immediate
3392 if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
3393 Op.addImmOperands(Inst, 1);
3397 // Handle tokens like 'offen' which are sometimes hard-coded into the
3398 // asm string. There are no MCInst operands for these.
3404 // Handle optional arguments
3405 OptionalIdx[Op.getImmTy()] = i;
3408 // Copy $vdata_in operand and insert as $vdata for MUBUF_Atomic RTN insns.
3409 if (IsAtomicReturn) {
3410 MCInst::iterator I = Inst.begin(); // $vdata_in is always at the beginning.
3414 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
3415 if (!IsAtomic) { // glc is hard-coded.
3416 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
3418 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
3419 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
3422 //===----------------------------------------------------------------------===//
3424 //===----------------------------------------------------------------------===//
3426 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
3428 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3429 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
3430 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
3433 OptionalImmIndexMap OptionalIdx;
3435 for (unsigned E = Operands.size(); I != E; ++I) {
3436 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
3438 // Add the register arguments
3439 if (Op.isRegOrImm()) {
3440 Op.addRegOrImmOperands(Inst, 1);
3442 } else if (Op.isImmModifier()) {
3443 OptionalIdx[Op.getImmTy()] = I;
3445 llvm_unreachable("unexpected operand type");
3449 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
3450 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
3451 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
3452 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
3453 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
3454 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
3455 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
3456 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
3459 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
3461 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3462 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
3463 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
3466 // Add src, same as dst
3467 ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1);
3469 OptionalImmIndexMap OptionalIdx;
3471 for (unsigned E = Operands.size(); I != E; ++I) {
3472 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
3474 // Add the register arguments
3475 if (Op.isRegOrImm()) {
3476 Op.addRegOrImmOperands(Inst, 1);
3478 } else if (Op.isImmModifier()) {
3479 OptionalIdx[Op.getImmTy()] = I;
3481 llvm_unreachable("unexpected operand type");
3485 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
3486 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
3487 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
3488 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
3489 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
3490 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
3491 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
3492 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
3495 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDMask() const {
3496 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDMask);
3499 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultUNorm() const {
3500 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyUNorm);
3503 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDA() const {
3504 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDA);
3507 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultR128() const {
3508 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyR128);
3511 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultLWE() const {
3512 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyLWE);
3515 //===----------------------------------------------------------------------===//
3517 //===----------------------------------------------------------------------===//
3519 bool AMDGPUOperand::isSMRDOffset8() const {
3520 return isImm() && isUInt<8>(getImm());
3523 bool AMDGPUOperand::isSMRDOffset20() const {
3524 return isImm() && isUInt<20>(getImm());
3527 bool AMDGPUOperand::isSMRDLiteralOffset() const {
3528 // 32-bit literals are only supported on CI and we only want to use them
3529 // when the offset is > 8-bits.
3530 return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
3533 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset8() const {
3534 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
3537 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset20() const {
3538 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
3541 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDLiteralOffset() const {
3542 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
3545 //===----------------------------------------------------------------------===//
3547 //===----------------------------------------------------------------------===//
3549 static bool ConvertOmodMul(int64_t &Mul) {
3550 if (Mul != 1 && Mul != 2 && Mul != 4)
3557 static bool ConvertOmodDiv(int64_t &Div) {
3571 static bool ConvertBoundCtrl(int64_t &BoundCtrl) {
3572 if (BoundCtrl == 0) {
3577 if (BoundCtrl == -1) {
3585 // Note: the order in this table matches the order of operands in AsmString.
3586 static const OptionalOperand AMDGPUOptionalOperandTable[] = {
3587 {"offen", AMDGPUOperand::ImmTyOffen, true, nullptr},
3588 {"idxen", AMDGPUOperand::ImmTyIdxen, true, nullptr},
3589 {"addr64", AMDGPUOperand::ImmTyAddr64, true, nullptr},
3590 {"offset0", AMDGPUOperand::ImmTyOffset0, false, nullptr},
3591 {"offset1", AMDGPUOperand::ImmTyOffset1, false, nullptr},
3592 {"gds", AMDGPUOperand::ImmTyGDS, true, nullptr},
3593 {"offset", AMDGPUOperand::ImmTyOffset, false, nullptr},
3594 {"glc", AMDGPUOperand::ImmTyGLC, true, nullptr},
3595 {"slc", AMDGPUOperand::ImmTySLC, true, nullptr},
3596 {"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr},
3597 {"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr},
3598 {"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
3599 {"unorm", AMDGPUOperand::ImmTyUNorm, true, nullptr},
3600 {"da", AMDGPUOperand::ImmTyDA, true, nullptr},
3601 {"r128", AMDGPUOperand::ImmTyR128, true, nullptr},
3602 {"lwe", AMDGPUOperand::ImmTyLWE, true, nullptr},
3603 {"dmask", AMDGPUOperand::ImmTyDMask, false, nullptr},
3604 {"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, nullptr},
3605 {"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, nullptr},
3606 {"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, ConvertBoundCtrl},
3607 {"dst_sel", AMDGPUOperand::ImmTySdwaDstSel, false, nullptr},
3608 {"src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel, false, nullptr},
3609 {"src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel, false, nullptr},
3610 {"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr},
3611 {"vm", AMDGPUOperand::ImmTyExpVM, true, nullptr},
3612 {"op_sel", AMDGPUOperand::ImmTyOpSel, false, nullptr},
3613 {"op_sel_hi", AMDGPUOperand::ImmTyOpSelHi, false, nullptr},
3614 {"neg_lo", AMDGPUOperand::ImmTyNegLo, false, nullptr},
3615 {"neg_hi", AMDGPUOperand::ImmTyNegHi, false, nullptr}
3618 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
3619 OperandMatchResultTy res;
3620 for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) {
3621 // try to parse any optional operand here
3623 res = parseNamedBit(Op.Name, Operands, Op.Type);
3624 } else if (Op.Type == AMDGPUOperand::ImmTyOModSI) {
3625 res = parseOModOperand(Operands);
3626 } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstSel ||
3627 Op.Type == AMDGPUOperand::ImmTySdwaSrc0Sel ||
3628 Op.Type == AMDGPUOperand::ImmTySdwaSrc1Sel) {
3629 res = parseSDWASel(Operands, Op.Name, Op.Type);
3630 } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstUnused) {
3631 res = parseSDWADstUnused(Operands);
3632 } else if (Op.Type == AMDGPUOperand::ImmTyOpSel ||
3633 Op.Type == AMDGPUOperand::ImmTyOpSelHi ||
3634 Op.Type == AMDGPUOperand::ImmTyNegLo ||
3635 Op.Type == AMDGPUOperand::ImmTyNegHi) {
3636 res = parseOperandArrayWithPrefix(Op.Name, Operands, Op.Type,
3639 res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);
3641 if (res != MatchOperand_NoMatch) {
3645 return MatchOperand_NoMatch;
3648 OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) {
3649 StringRef Name = Parser.getTok().getString();
3650 if (Name == "mul") {
3651 return parseIntWithPrefix("mul", Operands,
3652 AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);
3655 if (Name == "div") {
3656 return parseIntWithPrefix("div", Operands,
3657 AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);
3660 return MatchOperand_NoMatch;
3663 void AMDGPUAsmParser::cvtId(MCInst &Inst, const OperandVector &Operands) {
3665 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3666 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
3667 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
3669 for (unsigned E = Operands.size(); I != E; ++I)
3670 ((AMDGPUOperand &)*Operands[I]).addRegOrImmOperands(Inst, 1);
3673 void AMDGPUAsmParser::cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands) {
3674 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
3675 if (TSFlags & SIInstrFlags::VOP3) {
3676 cvtVOP3(Inst, Operands);
3678 cvtId(Inst, Operands);
3682 static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
3683 // 1. This operand is input modifiers
3684 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
3685 // 2. This is not last operand
3686 && Desc.NumOperands > (OpNum + 1)
3687 // 3. Next operand is register class
3688 && Desc.OpInfo[OpNum + 1].RegClass != -1
3689 // 4. Next register is not tied to any other operand
3690 && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
3693 void AMDGPUAsmParser::cvtVOP3Impl(MCInst &Inst, const OperandVector &Operands,
3694 OptionalImmIndexMap &OptionalIdx) {
3696 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3697 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
3698 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
3701 for (unsigned E = Operands.size(); I != E; ++I) {
3702 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
3703 if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
3704 Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
3705 } else if (Op.isImmModifier()) {
3706 OptionalIdx[Op.getImmTy()] = I;
3707 } else if (Op.isRegOrImm()) {
3708 Op.addRegOrImmOperands(Inst, 1);
3710 llvm_unreachable("unhandled operand type");
3715 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
3716 OptionalImmIndexMap OptionalIdx;
3718 cvtVOP3Impl(Inst, Operands, OptionalIdx);
3720 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
3721 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
3723 // special case v_mac_{f16, f32}:
3724 // it has src2 register operand that is tied to dst operand
3725 // we don't allow modifiers for this operand in assembler so src2_modifiers
3727 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
3728 Inst.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
3729 Inst.getOpcode() == AMDGPU::V_MAC_F16_e64_vi) {
3730 auto it = Inst.begin();
3733 AMDGPU::getNamedOperandIdx(Inst.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ?
3734 AMDGPU::V_MAC_F16_e64 :
3735 AMDGPU::V_MAC_F32_e64,
3736 AMDGPU::OpName::src2_modifiers));
3737 it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2
3739 Inst.insert(it, Inst.getOperand(0)); // src2 = dst
3743 void AMDGPUAsmParser::cvtVOP3OMod(MCInst &Inst, const OperandVector &Operands) {
3744 OptionalImmIndexMap OptionalIdx;
3747 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3748 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
3749 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
3752 for (unsigned E = Operands.size(); I != E; ++I) {
3753 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
3755 OptionalIdx[Op.getImmTy()] = I;
3757 Op.addRegOrImmOperands(Inst, 1);
3761 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
3762 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
3765 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
3766 OptionalImmIndexMap OptIdx;
3768 cvtVOP3Impl(Inst, Operands, OptIdx);
3770 // FIXME: This is messy. Parse the modifiers as if it was a normal VOP3
3771 // instruction, and then figure out where to actually put the modifiers
3772 int Opc = Inst.getOpcode();
3774 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
3775 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyClampSI);
3778 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
3779 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, -1);
3781 int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);
3782 if (NegLoIdx != -1) {
3783 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);
3784 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
3787 const int Ops[] = { AMDGPU::OpName::src0,
3788 AMDGPU::OpName::src1,
3789 AMDGPU::OpName::src2 };
3790 const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
3791 AMDGPU::OpName::src1_modifiers,
3792 AMDGPU::OpName::src2_modifiers };
3794 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
3795 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
3797 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
3798 unsigned OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();
3802 if (NegLoIdx != -1) {
3803 int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);
3804 NegLo = Inst.getOperand(NegLoIdx).getImm();
3805 NegHi = Inst.getOperand(NegHiIdx).getImm();
3808 for (int J = 0; J < 3; ++J) {
3809 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);
3813 uint32_t ModVal = 0;
3815 if ((OpSel & (1 << J)) != 0)
3816 ModVal |= SISrcMods::OP_SEL_0;
3818 if ((OpSelHi & (1 << J)) != 0)
3819 ModVal |= SISrcMods::OP_SEL_1;
3821 if ((NegLo & (1 << J)) != 0)
3822 ModVal |= SISrcMods::NEG;
3824 if ((NegHi & (1 << J)) != 0)
3825 ModVal |= SISrcMods::NEG_HI;
3827 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
3829 Inst.getOperand(ModIdx).setImm(ModVal);
3833 //===----------------------------------------------------------------------===//
3835 //===----------------------------------------------------------------------===//
3837 bool AMDGPUOperand::isDPPCtrl() const {
3838 bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());
3840 int64_t Imm = getImm();
3841 return ((Imm >= 0x000) && (Imm <= 0x0ff)) ||
3842 ((Imm >= 0x101) && (Imm <= 0x10f)) ||
3843 ((Imm >= 0x111) && (Imm <= 0x11f)) ||
3844 ((Imm >= 0x121) && (Imm <= 0x12f)) ||
3857 bool AMDGPUOperand::isGPRIdxMode() const {
3858 return isImm() && isUInt<4>(getImm());
3861 OperandMatchResultTy
3862 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
3863 SMLoc S = Parser.getTok().getLoc();
3867 if (getLexer().getKind() == AsmToken::Identifier) {
3868 Prefix = Parser.getTok().getString();
3870 return MatchOperand_NoMatch;
3873 if (Prefix == "row_mirror") {
3876 } else if (Prefix == "row_half_mirror") {
3880 // Check to prevent parseDPPCtrlOps from eating invalid tokens
3881 if (Prefix != "quad_perm"
3882 && Prefix != "row_shl"
3883 && Prefix != "row_shr"
3884 && Prefix != "row_ror"
3885 && Prefix != "wave_shl"
3886 && Prefix != "wave_rol"
3887 && Prefix != "wave_shr"
3888 && Prefix != "wave_ror"
3889 && Prefix != "row_bcast") {
3890 return MatchOperand_NoMatch;
3894 if (getLexer().isNot(AsmToken::Colon))
3895 return MatchOperand_ParseFail;
3897 if (Prefix == "quad_perm") {
3898 // quad_perm:[%d,%d,%d,%d]
3900 if (getLexer().isNot(AsmToken::LBrac))
3901 return MatchOperand_ParseFail;
3904 if (getParser().parseAbsoluteExpression(Int) || !(0 <= Int && Int <=3))
3905 return MatchOperand_ParseFail;
3907 for (int i = 0; i < 3; ++i) {
3908 if (getLexer().isNot(AsmToken::Comma))
3909 return MatchOperand_ParseFail;
3913 if (getParser().parseAbsoluteExpression(Temp) || !(0 <= Temp && Temp <=3))
3914 return MatchOperand_ParseFail;
3915 const int shift = i*2 + 2;
3916 Int += (Temp << shift);
3919 if (getLexer().isNot(AsmToken::RBrac))
3920 return MatchOperand_ParseFail;
3926 if (getParser().parseAbsoluteExpression(Int))
3927 return MatchOperand_ParseFail;
3929 if (Prefix == "row_shl" && 1 <= Int && Int <= 15) {
3931 } else if (Prefix == "row_shr" && 1 <= Int && Int <= 15) {
3933 } else if (Prefix == "row_ror" && 1 <= Int && Int <= 15) {
3935 } else if (Prefix == "wave_shl" && 1 == Int) {
3937 } else if (Prefix == "wave_rol" && 1 == Int) {
3939 } else if (Prefix == "wave_shr" && 1 == Int) {
3941 } else if (Prefix == "wave_ror" && 1 == Int) {
3943 } else if (Prefix == "row_bcast") {
3946 } else if (Int == 31) {
3949 return MatchOperand_ParseFail;
3952 return MatchOperand_ParseFail;
3957 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTyDppCtrl));
3958 return MatchOperand_Success;
3961 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultRowMask() const {
3962 return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppRowMask);
3965 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBankMask() const {
3966 return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppBankMask);
3969 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBoundCtrl() const {
3970 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppBoundCtrl);
3973 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands) {
3974 OptionalImmIndexMap OptionalIdx;
3977 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3978 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
3979 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
3982 for (unsigned E = Operands.size(); I != E; ++I) {
3983 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
3984 // Add the register arguments
3985 if (Op.isReg() && Op.Reg.RegNo == AMDGPU::VCC) {
3986 // VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.
3989 } if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
3990 Op.addRegWithFPInputModsOperands(Inst, 2);
3991 } else if (Op.isDPPCtrl()) {
3992 Op.addImmOperands(Inst, 1);
3993 } else if (Op.isImm()) {
3994 // Handle optional arguments
3995 OptionalIdx[Op.getImmTy()] = I;
3997 llvm_unreachable("Invalid operand type");
4001 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
4002 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
4003 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
4005 // special case v_mac_{f16, f32}:
4006 // it has src2 register operand that is tied to dst operand
4007 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_dpp ||
4008 Inst.getOpcode() == AMDGPU::V_MAC_F16_dpp) {
4009 auto it = Inst.begin();
4011 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));
4012 Inst.insert(it, Inst.getOperand(0)); // src2 = dst
4016 //===----------------------------------------------------------------------===//
4018 //===----------------------------------------------------------------------===//
4020 OperandMatchResultTy
4021 AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,
4022 AMDGPUOperand::ImmTy Type) {
4023 using namespace llvm::AMDGPU::SDWA;
4025 SMLoc S = Parser.getTok().getLoc();
4027 OperandMatchResultTy res;
4029 res = parseStringWithPrefix(Prefix, Value);
4030 if (res != MatchOperand_Success) {
4035 Int = StringSwitch<int64_t>(Value)
4036 .Case("BYTE_0", SdwaSel::BYTE_0)
4037 .Case("BYTE_1", SdwaSel::BYTE_1)
4038 .Case("BYTE_2", SdwaSel::BYTE_2)
4039 .Case("BYTE_3", SdwaSel::BYTE_3)
4040 .Case("WORD_0", SdwaSel::WORD_0)
4041 .Case("WORD_1", SdwaSel::WORD_1)
4042 .Case("DWORD", SdwaSel::DWORD)
4043 .Default(0xffffffff);
4044 Parser.Lex(); // eat last token
4046 if (Int == 0xffffffff) {
4047 return MatchOperand_ParseFail;
4050 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));
4051 return MatchOperand_Success;
4054 OperandMatchResultTy
4055 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
4056 using namespace llvm::AMDGPU::SDWA;
4058 SMLoc S = Parser.getTok().getLoc();
4060 OperandMatchResultTy res;
4062 res = parseStringWithPrefix("dst_unused", Value);
4063 if (res != MatchOperand_Success) {
4068 Int = StringSwitch<int64_t>(Value)
4069 .Case("UNUSED_PAD", DstUnused::UNUSED_PAD)
4070 .Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)
4071 .Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)
4072 .Default(0xffffffff);
4073 Parser.Lex(); // eat last token
4075 if (Int == 0xffffffff) {
4076 return MatchOperand_ParseFail;
4079 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySdwaDstUnused));
4080 return MatchOperand_Success;
4083 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
4084 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);
4087 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
4088 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);
4091 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
4092 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC);
4095 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
4096 uint64_t BasicInstType) {
4097 using namespace llvm::AMDGPU::SDWA;
4098 OptionalImmIndexMap OptionalIdx;
4101 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
4102 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
4103 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
4106 for (unsigned E = Operands.size(); I != E; ++I) {
4107 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
4108 // Add the register arguments
4109 if ((BasicInstType == SIInstrFlags::VOPC ||
4110 BasicInstType == SIInstrFlags::VOP2)&&
4112 Op.Reg.RegNo == AMDGPU::VCC) {
4113 // VOPC and VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.
4116 } else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
4117 Op.addRegWithInputModsOperands(Inst, 2);
4118 } else if (Op.isImm()) {
4119 // Handle optional arguments
4120 OptionalIdx[Op.getImmTy()] = I;
4122 llvm_unreachable("Invalid operand type");
4126 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
4128 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) {
4129 // V_NOP_sdwa_vi has no optional sdwa arguments
4130 switch (BasicInstType) {
4131 case SIInstrFlags::VOP1:
4132 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
4133 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE);
4134 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
4137 case SIInstrFlags::VOP2:
4138 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
4139 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE);
4140 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
4141 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
4144 case SIInstrFlags::VOPC:
4145 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
4146 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
4150 llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
4154 // special case v_mac_{f16, f32}:
4155 // it has src2 register operand that is tied to dst operand
4156 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi ||
4157 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
4158 auto it = Inst.begin();
4160 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));
4161 Inst.insert(it, Inst.getOperand(0)); // src2 = dst
4166 /// Force static initialization.
4167 extern "C" void LLVMInitializeAMDGPUAsmParser() {
4168 RegisterMCAsmParser<AMDGPUAsmParser> A(getTheAMDGPUTarget());
4169 RegisterMCAsmParser<AMDGPUAsmParser> B(getTheGCNTarget());
4172 #define GET_REGISTER_MATCHER
4173 #define GET_MATCHER_IMPLEMENTATION
4174 #include "AMDGPUGenAsmMatcher.inc"
4176 // This fuction should be defined after auto-generated include so that we have
4177 // MatchClassKind enum defined
4178 unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
4180 // Tokens like "glc" would be parsed as immediate operands in ParseOperand().
4181 // But MatchInstructionImpl() expects to meet token and fails to validate
4182 // operand. This method checks if we are given immediate operand but expect to
4183 // get corresponding token.
4184 AMDGPUOperand &Operand = (AMDGPUOperand&)Op;
4187 return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;
4189 return Operand.isGDS() ? Match_Success : Match_InvalidOperand;
4191 return Operand.isGLC() ? Match_Success : Match_InvalidOperand;
4193 return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;
4195 return Operand.isOffen() ? Match_Success : Match_InvalidOperand;
4197 // When operands have expression values, they will return true for isToken,
4198 // because it is not possible to distinguish between a token and an
4199 // expression at parse time. MatchInstructionImpl() will always try to
4200 // match an operand as a token, when isToken returns true, and when the
4201 // name of the expression is not a valid token, the match will fail,
4202 // so we need to handle it here.
4203 return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;
4205 return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;
4206 case MCK_SoppBrTarget:
4207 return Operand.isSoppBrTarget() ? Match_Success : Match_InvalidOperand;
4208 case MCK_VReg32OrOff:
4209 return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
4210 case MCK_InterpSlot:
4211 return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;
4213 return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;
4215 return Operand.isAttrChan() ? Match_Success : Match_InvalidOperand;
4217 return Match_InvalidOperand;