1 //===-- BUFInstructions.td - Buffer Instruction Defintions ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
11 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
12 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
14 def MUBUFScratchOffen : ComplexPattern<i64, 4, "SelectMUBUFScratchOffen", [], [SDNPWantParent]>;
15 def MUBUFScratchOffset : ComplexPattern<i64, 3, "SelectMUBUFScratchOffset", [], [SDNPWantParent], 20>;
17 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
18 def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">;
19 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
20 def MUBUFIntrinsicOffset : ComplexPattern<i32, 2, "SelectMUBUFIntrinsicOffset">;
21 def MUBUFIntrinsicVOffset : ComplexPattern<i32, 3, "SelectMUBUFIntrinsicVOffset">;
23 class MubufLoad <SDPatternOperator op> : PatFrag <
24 (ops node:$ptr), (op node:$ptr), [{
25 auto const AS = cast<MemSDNode>(N)->getAddressSpace();
26 return AS == AMDGPUASI.GLOBAL_ADDRESS ||
27 AS == AMDGPUASI.CONSTANT_ADDRESS;
30 def mubuf_load : MubufLoad <load>;
31 def mubuf_az_extloadi8 : MubufLoad <az_extloadi8>;
32 def mubuf_sextloadi8 : MubufLoad <sextloadi8>;
33 def mubuf_az_extloadi16 : MubufLoad <az_extloadi16>;
34 def mubuf_sextloadi16 : MubufLoad <sextloadi16>;
35 def mubuf_load_atomic : MubufLoad <atomic_load>;
45 class getAddrName<int addrKind> {
47 !if(!eq(addrKind, BUFAddrKind.Offset), "offset",
48 !if(!eq(addrKind, BUFAddrKind.OffEn), "offen",
49 !if(!eq(addrKind, BUFAddrKind.IdxEn), "idxen",
50 !if(!eq(addrKind, BUFAddrKind.BothEn), "bothen",
51 !if(!eq(addrKind, BUFAddrKind.Addr64), "addr64",
55 class MUBUFAddr64Table <bit is_addr64, string Name> {
56 bit IsAddr64 = is_addr64;
60 class MUBUFLdsTable <bit is_lds, string Name> {
65 class MTBUFAddr64Table <bit is_addr64, string Name> {
66 bit IsAddr64 = is_addr64;
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
74 class MTBUF_Pseudo <string opName, dag outs, dag ins,
75 string asmOps, list<dag> pattern=[]> :
76 InstSI<outs, ins, "", pattern>,
77 SIMCInstr<opName, SIEncodingFamily.NONE> {
80 let isCodeGenOnly = 1;
82 let UseNamedOperandTable = 1;
84 string Mnemonic = opName;
85 string AsmOperands = asmOps;
91 let hasSideEffects = 0;
92 let SchedRW = [WriteVMEM];
94 let AsmMatchConverter = "cvtMtbuf";
99 bits<1> has_vdata = 1;
100 bits<1> has_vaddr = 1;
102 bits<1> glc_value = 0; // the value for glc if no such operand
103 bits<4> dfmt_value = 1; // the value for dfmt if no such operand
104 bits<3> nfmt_value = 0; // the value for nfmt if no such operand
105 bits<1> has_srsrc = 1;
106 bits<1> has_soffset = 1;
107 bits<1> has_offset = 1;
110 bits<1> has_dfmt = 1;
111 bits<1> has_nfmt = 1;
114 class MTBUF_Real <MTBUF_Pseudo ps> :
115 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
118 let isCodeGenOnly = 0;
120 // copy relevant pseudo op flags
121 let SubtargetPredicate = ps.SubtargetPredicate;
122 let AsmMatchConverter = ps.AsmMatchConverter;
123 let Constraints = ps.Constraints;
124 let DisableEncoding = ps.DisableEncoding;
125 let TSFlags = ps.TSFlags;
139 class getMTBUFInsDA<list<RegisterClass> vdataList,
140 list<RegisterClass> vaddrList=[]> {
141 RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
142 RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
143 dag InsNoData = !if(!empty(vaddrList),
144 (ins SReg_128:$srsrc, SCSrc_b32:$soffset,
145 offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, SLC:$slc, TFE:$tfe),
146 (ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
147 offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, SLC:$slc, TFE:$tfe)
149 dag InsData = !if(!empty(vaddrList),
150 (ins vdataClass:$vdata, SReg_128:$srsrc,
151 SCSrc_b32:$soffset, offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc,
153 (ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
154 SCSrc_b32:$soffset, offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc,
157 dag ret = !if(!empty(vdataList), InsNoData, InsData);
160 class getMTBUFIns<int addrKind, list<RegisterClass> vdataList=[]> {
162 !if(!eq(addrKind, BUFAddrKind.Offset), getMTBUFInsDA<vdataList>.ret,
163 !if(!eq(addrKind, BUFAddrKind.OffEn), getMTBUFInsDA<vdataList, [VGPR_32]>.ret,
164 !if(!eq(addrKind, BUFAddrKind.IdxEn), getMTBUFInsDA<vdataList, [VGPR_32]>.ret,
165 !if(!eq(addrKind, BUFAddrKind.BothEn), getMTBUFInsDA<vdataList, [VReg_64]>.ret,
166 !if(!eq(addrKind, BUFAddrKind.Addr64), getMTBUFInsDA<vdataList, [VReg_64]>.ret,
170 class getMTBUFAsmOps<int addrKind> {
172 !if(!eq(addrKind, BUFAddrKind.Offset), "off, $srsrc, $dfmt, $nfmt, $soffset",
173 !if(!eq(addrKind, BUFAddrKind.OffEn),
174 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset offen",
175 !if(!eq(addrKind, BUFAddrKind.IdxEn),
176 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset idxen",
177 !if(!eq(addrKind, BUFAddrKind.BothEn),
178 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset idxen offen",
179 !if(!eq(addrKind, BUFAddrKind.Addr64),
180 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset addr64",
182 string ret = Pfx # "$offset";
185 class MTBUF_SetupAddr<int addrKind> {
186 bits<1> offen = !if(!eq(addrKind, BUFAddrKind.OffEn), 1,
187 !if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));
189 bits<1> idxen = !if(!eq(addrKind, BUFAddrKind.IdxEn), 1,
190 !if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));
192 bits<1> addr64 = !if(!eq(addrKind, BUFAddrKind.Addr64), 1, 0);
194 bits<1> has_vaddr = !if(!eq(addrKind, BUFAddrKind.Offset), 0, 1);
197 class MTBUF_Load_Pseudo <string opName,
199 RegisterClass vdataClass,
200 list<dag> pattern=[],
201 // Workaround bug bz30254
202 int addrKindCopy = addrKind>
203 : MTBUF_Pseudo<opName,
204 (outs vdataClass:$vdata),
205 getMTBUFIns<addrKindCopy>.ret,
206 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
208 MTBUF_SetupAddr<addrKindCopy> {
209 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
214 multiclass MTBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
215 ValueType load_vt = i32,
216 SDPatternOperator ld = null_frag> {
218 def _OFFSET : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
219 [(set load_vt:$vdata,
220 (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i8:$dfmt,
221 i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
222 MTBUFAddr64Table<0, NAME>;
224 def _ADDR64 : MTBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
225 [(set load_vt:$vdata,
226 (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset,
227 i8:$dfmt, i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
228 MTBUFAddr64Table<1, NAME>;
230 def _OFFEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
231 def _IDXEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
232 def _BOTHEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
234 let DisableWQM = 1 in {
235 def _OFFSET_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
236 def _OFFEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
237 def _IDXEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
238 def _BOTHEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
242 class MTBUF_Store_Pseudo <string opName,
244 RegisterClass vdataClass,
245 list<dag> pattern=[],
246 // Workaround bug bz30254
247 int addrKindCopy = addrKind,
248 RegisterClass vdataClassCopy = vdataClass>
249 : MTBUF_Pseudo<opName,
251 getMTBUFIns<addrKindCopy, [vdataClassCopy]>.ret,
252 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
254 MTBUF_SetupAddr<addrKindCopy> {
255 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
260 multiclass MTBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
261 ValueType store_vt = i32,
262 SDPatternOperator st = null_frag> {
264 def _OFFSET : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
265 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
266 i16:$offset, i8:$dfmt, i8:$nfmt, i1:$glc,
267 i1:$slc, i1:$tfe))]>,
268 MTBUFAddr64Table<0, NAME>;
270 def _ADDR64 : MTBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
271 [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
272 i16:$offset, i8:$dfmt, i8:$nfmt, i1:$glc,
273 i1:$slc, i1:$tfe))]>,
274 MTBUFAddr64Table<1, NAME>;
276 def _OFFEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
277 def _IDXEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
278 def _BOTHEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
280 let DisableWQM = 1 in {
281 def _OFFSET_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
282 def _OFFEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
283 def _IDXEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
284 def _BOTHEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
289 //===----------------------------------------------------------------------===//
291 //===----------------------------------------------------------------------===//
293 class MUBUF_Pseudo <string opName, dag outs, dag ins,
294 string asmOps, list<dag> pattern=[]> :
295 InstSI<outs, ins, "", pattern>,
296 SIMCInstr<opName, SIEncodingFamily.NONE> {
299 let isCodeGenOnly = 1;
301 let UseNamedOperandTable = 1;
303 string Mnemonic = opName;
304 string AsmOperands = asmOps;
310 let hasSideEffects = 0;
311 let SchedRW = [WriteVMEM];
313 let AsmMatchConverter = "cvtMubuf";
319 bits<1> has_vdata = 1;
320 bits<1> has_vaddr = 1;
322 bits<1> glc_value = 0; // the value for glc if no such operand
323 bits<1> has_srsrc = 1;
324 bits<1> has_soffset = 1;
325 bits<1> has_offset = 1;
330 class MUBUF_Real <bits<7> op, MUBUF_Pseudo ps> :
331 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
334 let isCodeGenOnly = 0;
336 // copy relevant pseudo op flags
337 let SubtargetPredicate = ps.SubtargetPredicate;
338 let AsmMatchConverter = ps.AsmMatchConverter;
339 let Constraints = ps.Constraints;
340 let DisableEncoding = ps.DisableEncoding;
341 let TSFlags = ps.TSFlags;
354 // For cache invalidation instructions.
355 class MUBUF_Invalidate <string opName, SDPatternOperator node> :
356 MUBUF_Pseudo<opName, (outs), (ins), "", [(node)]> {
358 let AsmMatchConverter = "";
360 let hasSideEffects = 1;
363 // Set everything to 0.
378 class getMUBUFInsDA<list<RegisterClass> vdataList,
379 list<RegisterClass> vaddrList=[],
381 RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
382 RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
383 dag InsNoData = !if(!empty(vaddrList),
384 (ins SReg_128:$srsrc, SCSrc_b32:$soffset,
385 offset:$offset, GLC:$glc, SLC:$slc),
386 (ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
387 offset:$offset, GLC:$glc, SLC:$slc)
389 dag InsData = !if(!empty(vaddrList),
390 (ins vdataClass:$vdata, SReg_128:$srsrc,
391 SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc),
392 (ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
393 SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc)
396 !if(!empty(vdataList), InsNoData, InsData),
397 !if(isLds, (ins), (ins TFE:$tfe))
401 class getMUBUFIns<int addrKind, list<RegisterClass> vdataList=[], bit isLds = 0> {
403 !if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList, [], isLds>.ret,
404 !if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPR_32], isLds>.ret,
405 !if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPR_32], isLds>.ret,
406 !if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64], isLds>.ret,
407 !if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64], isLds>.ret,
411 class getMUBUFAsmOps<int addrKind> {
413 !if(!eq(addrKind, BUFAddrKind.Offset), "off, $srsrc, $soffset",
414 !if(!eq(addrKind, BUFAddrKind.OffEn), "$vaddr, $srsrc, $soffset offen",
415 !if(!eq(addrKind, BUFAddrKind.IdxEn), "$vaddr, $srsrc, $soffset idxen",
416 !if(!eq(addrKind, BUFAddrKind.BothEn), "$vaddr, $srsrc, $soffset idxen offen",
417 !if(!eq(addrKind, BUFAddrKind.Addr64), "$vaddr, $srsrc, $soffset addr64",
419 string ret = Pfx # "$offset";
422 class MUBUF_SetupAddr<int addrKind> {
423 bits<1> offen = !if(!eq(addrKind, BUFAddrKind.OffEn), 1,
424 !if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));
426 bits<1> idxen = !if(!eq(addrKind, BUFAddrKind.IdxEn), 1,
427 !if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));
429 bits<1> addr64 = !if(!eq(addrKind, BUFAddrKind.Addr64), 1, 0);
431 bits<1> has_vaddr = !if(!eq(addrKind, BUFAddrKind.Offset), 0, 1);
434 class MUBUF_Load_Pseudo <string opName,
436 RegisterClass vdataClass,
439 list<dag> pattern=[],
440 // Workaround bug bz30254
441 int addrKindCopy = addrKind>
442 : MUBUF_Pseudo<opName,
443 (outs vdataClass:$vdata),
444 !con(getMUBUFIns<addrKindCopy, [], isLds>.ret,
445 !if(HasTiedDest, (ins vdataClass:$vdata_in), (ins))),
446 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc" #
447 !if(isLds, " lds", "$tfe"),
449 MUBUF_SetupAddr<addrKindCopy> {
450 let PseudoInstr = opName # !if(isLds, "_lds", "") #
451 "_" # getAddrName<addrKindCopy>.ret;
452 let AsmMatchConverter = !if(isLds, "cvtMubufLds", "cvtMubuf");
454 let Constraints = !if(HasTiedDest, "$vdata = $vdata_in", "");
458 let Uses = !if(isLds, [EXEC, M0], [EXEC]);
459 let has_tfe = !if(isLds, 0, 1);
463 // FIXME: tfe can't be an operand because it requires a separate
464 // opcode because it needs an N+1 register class dest register.
465 multiclass MUBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
466 ValueType load_vt = i32,
467 SDPatternOperator ld = null_frag,
471 def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
475 [(set load_vt:$vdata,
476 (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
477 MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>;
479 def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
483 [(set load_vt:$vdata,
484 (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
485 MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>;
487 def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;
488 def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;
489 def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>;
491 let DisableWQM = 1 in {
492 def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest, isLds>;
493 def _OFFEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;
494 def _IDXEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;
495 def _BOTHEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>;
499 multiclass MUBUF_Pseudo_Loads_Lds<string opName, RegisterClass vdataClass,
500 ValueType load_vt = i32,
501 SDPatternOperator ld_nolds = null_frag,
502 SDPatternOperator ld_lds = null_frag> {
503 defm NAME : MUBUF_Pseudo_Loads<opName, vdataClass, load_vt, ld_nolds>;
504 defm _LDS : MUBUF_Pseudo_Loads<opName, vdataClass, load_vt, ld_lds, 0, 1>;
507 class MUBUF_Store_Pseudo <string opName,
509 RegisterClass vdataClass,
510 list<dag> pattern=[],
511 // Workaround bug bz30254
512 int addrKindCopy = addrKind,
513 RegisterClass vdataClassCopy = vdataClass>
514 : MUBUF_Pseudo<opName,
516 getMUBUFIns<addrKindCopy, [vdataClassCopy]>.ret,
517 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
519 MUBUF_SetupAddr<addrKindCopy> {
520 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
526 multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
527 ValueType store_vt = i32,
528 SDPatternOperator st = null_frag> {
530 def _OFFSET : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
531 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
532 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
533 MUBUFAddr64Table<0, NAME>;
535 def _ADDR64 : MUBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
536 [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
537 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
538 MUBUFAddr64Table<1, NAME>;
540 def _OFFEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
541 def _IDXEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
542 def _BOTHEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
544 let DisableWQM = 1 in {
545 def _OFFSET_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
546 def _OFFEN_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
547 def _IDXEN_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
548 def _BOTHEN_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
552 class MUBUF_Pseudo_Store_Lds<string opName>
553 : MUBUF_Pseudo<opName,
555 (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc),
556 " $srsrc, $soffset$offset lds$glc$slc"> {
566 let Uses = [EXEC, M0];
567 let AsmMatchConverter = "cvtMubufLds";
570 class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in,
571 list<RegisterClass> vaddrList=[]> {
572 RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
573 dag ret = !if(vdata_in,
574 !if(!empty(vaddrList),
575 (ins vdataClass:$vdata_in,
576 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc),
577 (ins vdataClass:$vdata_in, vaddrClass:$vaddr,
578 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc)
580 !if(!empty(vaddrList),
581 (ins vdataClass:$vdata,
582 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc),
583 (ins vdataClass:$vdata, vaddrClass:$vaddr,
584 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc)
588 class getMUBUFAtomicIns<int addrKind,
589 RegisterClass vdataClass,
591 // Workaround bug bz30254
592 RegisterClass vdataClassCopy=vdataClass> {
594 !if(!eq(addrKind, BUFAddrKind.Offset),
595 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in>.ret,
596 !if(!eq(addrKind, BUFAddrKind.OffEn),
597 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VGPR_32]>.ret,
598 !if(!eq(addrKind, BUFAddrKind.IdxEn),
599 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VGPR_32]>.ret,
600 !if(!eq(addrKind, BUFAddrKind.BothEn),
601 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VReg_64]>.ret,
602 !if(!eq(addrKind, BUFAddrKind.Addr64),
603 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VReg_64]>.ret,
607 class MUBUF_Atomic_Pseudo<string opName,
612 list<dag> pattern=[],
613 // Workaround bug bz30254
614 int addrKindCopy = addrKind>
615 : MUBUF_Pseudo<opName, outs, ins, asmOps, pattern>,
616 MUBUF_SetupAddr<addrKindCopy> {
619 let hasPostISelHook = 1;
620 let hasSideEffects = 1;
627 class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind,
628 RegisterClass vdataClass,
629 list<dag> pattern=[],
630 // Workaround bug bz30254
631 int addrKindCopy = addrKind,
632 RegisterClass vdataClassCopy = vdataClass>
633 : MUBUF_Atomic_Pseudo<opName, addrKindCopy,
635 getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 0>.ret,
636 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$slc",
638 AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 0> {
639 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
641 let AsmMatchConverter = "cvtMubufAtomic";
644 class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
645 RegisterClass vdataClass,
646 list<dag> pattern=[],
647 // Workaround bug bz30254
648 int addrKindCopy = addrKind,
649 RegisterClass vdataClassCopy = vdataClass>
650 : MUBUF_Atomic_Pseudo<opName, addrKindCopy,
651 (outs vdataClassCopy:$vdata),
652 getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 1>.ret,
653 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # " glc$slc",
655 AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 1> {
656 let PseudoInstr = opName # "_rtn_" # getAddrName<addrKindCopy>.ret;
658 let Constraints = "$vdata = $vdata_in";
659 let DisableEncoding = "$vdata_in";
660 let AsmMatchConverter = "cvtMubufAtomicReturn";
663 multiclass MUBUF_Pseudo_Atomics <string opName,
664 RegisterClass vdataClass,
666 SDPatternOperator atomic> {
668 def _OFFSET : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass>,
669 MUBUFAddr64Table <0, NAME>;
670 def _ADDR64 : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass>,
671 MUBUFAddr64Table <1, NAME>;
672 def _OFFEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
673 def _IDXEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
674 def _BOTHEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
676 def _OFFSET_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
677 [(set vdataType:$vdata,
678 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$slc),
679 vdataType:$vdata_in))]>,
680 MUBUFAddr64Table <0, NAME # "_RTN">;
682 def _ADDR64_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
683 [(set vdataType:$vdata,
684 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc),
685 vdataType:$vdata_in))]>,
686 MUBUFAddr64Table <1, NAME # "_RTN">;
688 def _OFFEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
689 def _IDXEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
690 def _BOTHEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
694 //===----------------------------------------------------------------------===//
695 // MUBUF Instructions
696 //===----------------------------------------------------------------------===//
698 defm BUFFER_LOAD_FORMAT_X : MUBUF_Pseudo_Loads_Lds <
699 "buffer_load_format_x", VGPR_32
701 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Pseudo_Loads <
702 "buffer_load_format_xy", VReg_64
704 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Pseudo_Loads <
705 "buffer_load_format_xyz", VReg_96
707 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Pseudo_Loads <
708 "buffer_load_format_xyzw", VReg_128
710 defm BUFFER_STORE_FORMAT_X : MUBUF_Pseudo_Stores <
711 "buffer_store_format_x", VGPR_32
713 defm BUFFER_STORE_FORMAT_XY : MUBUF_Pseudo_Stores <
714 "buffer_store_format_xy", VReg_64
716 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Pseudo_Stores <
717 "buffer_store_format_xyz", VReg_96
719 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Pseudo_Stores <
720 "buffer_store_format_xyzw", VReg_128
723 let SubtargetPredicate = HasUnpackedD16VMem, D16Buf = 1 in {
724 defm BUFFER_LOAD_FORMAT_D16_X_gfx80 : MUBUF_Pseudo_Loads <
725 "buffer_load_format_d16_x", VGPR_32
727 defm BUFFER_LOAD_FORMAT_D16_XY_gfx80 : MUBUF_Pseudo_Loads <
728 "buffer_load_format_d16_xy", VReg_64
730 defm BUFFER_LOAD_FORMAT_D16_XYZ_gfx80 : MUBUF_Pseudo_Loads <
731 "buffer_load_format_d16_xyz", VReg_96
733 defm BUFFER_LOAD_FORMAT_D16_XYZW_gfx80 : MUBUF_Pseudo_Loads <
734 "buffer_load_format_d16_xyzw", VReg_128
736 defm BUFFER_STORE_FORMAT_D16_X_gfx80 : MUBUF_Pseudo_Stores <
737 "buffer_store_format_d16_x", VGPR_32
739 defm BUFFER_STORE_FORMAT_D16_XY_gfx80 : MUBUF_Pseudo_Stores <
740 "buffer_store_format_d16_xy", VReg_64
742 defm BUFFER_STORE_FORMAT_D16_XYZ_gfx80 : MUBUF_Pseudo_Stores <
743 "buffer_store_format_d16_xyz", VReg_96
745 defm BUFFER_STORE_FORMAT_D16_XYZW_gfx80 : MUBUF_Pseudo_Stores <
746 "buffer_store_format_d16_xyzw", VReg_128
748 } // End HasUnpackedD16VMem.
750 let SubtargetPredicate = HasPackedD16VMem, D16Buf = 1 in {
751 defm BUFFER_LOAD_FORMAT_D16_X : MUBUF_Pseudo_Loads <
752 "buffer_load_format_d16_x", VGPR_32
754 defm BUFFER_LOAD_FORMAT_D16_XY : MUBUF_Pseudo_Loads <
755 "buffer_load_format_d16_xy", VGPR_32
757 defm BUFFER_LOAD_FORMAT_D16_XYZ : MUBUF_Pseudo_Loads <
758 "buffer_load_format_d16_xyz", VReg_64
760 defm BUFFER_LOAD_FORMAT_D16_XYZW : MUBUF_Pseudo_Loads <
761 "buffer_load_format_d16_xyzw", VReg_64
763 defm BUFFER_STORE_FORMAT_D16_X : MUBUF_Pseudo_Stores <
764 "buffer_store_format_d16_x", VGPR_32
766 defm BUFFER_STORE_FORMAT_D16_XY : MUBUF_Pseudo_Stores <
767 "buffer_store_format_d16_xy", VGPR_32
769 defm BUFFER_STORE_FORMAT_D16_XYZ : MUBUF_Pseudo_Stores <
770 "buffer_store_format_d16_xyz", VReg_64
772 defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Pseudo_Stores <
773 "buffer_store_format_d16_xyzw", VReg_64
775 } // End HasPackedD16VMem.
777 defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads_Lds <
778 "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
780 defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads_Lds <
781 "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
783 defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads_Lds <
784 "buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16
786 defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads_Lds <
787 "buffer_load_sshort", VGPR_32, i32, mubuf_sextloadi16
789 defm BUFFER_LOAD_DWORD : MUBUF_Pseudo_Loads_Lds <
790 "buffer_load_dword", VGPR_32, i32, mubuf_load
792 defm BUFFER_LOAD_DWORDX2 : MUBUF_Pseudo_Loads <
793 "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load
795 defm BUFFER_LOAD_DWORDX3 : MUBUF_Pseudo_Loads <
796 "buffer_load_dwordx3", VReg_96, untyped, mubuf_load
798 defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads <
799 "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load
802 // This is not described in AMD documentation,
803 // but 'lds' versions of these opcodes are available
804 // in at least GFX8+ chips. See Bug 37653.
805 let SubtargetPredicate = isVI in {
806 defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads <
807 "buffer_load_dwordx2", VReg_64, v2i32, null_frag, 0, 1
809 defm BUFFER_LOAD_DWORDX3_LDS : MUBUF_Pseudo_Loads <
810 "buffer_load_dwordx3", VReg_96, untyped, null_frag, 0, 1
812 defm BUFFER_LOAD_DWORDX4_LDS : MUBUF_Pseudo_Loads <
813 "buffer_load_dwordx4", VReg_128, v4i32, null_frag, 0, 1
817 defm BUFFER_STORE_BYTE : MUBUF_Pseudo_Stores <
818 "buffer_store_byte", VGPR_32, i32, truncstorei8_global
820 defm BUFFER_STORE_SHORT : MUBUF_Pseudo_Stores <
821 "buffer_store_short", VGPR_32, i32, truncstorei16_global
823 defm BUFFER_STORE_DWORD : MUBUF_Pseudo_Stores <
824 "buffer_store_dword", VGPR_32, i32, store_global
826 defm BUFFER_STORE_DWORDX2 : MUBUF_Pseudo_Stores <
827 "buffer_store_dwordx2", VReg_64, v2i32, store_global
829 defm BUFFER_STORE_DWORDX3 : MUBUF_Pseudo_Stores <
830 "buffer_store_dwordx3", VReg_96, untyped, store_global
832 defm BUFFER_STORE_DWORDX4 : MUBUF_Pseudo_Stores <
833 "buffer_store_dwordx4", VReg_128, v4i32, store_global
835 defm BUFFER_ATOMIC_SWAP : MUBUF_Pseudo_Atomics <
836 "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
838 defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Pseudo_Atomics <
839 "buffer_atomic_cmpswap", VReg_64, v2i32, null_frag
841 defm BUFFER_ATOMIC_ADD : MUBUF_Pseudo_Atomics <
842 "buffer_atomic_add", VGPR_32, i32, atomic_add_global
844 defm BUFFER_ATOMIC_SUB : MUBUF_Pseudo_Atomics <
845 "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
847 defm BUFFER_ATOMIC_SMIN : MUBUF_Pseudo_Atomics <
848 "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
850 defm BUFFER_ATOMIC_UMIN : MUBUF_Pseudo_Atomics <
851 "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
853 defm BUFFER_ATOMIC_SMAX : MUBUF_Pseudo_Atomics <
854 "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
856 defm BUFFER_ATOMIC_UMAX : MUBUF_Pseudo_Atomics <
857 "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
859 defm BUFFER_ATOMIC_AND : MUBUF_Pseudo_Atomics <
860 "buffer_atomic_and", VGPR_32, i32, atomic_and_global
862 defm BUFFER_ATOMIC_OR : MUBUF_Pseudo_Atomics <
863 "buffer_atomic_or", VGPR_32, i32, atomic_or_global
865 defm BUFFER_ATOMIC_XOR : MUBUF_Pseudo_Atomics <
866 "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
868 defm BUFFER_ATOMIC_INC : MUBUF_Pseudo_Atomics <
869 "buffer_atomic_inc", VGPR_32, i32, atomic_inc_global
871 defm BUFFER_ATOMIC_DEC : MUBUF_Pseudo_Atomics <
872 "buffer_atomic_dec", VGPR_32, i32, atomic_dec_global
874 defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Pseudo_Atomics <
875 "buffer_atomic_swap_x2", VReg_64, i64, atomic_swap_global
877 defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Pseudo_Atomics <
878 "buffer_atomic_cmpswap_x2", VReg_128, v2i64, null_frag
880 defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Pseudo_Atomics <
881 "buffer_atomic_add_x2", VReg_64, i64, atomic_add_global
883 defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Pseudo_Atomics <
884 "buffer_atomic_sub_x2", VReg_64, i64, atomic_sub_global
886 defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Pseudo_Atomics <
887 "buffer_atomic_smin_x2", VReg_64, i64, atomic_min_global
889 defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Pseudo_Atomics <
890 "buffer_atomic_umin_x2", VReg_64, i64, atomic_umin_global
892 defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Pseudo_Atomics <
893 "buffer_atomic_smax_x2", VReg_64, i64, atomic_max_global
895 defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Pseudo_Atomics <
896 "buffer_atomic_umax_x2", VReg_64, i64, atomic_umax_global
898 defm BUFFER_ATOMIC_AND_X2 : MUBUF_Pseudo_Atomics <
899 "buffer_atomic_and_x2", VReg_64, i64, atomic_and_global
901 defm BUFFER_ATOMIC_OR_X2 : MUBUF_Pseudo_Atomics <
902 "buffer_atomic_or_x2", VReg_64, i64, atomic_or_global
904 defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Pseudo_Atomics <
905 "buffer_atomic_xor_x2", VReg_64, i64, atomic_xor_global
907 defm BUFFER_ATOMIC_INC_X2 : MUBUF_Pseudo_Atomics <
908 "buffer_atomic_inc_x2", VReg_64, i64, atomic_inc_global
910 defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Pseudo_Atomics <
911 "buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
914 let SubtargetPredicate = isVI in {
915 def BUFFER_STORE_LDS_DWORD : MUBUF_Pseudo_Store_Lds <"buffer_store_lds_dword">;
918 let SubtargetPredicate = isSI in { // isn't on CI & VI
920 defm BUFFER_ATOMIC_RSUB : MUBUF_Pseudo_Atomics <"buffer_atomic_rsub">;
921 defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Pseudo_Atomics <"buffer_atomic_fcmpswap">;
922 defm BUFFER_ATOMIC_FMIN : MUBUF_Pseudo_Atomics <"buffer_atomic_fmin">;
923 defm BUFFER_ATOMIC_FMAX : MUBUF_Pseudo_Atomics <"buffer_atomic_fmax">;
924 defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_rsub_x2">;
925 defm BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_fcmpswap_x2">;
926 defm BUFFER_ATOMIC_FMIN_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_fmin_x2">;
927 defm BUFFER_ATOMIC_FMAX_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_fmax_x2">;
930 def BUFFER_WBINVL1_SC : MUBUF_Invalidate <"buffer_wbinvl1_sc",
931 int_amdgcn_buffer_wbinvl1_sc>;
934 let SubtargetPredicate = HasD16LoadStore in {
936 defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Pseudo_Loads <
937 "buffer_load_ubyte_d16", VGPR_32, i32, null_frag, 1
940 defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Pseudo_Loads <
941 "buffer_load_ubyte_d16_hi", VGPR_32, i32, null_frag, 1
944 defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Pseudo_Loads <
945 "buffer_load_sbyte_d16", VGPR_32, i32, null_frag, 1
948 defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Pseudo_Loads <
949 "buffer_load_sbyte_d16_hi", VGPR_32, i32, null_frag, 1
952 defm BUFFER_LOAD_SHORT_D16 : MUBUF_Pseudo_Loads <
953 "buffer_load_short_d16", VGPR_32, i32, null_frag, 1
956 defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Pseudo_Loads <
957 "buffer_load_short_d16_hi", VGPR_32, i32, null_frag, 1
960 defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Pseudo_Stores <
961 "buffer_store_byte_d16_hi", VGPR_32, i32
964 defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Pseudo_Stores <
965 "buffer_store_short_d16_hi", VGPR_32, i32
968 defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Pseudo_Loads <
969 "buffer_load_format_d16_hi_x", VGPR_32
971 defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Pseudo_Stores <
972 "buffer_store_format_d16_hi_x", VGPR_32
975 } // End HasD16LoadStore
977 def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1",
978 int_amdgcn_buffer_wbinvl1>;
980 //===----------------------------------------------------------------------===//
981 // MTBUF Instructions
982 //===----------------------------------------------------------------------===//
984 defm TBUFFER_LOAD_FORMAT_X : MTBUF_Pseudo_Loads <"tbuffer_load_format_x", VGPR_32>;
985 defm TBUFFER_LOAD_FORMAT_XY : MTBUF_Pseudo_Loads <"tbuffer_load_format_xy", VReg_64>;
986 defm TBUFFER_LOAD_FORMAT_XYZ : MTBUF_Pseudo_Loads <"tbuffer_load_format_xyz", VReg_128>;
987 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Pseudo_Loads <"tbuffer_load_format_xyzw", VReg_128>;
988 defm TBUFFER_STORE_FORMAT_X : MTBUF_Pseudo_Stores <"tbuffer_store_format_x", VGPR_32>;
989 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Pseudo_Stores <"tbuffer_store_format_xy", VReg_64>;
990 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyz", VReg_128>;
991 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyzw", VReg_128>;
993 let SubtargetPredicate = HasUnpackedD16VMem, D16Buf = 1 in {
994 defm TBUFFER_LOAD_FORMAT_D16_X_gfx80 : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_x", VGPR_32>;
995 defm TBUFFER_LOAD_FORMAT_D16_XY_gfx80 : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xy", VReg_64>;
996 defm TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80 : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xyz", VReg_96>;
997 defm TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80 : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xyzw", VReg_128>;
998 defm TBUFFER_STORE_FORMAT_D16_X_gfx80 : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_x", VGPR_32>;
999 defm TBUFFER_STORE_FORMAT_D16_XY_gfx80 : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xy", VReg_64>;
1000 defm TBUFFER_STORE_FORMAT_D16_XYZ_gfx80 : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyz", VReg_96>;
1001 defm TBUFFER_STORE_FORMAT_D16_XYZW_gfx80 : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyzw", VReg_128>;
1002 } // End HasUnpackedD16VMem.
1004 let SubtargetPredicate = HasPackedD16VMem, D16Buf = 1 in {
1005 defm TBUFFER_LOAD_FORMAT_D16_X : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_x", VGPR_32>;
1006 defm TBUFFER_LOAD_FORMAT_D16_XY : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xy", VGPR_32>;
1007 defm TBUFFER_LOAD_FORMAT_D16_XYZ : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xyz", VReg_64>;
1008 defm TBUFFER_LOAD_FORMAT_D16_XYZW : MTBUF_Pseudo_Loads <"tbuffer_load_format_d16_xyzw", VReg_64>;
1009 defm TBUFFER_STORE_FORMAT_D16_X : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_x", VGPR_32>;
1010 defm TBUFFER_STORE_FORMAT_D16_XY : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xy", VGPR_32>;
1011 defm TBUFFER_STORE_FORMAT_D16_XYZ : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyz", VReg_64>;
1012 defm TBUFFER_STORE_FORMAT_D16_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyzw", VReg_64>;
1013 } // End HasPackedD16VMem.
1015 let SubtargetPredicate = isCIVI in {
1017 //===----------------------------------------------------------------------===//
1018 // Instruction definitions for CI and newer.
1019 //===----------------------------------------------------------------------===//
1020 // Remaining instructions:
1021 // BUFFER_LOAD_DWORDX3
1022 // BUFFER_STORE_DWORDX3
1024 def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",
1025 int_amdgcn_buffer_wbinvl1_vol>;
1027 } // End let SubtargetPredicate = isCIVI
1029 //===----------------------------------------------------------------------===//
1031 //===----------------------------------------------------------------------===//
1033 //===----------------------------------------------------------------------===//
1034 // buffer_load/store_format patterns
1035 //===----------------------------------------------------------------------===//
1037 multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
1040 (vt (name v4i32:$rsrc, 0,
1041 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1042 imm:$glc, imm:$slc)),
1043 (!cast<MUBUF_Pseudo>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
1044 (as_i1imm $glc), (as_i1imm $slc), 0)
1048 (vt (name v4i32:$rsrc, i32:$vindex,
1049 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1050 imm:$glc, imm:$slc)),
1051 (!cast<MUBUF_Pseudo>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
1052 (as_i1imm $glc), (as_i1imm $slc), 0)
1056 (vt (name v4i32:$rsrc, 0,
1057 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1058 imm:$glc, imm:$slc)),
1059 (!cast<MUBUF_Pseudo>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
1060 (as_i1imm $glc), (as_i1imm $slc), 0)
1064 (vt (name v4i32:$rsrc, i32:$vindex,
1065 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1066 imm:$glc, imm:$slc)),
1067 (!cast<MUBUF_Pseudo>(opcode # _BOTHEN)
1068 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1069 $rsrc, $soffset, (as_i16imm $offset),
1070 (as_i1imm $glc), (as_i1imm $slc), 0)
1074 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">;
1075 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
1076 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
1078 let SubtargetPredicate = HasUnpackedD16VMem in {
1079 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, f16, "BUFFER_LOAD_FORMAT_D16_X_gfx80">;
1080 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v2i32, "BUFFER_LOAD_FORMAT_D16_XY_gfx80">;
1081 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v4i32, "BUFFER_LOAD_FORMAT_D16_XYZW_gfx80">;
1082 } // End HasUnpackedD16VMem.
1084 let SubtargetPredicate = HasPackedD16VMem in {
1085 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, f16, "BUFFER_LOAD_FORMAT_D16_X">;
1086 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v2f16, "BUFFER_LOAD_FORMAT_D16_XY">;
1087 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v4f16, "BUFFER_LOAD_FORMAT_D16_XYZW">;
1088 } // End HasPackedD16VMem.
1090 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, f32, "BUFFER_LOAD_DWORD">;
1091 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
1092 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
1094 multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
1097 (name vt:$vdata, v4i32:$rsrc, 0,
1098 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1099 imm:$glc, imm:$slc),
1100 (!cast<MUBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (as_i16imm $offset),
1101 (as_i1imm $glc), (as_i1imm $slc), 0)
1105 (name vt:$vdata, v4i32:$rsrc, i32:$vindex,
1106 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1107 imm:$glc, imm:$slc),
1108 (!cast<MUBUF_Pseudo>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
1109 (as_i16imm $offset), (as_i1imm $glc),
1114 (name vt:$vdata, v4i32:$rsrc, 0,
1115 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1116 imm:$glc, imm:$slc),
1117 (!cast<MUBUF_Pseudo>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
1118 (as_i16imm $offset), (as_i1imm $glc),
1123 (name vt:$vdata, v4i32:$rsrc, i32:$vindex,
1124 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1125 imm:$glc, imm:$slc),
1126 (!cast<MUBUF_Pseudo>(opcode # _BOTHEN_exact)
1128 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1129 $rsrc, $soffset, (as_i16imm $offset),
1130 (as_i1imm $glc), (as_i1imm $slc), 0)
1134 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
1135 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
1136 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
1138 let SubtargetPredicate = HasUnpackedD16VMem in {
1139 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, f16, "BUFFER_STORE_FORMAT_D16_X_gfx80">;
1140 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v2i32, "BUFFER_STORE_FORMAT_D16_XY_gfx80">;
1141 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v4i32, "BUFFER_STORE_FORMAT_D16_XYZW_gfx80">;
1142 } // End HasUnpackedD16VMem.
1144 let SubtargetPredicate = HasPackedD16VMem in {
1145 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, f16, "BUFFER_STORE_FORMAT_D16_X">;
1146 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v2f16, "BUFFER_STORE_FORMAT_D16_XY">;
1147 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v4f16, "BUFFER_STORE_FORMAT_D16_XYZW">;
1148 } // End HasPackedD16VMem.
1150 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, f32, "BUFFER_STORE_DWORD">;
1151 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
1152 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
1154 //===----------------------------------------------------------------------===//
1155 // buffer_atomic patterns
1156 //===----------------------------------------------------------------------===//
1158 multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> {
1160 (name i32:$vdata_in, v4i32:$rsrc, 0,
1161 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1163 (!cast<MUBUF_Pseudo>(opcode # _OFFSET_RTN) $vdata_in, $rsrc, $soffset,
1164 (as_i16imm $offset), (as_i1imm $slc))
1168 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
1169 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1171 (!cast<MUBUF_Pseudo>(opcode # _IDXEN_RTN) $vdata_in, $vindex, $rsrc, $soffset,
1172 (as_i16imm $offset), (as_i1imm $slc))
1176 (name i32:$vdata_in, v4i32:$rsrc, 0,
1177 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1179 (!cast<MUBUF_Pseudo>(opcode # _OFFEN_RTN) $vdata_in, $voffset, $rsrc, $soffset,
1180 (as_i16imm $offset), (as_i1imm $slc))
1184 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
1185 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1187 (!cast<MUBUF_Pseudo>(opcode # _BOTHEN_RTN)
1189 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1190 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc))
1194 defm : BufferAtomicPatterns<SIbuffer_atomic_swap, "BUFFER_ATOMIC_SWAP">;
1195 defm : BufferAtomicPatterns<SIbuffer_atomic_add, "BUFFER_ATOMIC_ADD">;
1196 defm : BufferAtomicPatterns<SIbuffer_atomic_sub, "BUFFER_ATOMIC_SUB">;
1197 defm : BufferAtomicPatterns<SIbuffer_atomic_smin, "BUFFER_ATOMIC_SMIN">;
1198 defm : BufferAtomicPatterns<SIbuffer_atomic_umin, "BUFFER_ATOMIC_UMIN">;
1199 defm : BufferAtomicPatterns<SIbuffer_atomic_smax, "BUFFER_ATOMIC_SMAX">;
1200 defm : BufferAtomicPatterns<SIbuffer_atomic_umax, "BUFFER_ATOMIC_UMAX">;
1201 defm : BufferAtomicPatterns<SIbuffer_atomic_and, "BUFFER_ATOMIC_AND">;
1202 defm : BufferAtomicPatterns<SIbuffer_atomic_or, "BUFFER_ATOMIC_OR">;
1203 defm : BufferAtomicPatterns<SIbuffer_atomic_xor, "BUFFER_ATOMIC_XOR">;
1206 (SIbuffer_atomic_cmpswap
1207 i32:$data, i32:$cmp, v4i32:$rsrc, 0,
1208 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1211 (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN
1212 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1213 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1218 (SIbuffer_atomic_cmpswap
1219 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
1220 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
1223 (BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN
1224 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1225 $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1230 (SIbuffer_atomic_cmpswap
1231 i32:$data, i32:$cmp, v4i32:$rsrc, 0,
1232 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1235 (BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN
1236 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1237 $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1242 (SIbuffer_atomic_cmpswap
1243 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
1244 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
1247 (BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN
1248 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
1249 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1250 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
1255 class MUBUFLoad_PatternADDR64 <MUBUF_Pseudo Instr_ADDR64, ValueType vt,
1256 PatFrag constant_ld> : GCNPat <
1257 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1258 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
1259 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
1262 multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET,
1263 ValueType vt, PatFrag atomic_ld> {
1265 (vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1266 i16:$offset, i1:$slc))),
1267 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0)
1271 (vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))),
1272 (Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0)
1276 let SubtargetPredicate = isSICI in {
1277 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
1278 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
1279 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
1280 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
1282 defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
1283 defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
1284 } // End SubtargetPredicate = isSICI
1286 multiclass MUBUFLoad_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
1290 (vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1291 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
1292 (Instr_OFFSET $srsrc, $soffset, $offset, $glc, $slc, $tfe)
1296 let OtherPredicates = [Has16BitInsts] in {
1298 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_constant>;
1299 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_constant>;
1300 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, mubuf_sextloadi8>;
1301 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, mubuf_az_extloadi8>;
1303 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_OFFSET, i16, mubuf_load>;
1305 } // End OtherPredicates = [Has16BitInsts]
1307 multiclass MUBUFScratchLoadPat <MUBUF_Pseudo InstrOffen,
1308 MUBUF_Pseudo InstrOffset,
1309 ValueType vt, PatFrag ld> {
1311 (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
1312 i32:$soffset, u16imm:$offset))),
1313 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
1317 (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))),
1318 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0)
1322 // XXX - Is it possible to have a complex pattern in a PatFrag?
1323 multiclass MUBUFScratchLoadPat_Hi16 <MUBUF_Pseudo InstrOffen,
1324 MUBUF_Pseudo InstrOffset,
1325 ValueType vt, PatFrag ld> {
1327 (build_vector vt:$lo, (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
1328 i32:$soffset, u16imm:$offset)))),
1329 (v2i16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $lo))
1333 (build_vector f16:$lo, (f16 (bitconvert (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
1334 i32:$soffset, u16imm:$offset)))))),
1335 (v2f16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $lo))
1340 (build_vector vt:$lo, (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset)))),
1341 (v2i16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $lo))
1345 (build_vector f16:$lo, (f16 (bitconvert (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset)))))),
1346 (v2f16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $lo))
1350 multiclass MUBUFScratchLoadPat_Lo16 <MUBUF_Pseudo InstrOffen,
1351 MUBUF_Pseudo InstrOffset,
1352 ValueType vt, PatFrag ld> {
1354 (build_vector (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
1355 i32:$soffset, u16imm:$offset))),
1356 (vt (Hi16Elt vt:$hi))),
1357 (v2i16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $hi))
1361 (build_vector (f16 (bitconvert (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
1362 i32:$soffset, u16imm:$offset))))),
1363 (f16 (Hi16Elt f16:$hi))),
1364 (v2f16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $hi))
1368 (build_vector (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))),
1369 (vt (Hi16Elt vt:$hi))),
1370 (v2i16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $hi))
1374 (build_vector (f16 (bitconvert (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))))),
1375 (f16 (Hi16Elt f16:$hi))),
1376 (v2f16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $hi))
1380 defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i32, sextloadi8_private>;
1381 defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i32, az_extloadi8_private>;
1382 defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_private>;
1383 defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_private>;
1384 defm : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, BUFFER_LOAD_SSHORT_OFFSET, i32, sextloadi16_private>;
1385 defm : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, BUFFER_LOAD_USHORT_OFFSET, i32, az_extloadi16_private>;
1386 defm : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, BUFFER_LOAD_USHORT_OFFSET, i16, load_private>;
1387 defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, BUFFER_LOAD_DWORD_OFFSET, i32, load_private>;
1388 defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, BUFFER_LOAD_DWORDX2_OFFSET, v2i32, load_private>;
1389 defm : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, BUFFER_LOAD_DWORDX4_OFFSET, v4i32, load_private>;
1391 let OtherPredicates = [D16PreservesUnusedBits] in {
1392 defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_SHORT_D16_HI_OFFEN, BUFFER_LOAD_SHORT_D16_HI_OFFSET, i16, load_private>;
1393 defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_UBYTE_D16_HI_OFFEN, BUFFER_LOAD_UBYTE_D16_HI_OFFSET, i16, az_extloadi8_private>;
1394 defm : MUBUFScratchLoadPat_Hi16<BUFFER_LOAD_SBYTE_D16_HI_OFFEN, BUFFER_LOAD_SBYTE_D16_HI_OFFSET, i16, sextloadi8_private>;
1396 defm : MUBUFScratchLoadPat_Lo16<BUFFER_LOAD_SHORT_D16_OFFEN, BUFFER_LOAD_SHORT_D16_OFFSET, i16, load_private>;
1397 defm : MUBUFScratchLoadPat_Lo16<BUFFER_LOAD_UBYTE_D16_OFFEN, BUFFER_LOAD_UBYTE_D16_OFFSET, i16, az_extloadi8_private>;
1398 defm : MUBUFScratchLoadPat_Lo16<BUFFER_LOAD_SBYTE_D16_OFFEN, BUFFER_LOAD_SBYTE_D16_OFFSET, i16, sextloadi8_private>;
1401 // BUFFER_LOAD_DWORD*, addr64=0
1402 multiclass MUBUF_Load_Dword <ValueType vt,
1403 MUBUF_Pseudo offset,
1406 MUBUF_Pseudo bothen> {
1409 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
1410 imm:$offset, 0, 0, imm:$glc, imm:$slc,
1412 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
1413 (as_i1imm $slc), (as_i1imm $tfe))
1417 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
1418 imm:$offset, 1, 0, imm:$glc, imm:$slc,
1420 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
1425 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
1426 imm:$offset, 0, 1, imm:$glc, imm:$slc,
1428 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
1429 (as_i1imm $slc), (as_i1imm $tfe))
1433 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
1434 imm:$offset, 1, 1, imm:$glc, imm:$slc,
1436 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
1441 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
1442 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
1443 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
1444 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
1445 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
1446 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
1448 multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET,
1449 ValueType vt, PatFrag atomic_st> {
1450 // Store follows atomic op convention so address is forst
1452 (atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1453 i16:$offset, i1:$slc), vt:$val),
1454 (Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0)
1458 (atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val),
1459 (Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0)
1462 let SubtargetPredicate = isSICI in {
1463 defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, store_atomic_global>;
1464 defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, store_atomic_global>;
1465 } // End Predicates = isSICI
1468 multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
1472 (st vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1473 i16:$offset, i1:$glc, i1:$slc, i1:$tfe)),
1474 (Instr_OFFSET $vdata, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
1478 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_global>;
1479 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT_OFFSET, i16, store_global>;
1481 multiclass MUBUFScratchStorePat <MUBUF_Pseudo InstrOffen,
1482 MUBUF_Pseudo InstrOffset,
1483 ValueType vt, PatFrag st> {
1485 (st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
1486 i32:$soffset, u16imm:$offset)),
1487 (InstrOffen $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
1491 (st vt:$value, (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset,
1493 (InstrOffset $value, $srsrc, $soffset, $offset, 0, 0, 0)
1497 defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i32, truncstorei8_private>;
1498 defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i32, truncstorei16_private>;
1499 defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_private>;
1500 defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i16, store_private>;
1501 defm : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, BUFFER_STORE_DWORD_OFFSET, i32, store_private>;
1502 defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, BUFFER_STORE_DWORDX2_OFFSET, v2i32, store_private>;
1503 defm : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, BUFFER_STORE_DWORDX4_OFFSET, v4i32, store_private>;
1506 let OtherPredicates = [D16PreservesUnusedBits] in {
1507 // Hiding the extract high pattern in the PatFrag seems to not
1508 // automatically increase the complexity.
1509 let AddedComplexity = 1 in {
1510 defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_D16_HI_OFFEN, BUFFER_STORE_SHORT_D16_HI_OFFSET, i32, store_hi16_private>;
1511 defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_D16_HI_OFFEN, BUFFER_STORE_BYTE_D16_HI_OFFSET, i32, truncstorei8_hi16_private>;
1515 //===----------------------------------------------------------------------===//
1517 //===----------------------------------------------------------------------===//
1519 //===----------------------------------------------------------------------===//
1520 // tbuffer_load/store_format patterns
1521 //===----------------------------------------------------------------------===//
1523 multiclass MTBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
1526 (vt (name v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset,
1527 imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)),
1528 (!cast<MTBUF_Pseudo>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
1529 (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0)
1533 (vt (name v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset,
1534 imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)),
1535 (!cast<MTBUF_Pseudo>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
1536 (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0)
1540 (vt (name v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset,
1541 imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)),
1542 (!cast<MTBUF_Pseudo>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
1543 (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0)
1547 (vt (name v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset,
1548 imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)),
1549 (!cast<MTBUF_Pseudo>(opcode # _BOTHEN)
1550 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1551 $rsrc, $soffset, (as_i16imm $offset),
1552 (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0)
1556 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, i32, "TBUFFER_LOAD_FORMAT_X">;
1557 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2i32, "TBUFFER_LOAD_FORMAT_XY">;
1558 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4i32, "TBUFFER_LOAD_FORMAT_XYZW">;
1559 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, f32, "TBUFFER_LOAD_FORMAT_X">;
1560 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2f32, "TBUFFER_LOAD_FORMAT_XY">;
1561 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4f32, "TBUFFER_LOAD_FORMAT_XYZW">;
1563 let SubtargetPredicate = HasUnpackedD16VMem in {
1564 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, f16, "TBUFFER_LOAD_FORMAT_D16_X_gfx80">;
1565 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, v2i32, "TBUFFER_LOAD_FORMAT_D16_XY_gfx80">;
1566 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, v4i32, "TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80">;
1567 } // End HasUnpackedD16VMem.
1569 let SubtargetPredicate = HasPackedD16VMem in {
1570 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, f16, "TBUFFER_LOAD_FORMAT_D16_X">;
1571 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, v2f16, "TBUFFER_LOAD_FORMAT_D16_XY">;
1572 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, v4f16, "TBUFFER_LOAD_FORMAT_D16_XYZW">;
1573 } // End HasPackedD16VMem.
1575 multiclass MTBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
1578 (name vt:$vdata, v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset,
1579 imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc),
1580 (!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset,
1581 (as_i16imm $offset), (as_i8imm $dfmt),
1582 (as_i8imm $nfmt), (as_i1imm $glc),
1587 (name vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset,
1588 imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc),
1589 (!cast<MTBUF_Pseudo>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
1590 (as_i16imm $offset), (as_i8imm $dfmt),
1591 (as_i8imm $nfmt), (as_i1imm $glc),
1596 (name vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset,
1597 imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc),
1598 (!cast<MTBUF_Pseudo>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
1599 (as_i16imm $offset), (as_i8imm $dfmt),
1600 (as_i8imm $nfmt), (as_i1imm $glc),
1605 (name vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset,
1606 imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc),
1607 (!cast<MTBUF_Pseudo>(opcode # _BOTHEN_exact)
1609 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
1610 $rsrc, $soffset, (as_i16imm $offset),
1611 (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0)
1615 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, i32, "TBUFFER_STORE_FORMAT_X">;
1616 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2i32, "TBUFFER_STORE_FORMAT_XY">;
1617 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_x3, v4i32, "TBUFFER_STORE_FORMAT_XYZ">;
1618 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4i32, "TBUFFER_STORE_FORMAT_XYZW">;
1619 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, f32, "TBUFFER_STORE_FORMAT_X">;
1620 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2f32, "TBUFFER_STORE_FORMAT_XY">;
1621 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_x3, v4f32, "TBUFFER_STORE_FORMAT_XYZ">;
1622 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4f32, "TBUFFER_STORE_FORMAT_XYZW">;
1624 let SubtargetPredicate = HasUnpackedD16VMem in {
1625 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, f16, "TBUFFER_STORE_FORMAT_D16_X_gfx80">;
1626 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v2i32, "TBUFFER_STORE_FORMAT_D16_XY_gfx80">;
1627 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v4i32, "TBUFFER_STORE_FORMAT_D16_XYZW_gfx80">;
1628 } // End HasUnpackedD16VMem.
1630 let SubtargetPredicate = HasPackedD16VMem in {
1631 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, f16, "TBUFFER_STORE_FORMAT_D16_X">;
1632 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v2f16, "TBUFFER_STORE_FORMAT_D16_XY">;
1633 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v4f16, "TBUFFER_STORE_FORMAT_D16_XYZW">;
1634 } // End HasPackedD16VMem.
1636 //===----------------------------------------------------------------------===//
1637 // Target instructions, move to the appropriate target TD file
1638 //===----------------------------------------------------------------------===//
1640 //===----------------------------------------------------------------------===//
1642 //===----------------------------------------------------------------------===//
1644 class MUBUF_Real_si <bits<7> op, MUBUF_Pseudo ps> :
1647 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
1648 let AssemblerPredicate=isSICI;
1649 let DecoderNamespace="SICI";
1651 let Inst{11-0} = !if(ps.has_offset, offset, ?);
1652 let Inst{12} = ps.offen;
1653 let Inst{13} = ps.idxen;
1654 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
1655 let Inst{15} = ps.addr64;
1656 let Inst{16} = !if(ps.lds, 1, 0);
1657 let Inst{24-18} = op;
1658 let Inst{31-26} = 0x38; //encoding
1659 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
1660 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
1661 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
1662 let Inst{54} = !if(ps.has_slc, slc, ?);
1663 let Inst{55} = !if(ps.has_tfe, tfe, ?);
1664 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
1667 multiclass MUBUF_Real_AllAddr_si<bits<7> op> {
1668 def _OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
1669 def _ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>;
1670 def _OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
1671 def _IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
1672 def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
1675 multiclass MUBUF_Real_AllAddr_Lds_si<bits<7> op> {
1677 def _OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
1678 MUBUFLdsTable<0, NAME # "_OFFSET_si">;
1679 def _ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>,
1680 MUBUFLdsTable<0, NAME # "_ADDR64_si">;
1681 def _OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
1682 MUBUFLdsTable<0, NAME # "_OFFEN_si">;
1683 def _IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
1684 MUBUFLdsTable<0, NAME # "_IDXEN_si">;
1685 def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
1686 MUBUFLdsTable<0, NAME # "_BOTHEN_si">;
1688 def _LDS_OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
1689 MUBUFLdsTable<1, NAME # "_OFFSET_si">;
1690 def _LDS_ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_ADDR64")>,
1691 MUBUFLdsTable<1, NAME # "_ADDR64_si">;
1692 def _LDS_OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
1693 MUBUFLdsTable<1, NAME # "_OFFEN_si">;
1694 def _LDS_IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
1695 MUBUFLdsTable<1, NAME # "_IDXEN_si">;
1696 def _LDS_BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
1697 MUBUFLdsTable<1, NAME # "_BOTHEN_si">;
1700 multiclass MUBUF_Real_Atomic_si<bits<7> op> : MUBUF_Real_AllAddr_si<op> {
1701 def _OFFSET_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
1702 def _ADDR64_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64_RTN")>;
1703 def _OFFEN_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
1704 def _IDXEN_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
1705 def _BOTHEN_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
1708 defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_Lds_si <0x00>;
1709 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_si <0x01>;
1710 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x02>;
1711 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x03>;
1712 defm BUFFER_STORE_FORMAT_X : MUBUF_Real_AllAddr_si <0x04>;
1713 defm BUFFER_STORE_FORMAT_XY : MUBUF_Real_AllAddr_si <0x05>;
1714 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x06>;
1715 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x07>;
1716 defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_Lds_si <0x08>;
1717 defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_Lds_si <0x09>;
1718 defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_Lds_si <0x0a>;
1719 defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_Lds_si <0x0b>;
1720 defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_Lds_si <0x0c>;
1721 defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_si <0x0d>;
1722 defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_si <0x0e>;
1723 defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_si <0x0f>;
1724 defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_si <0x18>;
1725 defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_si <0x1a>;
1726 defm BUFFER_STORE_DWORD : MUBUF_Real_AllAddr_si <0x1c>;
1727 defm BUFFER_STORE_DWORDX2 : MUBUF_Real_AllAddr_si <0x1d>;
1728 defm BUFFER_STORE_DWORDX4 : MUBUF_Real_AllAddr_si <0x1e>;
1729 defm BUFFER_STORE_DWORDX3 : MUBUF_Real_AllAddr_si <0x1f>;
1731 defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_si <0x30>;
1732 defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_si <0x31>;
1733 defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_si <0x32>;
1734 defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomic_si <0x33>;
1735 //defm BUFFER_ATOMIC_RSUB : MUBUF_Real_Atomic_si <0x34>; // isn't on CI & VI
1736 defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomic_si <0x35>;
1737 defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomic_si <0x36>;
1738 defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomic_si <0x37>;
1739 defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomic_si <0x38>;
1740 defm BUFFER_ATOMIC_AND : MUBUF_Real_Atomic_si <0x39>;
1741 defm BUFFER_ATOMIC_OR : MUBUF_Real_Atomic_si <0x3a>;
1742 defm BUFFER_ATOMIC_XOR : MUBUF_Real_Atomic_si <0x3b>;
1743 defm BUFFER_ATOMIC_INC : MUBUF_Real_Atomic_si <0x3c>;
1744 defm BUFFER_ATOMIC_DEC : MUBUF_Real_Atomic_si <0x3d>;
1746 //defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Real_Atomic_si <0x3e>; // isn't on VI
1747 //defm BUFFER_ATOMIC_FMIN : MUBUF_Real_Atomic_si <0x3f>; // isn't on VI
1748 //defm BUFFER_ATOMIC_FMAX : MUBUF_Real_Atomic_si <0x40>; // isn't on VI
1749 defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Real_Atomic_si <0x50>;
1750 defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Real_Atomic_si <0x51>;
1751 defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Real_Atomic_si <0x52>;
1752 defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Real_Atomic_si <0x53>;
1753 //defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Real_Atomic_si <0x54>; // isn't on CI & VI
1754 defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Real_Atomic_si <0x55>;
1755 defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Real_Atomic_si <0x56>;
1756 defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Real_Atomic_si <0x57>;
1757 defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Real_Atomic_si <0x58>;
1758 defm BUFFER_ATOMIC_AND_X2 : MUBUF_Real_Atomic_si <0x59>;
1759 defm BUFFER_ATOMIC_OR_X2 : MUBUF_Real_Atomic_si <0x5a>;
1760 defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_si <0x5b>;
1761 defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_si <0x5c>;
1762 defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_si <0x5d>;
1763 // FIXME: Need to handle hazard for BUFFER_ATOMIC_FCMPSWAP_X2 on CI.
1764 //defm BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_Real_Atomic_si <0x5e">; // isn't on VI
1765 //defm BUFFER_ATOMIC_FMIN_X2 : MUBUF_Real_Atomic_si <0x5f>; // isn't on VI
1766 //defm BUFFER_ATOMIC_FMAX_X2 : MUBUF_Real_Atomic_si <0x60>; // isn't on VI
1768 def BUFFER_WBINVL1_SC_si : MUBUF_Real_si <0x70, BUFFER_WBINVL1_SC>;
1769 def BUFFER_WBINVL1_si : MUBUF_Real_si <0x71, BUFFER_WBINVL1>;
1771 class MTBUF_Real_si <bits<3> op, MTBUF_Pseudo ps> :
1774 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
1775 let AssemblerPredicate=isSICI;
1776 let DecoderNamespace="SICI";
1778 let Inst{11-0} = !if(ps.has_offset, offset, ?);
1779 let Inst{12} = ps.offen;
1780 let Inst{13} = ps.idxen;
1781 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
1782 let Inst{15} = ps.addr64;
1783 let Inst{18-16} = op;
1784 let Inst{22-19} = !if(ps.has_dfmt, dfmt, ps.dfmt_value);
1785 let Inst{25-23} = !if(ps.has_nfmt, nfmt, ps.nfmt_value);
1786 let Inst{31-26} = 0x3a; //encoding
1787 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
1788 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
1789 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
1790 let Inst{54} = !if(ps.has_slc, slc, ?);
1791 let Inst{55} = !if(ps.has_tfe, tfe, ?);
1792 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
1795 multiclass MTBUF_Real_AllAddr_si<bits<3> op> {
1796 def _OFFSET_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
1797 def _ADDR64_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_ADDR64")>;
1798 def _OFFEN_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
1799 def _IDXEN_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
1800 def _BOTHEN_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
1803 defm TBUFFER_LOAD_FORMAT_X : MTBUF_Real_AllAddr_si <0>;
1804 defm TBUFFER_LOAD_FORMAT_XY : MTBUF_Real_AllAddr_si <1>;
1805 defm TBUFFER_LOAD_FORMAT_XYZ : MTBUF_Real_AllAddr_si <2>;
1806 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Real_AllAddr_si <3>;
1807 defm TBUFFER_STORE_FORMAT_X : MTBUF_Real_AllAddr_si <4>;
1808 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Real_AllAddr_si <5>;
1809 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Real_AllAddr_si <6>;
1810 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_si <7>;
1812 //===----------------------------------------------------------------------===//
1814 //===----------------------------------------------------------------------===//
1816 class MUBUF_Real_ci <bits<7> op, MUBUF_Pseudo ps> :
1817 MUBUF_Real_si<op, ps> {
1818 let AssemblerPredicate=isCIOnly;
1819 let DecoderNamespace="CI";
1822 def BUFFER_WBINVL1_VOL_ci : MUBUF_Real_ci <0x70, BUFFER_WBINVL1_VOL>;
1825 //===----------------------------------------------------------------------===//
1827 //===----------------------------------------------------------------------===//
1829 class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> :
1832 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
1833 let AssemblerPredicate=isVI;
1834 let DecoderNamespace="VI";
1836 let Inst{11-0} = !if(ps.has_offset, offset, ?);
1837 let Inst{12} = ps.offen;
1838 let Inst{13} = ps.idxen;
1839 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
1840 let Inst{16} = !if(ps.lds, 1, 0);
1841 let Inst{17} = !if(ps.has_slc, slc, ?);
1842 let Inst{24-18} = op;
1843 let Inst{31-26} = 0x38; //encoding
1844 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
1845 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
1846 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
1847 let Inst{55} = !if(ps.has_tfe, tfe, ?);
1848 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
1851 multiclass MUBUF_Real_AllAddr_vi<bits<7> op> {
1852 def _OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
1853 def _OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
1854 def _IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
1855 def _BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
1858 multiclass MUBUF_Real_AllAddr_Lds_vi<bits<7> op> {
1860 def _OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
1861 MUBUFLdsTable<0, NAME # "_OFFSET_vi">;
1862 def _OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
1863 MUBUFLdsTable<0, NAME # "_OFFEN_vi">;
1864 def _IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
1865 MUBUFLdsTable<0, NAME # "_IDXEN_vi">;
1866 def _BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
1867 MUBUFLdsTable<0, NAME # "_BOTHEN_vi">;
1869 def _LDS_OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
1870 MUBUFLdsTable<1, NAME # "_OFFSET_vi">;
1871 def _LDS_OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
1872 MUBUFLdsTable<1, NAME # "_OFFEN_vi">;
1873 def _LDS_IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
1874 MUBUFLdsTable<1, NAME # "_IDXEN_vi">;
1875 def _LDS_BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
1876 MUBUFLdsTable<1, NAME # "_BOTHEN_vi">;
1879 class MUBUF_Real_gfx80 <bits<7> op, MUBUF_Pseudo ps> :
1882 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> {
1883 let AssemblerPredicate=HasUnpackedD16VMem;
1884 let DecoderNamespace="GFX80_UNPACKED";
1886 let Inst{11-0} = !if(ps.has_offset, offset, ?);
1887 let Inst{12} = ps.offen;
1888 let Inst{13} = ps.idxen;
1889 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
1890 let Inst{16} = !if(ps.lds, 1, 0);
1891 let Inst{17} = !if(ps.has_slc, slc, ?);
1892 let Inst{24-18} = op;
1893 let Inst{31-26} = 0x38; //encoding
1894 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
1895 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
1896 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
1897 let Inst{55} = !if(ps.has_tfe, tfe, ?);
1898 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
1901 multiclass MUBUF_Real_AllAddr_gfx80<bits<7> op> {
1902 def _OFFSET_gfx80 : MUBUF_Real_gfx80 <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
1903 def _OFFEN_gfx80 : MUBUF_Real_gfx80 <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
1904 def _IDXEN_gfx80 : MUBUF_Real_gfx80 <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
1905 def _BOTHEN_gfx80 : MUBUF_Real_gfx80 <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
1908 multiclass MUBUF_Real_Atomic_vi<bits<7> op> :
1909 MUBUF_Real_AllAddr_vi<op> {
1910 def _OFFSET_RTN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
1911 def _OFFEN_RTN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
1912 def _IDXEN_RTN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
1913 def _BOTHEN_RTN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
1916 defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_Lds_vi <0x00>;
1917 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_vi <0x01>;
1918 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_vi <0x02>;
1919 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_vi <0x03>;
1920 defm BUFFER_STORE_FORMAT_X : MUBUF_Real_AllAddr_vi <0x04>;
1921 defm BUFFER_STORE_FORMAT_XY : MUBUF_Real_AllAddr_vi <0x05>;
1922 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Real_AllAddr_vi <0x06>;
1923 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Real_AllAddr_vi <0x07>;
1924 let SubtargetPredicate = HasUnpackedD16VMem in {
1925 defm BUFFER_LOAD_FORMAT_D16_X_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x08>;
1926 defm BUFFER_LOAD_FORMAT_D16_XY_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x09>;
1927 defm BUFFER_LOAD_FORMAT_D16_XYZ_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x0a>;
1928 defm BUFFER_LOAD_FORMAT_D16_XYZW_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x0b>;
1929 defm BUFFER_STORE_FORMAT_D16_X_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x0c>;
1930 defm BUFFER_STORE_FORMAT_D16_XY_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x0d>;
1931 defm BUFFER_STORE_FORMAT_D16_XYZ_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x0e>;
1932 defm BUFFER_STORE_FORMAT_D16_XYZW_gfx80 : MUBUF_Real_AllAddr_gfx80 <0x0f>;
1933 } // End HasUnpackedD16VMem.
1934 let SubtargetPredicate = HasPackedD16VMem in {
1935 defm BUFFER_LOAD_FORMAT_D16_X : MUBUF_Real_AllAddr_vi <0x08>;
1936 defm BUFFER_LOAD_FORMAT_D16_XY : MUBUF_Real_AllAddr_vi <0x09>;
1937 defm BUFFER_LOAD_FORMAT_D16_XYZ : MUBUF_Real_AllAddr_vi <0x0a>;
1938 defm BUFFER_LOAD_FORMAT_D16_XYZW : MUBUF_Real_AllAddr_vi <0x0b>;
1939 defm BUFFER_STORE_FORMAT_D16_X : MUBUF_Real_AllAddr_vi <0x0c>;
1940 defm BUFFER_STORE_FORMAT_D16_XY : MUBUF_Real_AllAddr_vi <0x0d>;
1941 defm BUFFER_STORE_FORMAT_D16_XYZ : MUBUF_Real_AllAddr_vi <0x0e>;
1942 defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Real_AllAddr_vi <0x0f>;
1943 } // End HasPackedD16VMem.
1944 defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_Lds_vi <0x10>;
1945 defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_Lds_vi <0x11>;
1946 defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_Lds_vi <0x12>;
1947 defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_Lds_vi <0x13>;
1948 defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_Lds_vi <0x14>;
1949 defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_Lds_vi <0x15>;
1950 defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_Lds_vi <0x16>;
1951 defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_Lds_vi <0x17>;
1952 defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_vi <0x18>;
1953 defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x19>;
1954 defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_vi <0x1a>;
1955 defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Real_AllAddr_vi <0x1b>;
1956 defm BUFFER_STORE_DWORD : MUBUF_Real_AllAddr_vi <0x1c>;
1957 defm BUFFER_STORE_DWORDX2 : MUBUF_Real_AllAddr_vi <0x1d>;
1958 defm BUFFER_STORE_DWORDX3 : MUBUF_Real_AllAddr_vi <0x1e>;
1959 defm BUFFER_STORE_DWORDX4 : MUBUF_Real_AllAddr_vi <0x1f>;
1961 defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Real_AllAddr_vi <0x20>;
1962 defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x21>;
1963 defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Real_AllAddr_vi <0x22>;
1964 defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x23>;
1965 defm BUFFER_LOAD_SHORT_D16 : MUBUF_Real_AllAddr_vi <0x24>;
1966 defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Real_AllAddr_vi <0x25>;
1968 defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_vi <0x26>;
1969 defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_vi <0x27>;
1971 defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_vi <0x40>;
1972 defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_vi <0x41>;
1973 defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_vi <0x42>;
1974 defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomic_vi <0x43>;
1975 defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomic_vi <0x44>;
1976 defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomic_vi <0x45>;
1977 defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomic_vi <0x46>;
1978 defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomic_vi <0x47>;
1979 defm BUFFER_ATOMIC_AND : MUBUF_Real_Atomic_vi <0x48>;
1980 defm BUFFER_ATOMIC_OR : MUBUF_Real_Atomic_vi <0x49>;
1981 defm BUFFER_ATOMIC_XOR : MUBUF_Real_Atomic_vi <0x4a>;
1982 defm BUFFER_ATOMIC_INC : MUBUF_Real_Atomic_vi <0x4b>;
1983 defm BUFFER_ATOMIC_DEC : MUBUF_Real_Atomic_vi <0x4c>;
1985 defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Real_Atomic_vi <0x60>;
1986 defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Real_Atomic_vi <0x61>;
1987 defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Real_Atomic_vi <0x62>;
1988 defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Real_Atomic_vi <0x63>;
1989 defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Real_Atomic_vi <0x64>;
1990 defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Real_Atomic_vi <0x65>;
1991 defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Real_Atomic_vi <0x66>;
1992 defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Real_Atomic_vi <0x67>;
1993 defm BUFFER_ATOMIC_AND_X2 : MUBUF_Real_Atomic_vi <0x68>;
1994 defm BUFFER_ATOMIC_OR_X2 : MUBUF_Real_Atomic_vi <0x69>;
1995 defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_vi <0x6a>;
1996 defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_vi <0x6b>;
1997 defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_vi <0x6c>;
1999 def BUFFER_STORE_LDS_DWORD_vi : MUBUF_Real_vi <0x3d, BUFFER_STORE_LDS_DWORD>;
2001 def BUFFER_WBINVL1_vi : MUBUF_Real_vi <0x3e, BUFFER_WBINVL1>;
2002 def BUFFER_WBINVL1_VOL_vi : MUBUF_Real_vi <0x3f, BUFFER_WBINVL1_VOL>;
2004 class MTBUF_Real_vi <bits<4> op, MTBUF_Pseudo ps> :
2007 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
2008 let AssemblerPredicate=isVI;
2009 let DecoderNamespace="VI";
2011 let Inst{11-0} = !if(ps.has_offset, offset, ?);
2012 let Inst{12} = ps.offen;
2013 let Inst{13} = ps.idxen;
2014 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
2015 let Inst{18-15} = op;
2016 let Inst{22-19} = !if(ps.has_dfmt, dfmt, ps.dfmt_value);
2017 let Inst{25-23} = !if(ps.has_nfmt, nfmt, ps.nfmt_value);
2018 let Inst{31-26} = 0x3a; //encoding
2019 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
2020 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
2021 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
2022 let Inst{54} = !if(ps.has_slc, slc, ?);
2023 let Inst{55} = !if(ps.has_tfe, tfe, ?);
2024 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
2027 multiclass MTBUF_Real_AllAddr_vi<bits<4> op> {
2028 def _OFFSET_vi : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
2029 def _OFFEN_vi : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
2030 def _IDXEN_vi : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
2031 def _BOTHEN_vi : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
2034 class MTBUF_Real_gfx80 <bits<4> op, MTBUF_Pseudo ps> :
2037 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> {
2038 let AssemblerPredicate=HasUnpackedD16VMem;
2039 let DecoderNamespace="GFX80_UNPACKED";
2041 let Inst{11-0} = !if(ps.has_offset, offset, ?);
2042 let Inst{12} = ps.offen;
2043 let Inst{13} = ps.idxen;
2044 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
2045 let Inst{18-15} = op;
2046 let Inst{22-19} = !if(ps.has_dfmt, dfmt, ps.dfmt_value);
2047 let Inst{25-23} = !if(ps.has_nfmt, nfmt, ps.nfmt_value);
2048 let Inst{31-26} = 0x3a; //encoding
2049 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
2050 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
2051 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
2052 let Inst{54} = !if(ps.has_slc, slc, ?);
2053 let Inst{55} = !if(ps.has_tfe, tfe, ?);
2054 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
2057 multiclass MTBUF_Real_AllAddr_gfx80<bits<4> op> {
2058 def _OFFSET_gfx80 : MTBUF_Real_gfx80 <op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
2059 def _OFFEN_gfx80 : MTBUF_Real_gfx80 <op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
2060 def _IDXEN_gfx80 : MTBUF_Real_gfx80 <op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
2061 def _BOTHEN_gfx80 : MTBUF_Real_gfx80 <op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
2064 defm TBUFFER_LOAD_FORMAT_X : MTBUF_Real_AllAddr_vi <0x00>;
2065 defm TBUFFER_LOAD_FORMAT_XY : MTBUF_Real_AllAddr_vi <0x01>;
2066 defm TBUFFER_LOAD_FORMAT_XYZ : MTBUF_Real_AllAddr_vi <0x02>;
2067 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Real_AllAddr_vi <0x03>;
2068 defm TBUFFER_STORE_FORMAT_X : MTBUF_Real_AllAddr_vi <0x04>;
2069 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Real_AllAddr_vi <0x05>;
2070 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Real_AllAddr_vi <0x06>;
2071 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_vi <0x07>;
2072 let SubtargetPredicate = HasUnpackedD16VMem in {
2073 defm TBUFFER_LOAD_FORMAT_D16_X_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x08>;
2074 defm TBUFFER_LOAD_FORMAT_D16_XY_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x09>;
2075 defm TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x0a>;
2076 defm TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x0b>;
2077 defm TBUFFER_STORE_FORMAT_D16_X_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x0c>;
2078 defm TBUFFER_STORE_FORMAT_D16_XY_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x0d>;
2079 defm TBUFFER_STORE_FORMAT_D16_XYZ_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x0e>;
2080 defm TBUFFER_STORE_FORMAT_D16_XYZW_gfx80 : MTBUF_Real_AllAddr_gfx80 <0x0f>;
2081 } // End HasUnpackedD16VMem.
2082 let SubtargetPredicate = HasPackedD16VMem in {
2083 defm TBUFFER_LOAD_FORMAT_D16_X : MTBUF_Real_AllAddr_vi <0x08>;
2084 defm TBUFFER_LOAD_FORMAT_D16_XY : MTBUF_Real_AllAddr_vi <0x09>;
2085 defm TBUFFER_LOAD_FORMAT_D16_XYZ : MTBUF_Real_AllAddr_vi <0x0a>;
2086 defm TBUFFER_LOAD_FORMAT_D16_XYZW : MTBUF_Real_AllAddr_vi <0x0b>;
2087 defm TBUFFER_STORE_FORMAT_D16_X : MTBUF_Real_AllAddr_vi <0x0c>;
2088 defm TBUFFER_STORE_FORMAT_D16_XY : MTBUF_Real_AllAddr_vi <0x0d>;
2089 defm TBUFFER_STORE_FORMAT_D16_XYZ : MTBUF_Real_AllAddr_vi <0x0e>;
2090 defm TBUFFER_STORE_FORMAT_D16_XYZW : MTBUF_Real_AllAddr_vi <0x0f>;
2091 } // End HasUnpackedD16VMem.