1 //===-- BUFInstructions.td - Buffer Instruction Defintions ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
11 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
12 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
14 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
15 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
16 def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">;
17 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
18 def MUBUFIntrinsicOffset : ComplexPattern<i32, 2, "SelectMUBUFIntrinsicOffset">;
19 def MUBUFIntrinsicVOffset : ComplexPattern<i32, 3, "SelectMUBUFIntrinsicVOffset">;
21 class MubufLoad <SDPatternOperator op> : PatFrag <
22 (ops node:$ptr), (op node:$ptr), [{
23 auto const AS = cast<MemSDNode>(N)->getAddressSpace();
24 return AS == AMDGPUASI.GLOBAL_ADDRESS ||
25 AS == AMDGPUASI.CONSTANT_ADDRESS;
28 def mubuf_load : MubufLoad <load>;
29 def mubuf_az_extloadi8 : MubufLoad <az_extloadi8>;
30 def mubuf_sextloadi8 : MubufLoad <sextloadi8>;
31 def mubuf_az_extloadi16 : MubufLoad <az_extloadi16>;
32 def mubuf_sextloadi16 : MubufLoad <sextloadi16>;
33 def mubuf_load_atomic : MubufLoad <atomic_load>;
43 class getAddrName<int addrKind> {
45 !if(!eq(addrKind, BUFAddrKind.Offset), "offset",
46 !if(!eq(addrKind, BUFAddrKind.OffEn), "offen",
47 !if(!eq(addrKind, BUFAddrKind.IdxEn), "idxen",
48 !if(!eq(addrKind, BUFAddrKind.BothEn), "bothen",
49 !if(!eq(addrKind, BUFAddrKind.Addr64), "addr64",
53 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
54 bit IsAddr64 = is_addr64;
55 string OpName = NAME # suffix;
58 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//
62 class MTBUF_Pseudo <string opName, dag outs, dag ins,
63 string asmOps, list<dag> pattern=[]> :
64 InstSI<outs, ins, "", pattern>,
65 SIMCInstr<opName, SIEncodingFamily.NONE> {
68 let isCodeGenOnly = 1;
70 let UseNamedOperandTable = 1;
72 string Mnemonic = opName;
73 string AsmOperands = asmOps;
80 let hasSideEffects = 0;
81 let SchedRW = [WriteVMEM];
84 class MTBUF_Real <MTBUF_Pseudo ps> :
85 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
89 let isCodeGenOnly = 0;
91 // copy relevant pseudo op flags
92 let SubtargetPredicate = ps.SubtargetPredicate;
93 let AsmMatchConverter = ps.AsmMatchConverter;
94 let Constraints = ps.Constraints;
95 let DisableEncoding = ps.DisableEncoding;
96 let TSFlags = ps.TSFlags;
112 let Inst{11-0} = offset;
113 let Inst{12} = offen;
114 let Inst{13} = idxen;
116 let Inst{22-19} = dfmt;
117 let Inst{25-23} = nfmt;
118 let Inst{31-26} = 0x3a; //encoding
119 let Inst{39-32} = vaddr;
120 let Inst{47-40} = vdata;
121 let Inst{52-48} = srsrc{6-2};
124 let Inst{63-56} = soffset;
127 class MTBUF_Load_Pseudo <string opName, RegisterClass regClass> : MTBUF_Pseudo <
128 opName, (outs regClass:$dst),
129 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
130 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
131 i1imm:$slc, i1imm:$tfe, SCSrc_b32:$soffset),
132 " $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"#
133 " $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"> {
138 class MTBUF_Store_Pseudo <string opName, RegisterClass regClass> : MTBUF_Pseudo <
140 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
141 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
142 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_b32:$soffset),
143 " $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"#
144 " $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"> {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 class MUBUF_Pseudo <string opName, dag outs, dag ins,
154 string asmOps, list<dag> pattern=[]> :
155 InstSI<outs, ins, "", pattern>,
156 SIMCInstr<opName, SIEncodingFamily.NONE> {
159 let isCodeGenOnly = 1;
161 let UseNamedOperandTable = 1;
163 string Mnemonic = opName;
164 string AsmOperands = asmOps;
170 let hasSideEffects = 0;
171 let SchedRW = [WriteVMEM];
173 let AsmMatchConverter = "cvtMubuf";
178 bits<1> has_vdata = 1;
179 bits<1> has_vaddr = 1;
181 bits<1> glc_value = 0; // the value for glc if no such operand
182 bits<1> has_srsrc = 1;
183 bits<1> has_soffset = 1;
184 bits<1> has_offset = 1;
189 class MUBUF_Real <bits<7> op, MUBUF_Pseudo ps> :
190 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
193 let isCodeGenOnly = 0;
195 // copy relevant pseudo op flags
196 let SubtargetPredicate = ps.SubtargetPredicate;
197 let AsmMatchConverter = ps.AsmMatchConverter;
198 let Constraints = ps.Constraints;
199 let DisableEncoding = ps.DisableEncoding;
200 let TSFlags = ps.TSFlags;
214 // For cache invalidation instructions.
215 class MUBUF_Invalidate <string opName, SDPatternOperator node> :
216 MUBUF_Pseudo<opName, (outs), (ins), "", [(node)]> {
218 let AsmMatchConverter = "";
220 let hasSideEffects = 1;
223 // Set everything to 0.
238 class getMUBUFInsDA<list<RegisterClass> vdataList,
239 list<RegisterClass> vaddrList=[]> {
240 RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
241 RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
242 dag InsNoData = !if(!empty(vaddrList),
243 (ins SReg_128:$srsrc, SCSrc_b32:$soffset,
244 offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe),
245 (ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
246 offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe)
248 dag InsData = !if(!empty(vaddrList),
249 (ins vdataClass:$vdata, SReg_128:$srsrc,
250 SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe),
251 (ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
252 SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe)
254 dag ret = !if(!empty(vdataList), InsNoData, InsData);
257 class getMUBUFIns<int addrKind, list<RegisterClass> vdataList=[]> {
259 !if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList>.ret,
260 !if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPR_32]>.ret,
261 !if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPR_32]>.ret,
262 !if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64]>.ret,
263 !if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64]>.ret,
267 class getMUBUFAsmOps<int addrKind> {
269 !if(!eq(addrKind, BUFAddrKind.Offset), "off, $srsrc, $soffset",
270 !if(!eq(addrKind, BUFAddrKind.OffEn), "$vaddr, $srsrc, $soffset offen",
271 !if(!eq(addrKind, BUFAddrKind.IdxEn), "$vaddr, $srsrc, $soffset idxen",
272 !if(!eq(addrKind, BUFAddrKind.BothEn), "$vaddr, $srsrc, $soffset idxen offen",
273 !if(!eq(addrKind, BUFAddrKind.Addr64), "$vaddr, $srsrc, $soffset addr64",
275 string ret = Pfx # "$offset";
278 class MUBUF_SetupAddr<int addrKind> {
279 bits<1> offen = !if(!eq(addrKind, BUFAddrKind.OffEn), 1,
280 !if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));
282 bits<1> idxen = !if(!eq(addrKind, BUFAddrKind.IdxEn), 1,
283 !if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));
285 bits<1> addr64 = !if(!eq(addrKind, BUFAddrKind.Addr64), 1, 0);
287 bits<1> has_vaddr = !if(!eq(addrKind, BUFAddrKind.Offset), 0, 1);
290 class MUBUF_Load_Pseudo <string opName,
292 RegisterClass vdataClass,
293 list<dag> pattern=[],
294 // Workaround bug bz30254
295 int addrKindCopy = addrKind>
296 : MUBUF_Pseudo<opName,
297 (outs vdataClass:$vdata),
298 getMUBUFIns<addrKindCopy>.ret,
299 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
301 MUBUF_SetupAddr<addrKindCopy> {
302 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
307 // FIXME: tfe can't be an operand because it requires a separate
308 // opcode because it needs an N+1 register class dest register.
309 multiclass MUBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
310 ValueType load_vt = i32,
311 SDPatternOperator ld = null_frag> {
313 def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
314 [(set load_vt:$vdata,
315 (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))]>,
318 def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
319 [(set load_vt:$vdata,
320 (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))]>,
323 def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
324 def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
325 def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
327 let DisableWQM = 1 in {
328 def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
329 def _OFFEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
330 def _IDXEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
331 def _BOTHEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
335 class MUBUF_Store_Pseudo <string opName,
337 RegisterClass vdataClass,
338 list<dag> pattern=[],
339 // Workaround bug bz30254
340 int addrKindCopy = addrKind,
341 RegisterClass vdataClassCopy = vdataClass>
342 : MUBUF_Pseudo<opName,
344 getMUBUFIns<addrKindCopy, [vdataClassCopy]>.ret,
345 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
347 MUBUF_SetupAddr<addrKindCopy> {
348 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
353 multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
354 ValueType store_vt = i32,
355 SDPatternOperator st = null_frag> {
357 def _OFFSET : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
358 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
359 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
362 def _ADDR64 : MUBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
363 [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
364 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
367 def _OFFEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
368 def _IDXEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
369 def _BOTHEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
371 let DisableWQM = 1 in {
372 def _OFFSET_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
373 def _OFFEN_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
374 def _IDXEN_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
375 def _BOTHEN_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
380 class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in,
381 list<RegisterClass> vaddrList=[]> {
382 RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
383 dag ret = !if(vdata_in,
384 !if(!empty(vaddrList),
385 (ins vdataClass:$vdata_in,
386 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc),
387 (ins vdataClass:$vdata_in, vaddrClass:$vaddr,
388 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc)
390 !if(!empty(vaddrList),
391 (ins vdataClass:$vdata,
392 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc),
393 (ins vdataClass:$vdata, vaddrClass:$vaddr,
394 SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc)
398 class getMUBUFAtomicIns<int addrKind,
399 RegisterClass vdataClass,
401 // Workaround bug bz30254
402 RegisterClass vdataClassCopy=vdataClass> {
404 !if(!eq(addrKind, BUFAddrKind.Offset),
405 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in>.ret,
406 !if(!eq(addrKind, BUFAddrKind.OffEn),
407 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VGPR_32]>.ret,
408 !if(!eq(addrKind, BUFAddrKind.IdxEn),
409 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VGPR_32]>.ret,
410 !if(!eq(addrKind, BUFAddrKind.BothEn),
411 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VReg_64]>.ret,
412 !if(!eq(addrKind, BUFAddrKind.Addr64),
413 getMUBUFAtomicInsDA<vdataClassCopy, vdata_in, [VReg_64]>.ret,
417 class MUBUF_Atomic_Pseudo<string opName,
422 list<dag> pattern=[],
423 // Workaround bug bz30254
424 int addrKindCopy = addrKind>
425 : MUBUF_Pseudo<opName, outs, ins, asmOps, pattern>,
426 MUBUF_SetupAddr<addrKindCopy> {
429 let hasPostISelHook = 1;
430 let hasSideEffects = 1;
436 class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind,
437 RegisterClass vdataClass,
438 list<dag> pattern=[],
439 // Workaround bug bz30254
440 int addrKindCopy = addrKind,
441 RegisterClass vdataClassCopy = vdataClass>
442 : MUBUF_Atomic_Pseudo<opName, addrKindCopy,
444 getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 0>.ret,
445 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$slc",
447 AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 0> {
448 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
450 let AsmMatchConverter = "cvtMubufAtomic";
453 class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
454 RegisterClass vdataClass,
455 list<dag> pattern=[],
456 // Workaround bug bz30254
457 int addrKindCopy = addrKind,
458 RegisterClass vdataClassCopy = vdataClass>
459 : MUBUF_Atomic_Pseudo<opName, addrKindCopy,
460 (outs vdataClassCopy:$vdata),
461 getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 1>.ret,
462 " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # " glc$slc",
464 AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 1> {
465 let PseudoInstr = opName # "_rtn_" # getAddrName<addrKindCopy>.ret;
467 let Constraints = "$vdata = $vdata_in";
468 let DisableEncoding = "$vdata_in";
469 let AsmMatchConverter = "cvtMubufAtomicReturn";
472 multiclass MUBUF_Pseudo_Atomics <string opName,
473 RegisterClass vdataClass,
475 SDPatternOperator atomic> {
477 def _OFFSET : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass>,
478 MUBUFAddr64Table <0>;
479 def _ADDR64 : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass>,
480 MUBUFAddr64Table <1>;
481 def _OFFEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
482 def _IDXEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
483 def _BOTHEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
485 def _RTN_OFFSET : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
486 [(set vdataType:$vdata,
487 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$slc),
488 vdataType:$vdata_in))]>,
489 MUBUFAddr64Table <0, "_RTN">;
491 def _RTN_ADDR64 : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
492 [(set vdataType:$vdata,
493 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc),
494 vdataType:$vdata_in))]>,
495 MUBUFAddr64Table <1, "_RTN">;
497 def _RTN_OFFEN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
498 def _RTN_IDXEN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
499 def _RTN_BOTHEN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
503 //===----------------------------------------------------------------------===//
504 // MUBUF Instructions
505 //===----------------------------------------------------------------------===//
507 let SubtargetPredicate = isGCN in {
509 defm BUFFER_LOAD_FORMAT_X : MUBUF_Pseudo_Loads <
510 "buffer_load_format_x", VGPR_32
512 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Pseudo_Loads <
513 "buffer_load_format_xy", VReg_64
515 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Pseudo_Loads <
516 "buffer_load_format_xyz", VReg_96
518 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Pseudo_Loads <
519 "buffer_load_format_xyzw", VReg_128
521 defm BUFFER_STORE_FORMAT_X : MUBUF_Pseudo_Stores <
522 "buffer_store_format_x", VGPR_32
524 defm BUFFER_STORE_FORMAT_XY : MUBUF_Pseudo_Stores <
525 "buffer_store_format_xy", VReg_64
527 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Pseudo_Stores <
528 "buffer_store_format_xyz", VReg_96
530 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Pseudo_Stores <
531 "buffer_store_format_xyzw", VReg_128
533 defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads <
534 "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
536 defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads <
537 "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
539 defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads <
540 "buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16
542 defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads <
543 "buffer_load_sshort", VGPR_32, i32, mubuf_sextloadi16
545 defm BUFFER_LOAD_DWORD : MUBUF_Pseudo_Loads <
546 "buffer_load_dword", VGPR_32, i32, mubuf_load
548 defm BUFFER_LOAD_DWORDX2 : MUBUF_Pseudo_Loads <
549 "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load
551 defm BUFFER_LOAD_DWORDX3 : MUBUF_Pseudo_Loads <
552 "buffer_load_dwordx3", VReg_96, untyped, mubuf_load
554 defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads <
555 "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load
557 defm BUFFER_STORE_BYTE : MUBUF_Pseudo_Stores <
558 "buffer_store_byte", VGPR_32, i32, truncstorei8_global
560 defm BUFFER_STORE_SHORT : MUBUF_Pseudo_Stores <
561 "buffer_store_short", VGPR_32, i32, truncstorei16_global
563 defm BUFFER_STORE_DWORD : MUBUF_Pseudo_Stores <
564 "buffer_store_dword", VGPR_32, i32, global_store
566 defm BUFFER_STORE_DWORDX2 : MUBUF_Pseudo_Stores <
567 "buffer_store_dwordx2", VReg_64, v2i32, global_store
569 defm BUFFER_STORE_DWORDX3 : MUBUF_Pseudo_Stores <
570 "buffer_store_dwordx3", VReg_96, untyped, global_store
572 defm BUFFER_STORE_DWORDX4 : MUBUF_Pseudo_Stores <
573 "buffer_store_dwordx4", VReg_128, v4i32, global_store
575 defm BUFFER_ATOMIC_SWAP : MUBUF_Pseudo_Atomics <
576 "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
578 defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Pseudo_Atomics <
579 "buffer_atomic_cmpswap", VReg_64, v2i32, null_frag
581 defm BUFFER_ATOMIC_ADD : MUBUF_Pseudo_Atomics <
582 "buffer_atomic_add", VGPR_32, i32, atomic_add_global
584 defm BUFFER_ATOMIC_SUB : MUBUF_Pseudo_Atomics <
585 "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
587 defm BUFFER_ATOMIC_SMIN : MUBUF_Pseudo_Atomics <
588 "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
590 defm BUFFER_ATOMIC_UMIN : MUBUF_Pseudo_Atomics <
591 "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
593 defm BUFFER_ATOMIC_SMAX : MUBUF_Pseudo_Atomics <
594 "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
596 defm BUFFER_ATOMIC_UMAX : MUBUF_Pseudo_Atomics <
597 "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
599 defm BUFFER_ATOMIC_AND : MUBUF_Pseudo_Atomics <
600 "buffer_atomic_and", VGPR_32, i32, atomic_and_global
602 defm BUFFER_ATOMIC_OR : MUBUF_Pseudo_Atomics <
603 "buffer_atomic_or", VGPR_32, i32, atomic_or_global
605 defm BUFFER_ATOMIC_XOR : MUBUF_Pseudo_Atomics <
606 "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
608 defm BUFFER_ATOMIC_INC : MUBUF_Pseudo_Atomics <
609 "buffer_atomic_inc", VGPR_32, i32, atomic_inc_global
611 defm BUFFER_ATOMIC_DEC : MUBUF_Pseudo_Atomics <
612 "buffer_atomic_dec", VGPR_32, i32, atomic_dec_global
614 defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Pseudo_Atomics <
615 "buffer_atomic_swap_x2", VReg_64, i64, atomic_swap_global
617 defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Pseudo_Atomics <
618 "buffer_atomic_cmpswap_x2", VReg_128, v2i64, null_frag
620 defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Pseudo_Atomics <
621 "buffer_atomic_add_x2", VReg_64, i64, atomic_add_global
623 defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Pseudo_Atomics <
624 "buffer_atomic_sub_x2", VReg_64, i64, atomic_sub_global
626 defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Pseudo_Atomics <
627 "buffer_atomic_smin_x2", VReg_64, i64, atomic_min_global
629 defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Pseudo_Atomics <
630 "buffer_atomic_umin_x2", VReg_64, i64, atomic_umin_global
632 defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Pseudo_Atomics <
633 "buffer_atomic_smax_x2", VReg_64, i64, atomic_max_global
635 defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Pseudo_Atomics <
636 "buffer_atomic_umax_x2", VReg_64, i64, atomic_umax_global
638 defm BUFFER_ATOMIC_AND_X2 : MUBUF_Pseudo_Atomics <
639 "buffer_atomic_and_x2", VReg_64, i64, atomic_and_global
641 defm BUFFER_ATOMIC_OR_X2 : MUBUF_Pseudo_Atomics <
642 "buffer_atomic_or_x2", VReg_64, i64, atomic_or_global
644 defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Pseudo_Atomics <
645 "buffer_atomic_xor_x2", VReg_64, i64, atomic_xor_global
647 defm BUFFER_ATOMIC_INC_X2 : MUBUF_Pseudo_Atomics <
648 "buffer_atomic_inc_x2", VReg_64, i64, atomic_inc_global
650 defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Pseudo_Atomics <
651 "buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
654 let SubtargetPredicate = isSI in { // isn't on CI & VI
656 defm BUFFER_ATOMIC_RSUB : MUBUF_Pseudo_Atomics <"buffer_atomic_rsub">;
657 defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Pseudo_Atomics <"buffer_atomic_fcmpswap">;
658 defm BUFFER_ATOMIC_FMIN : MUBUF_Pseudo_Atomics <"buffer_atomic_fmin">;
659 defm BUFFER_ATOMIC_FMAX : MUBUF_Pseudo_Atomics <"buffer_atomic_fmax">;
660 defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_rsub_x2">;
661 defm BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_fcmpswap_x2">;
662 defm BUFFER_ATOMIC_FMIN_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_fmin_x2">;
663 defm BUFFER_ATOMIC_FMAX_X2 : MUBUF_Pseudo_Atomics <"buffer_atomic_fmax_x2">;
666 def BUFFER_WBINVL1_SC : MUBUF_Invalidate <"buffer_wbinvl1_sc",
667 int_amdgcn_buffer_wbinvl1_sc>;
670 def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1",
671 int_amdgcn_buffer_wbinvl1>;
673 //===----------------------------------------------------------------------===//
674 // MTBUF Instructions
675 //===----------------------------------------------------------------------===//
677 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0, "tbuffer_load_format_x", []>;
678 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <1, "tbuffer_load_format_xy", []>;
679 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <2, "tbuffer_load_format_xyz", []>;
680 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Pseudo <"tbuffer_load_format_xyzw", VReg_128>;
681 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Pseudo <"tbuffer_store_format_x", VGPR_32>;
682 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Pseudo <"tbuffer_store_format_xy", VReg_64>;
683 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Pseudo <"tbuffer_store_format_xyz", VReg_128>;
684 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Pseudo <"tbuffer_store_format_xyzw", VReg_128>;
686 } // End let SubtargetPredicate = isGCN
688 let SubtargetPredicate = isCIVI in {
690 //===----------------------------------------------------------------------===//
691 // Instruction definitions for CI and newer.
692 //===----------------------------------------------------------------------===//
693 // Remaining instructions:
694 // BUFFER_LOAD_DWORDX3
695 // BUFFER_STORE_DWORDX3
697 def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",
698 int_amdgcn_buffer_wbinvl1_vol>;
700 } // End let SubtargetPredicate = isCIVI
702 //===----------------------------------------------------------------------===//
704 //===----------------------------------------------------------------------===//
706 let Predicates = [isGCN] in {
708 // Offset in an 32-bit VGPR
710 (SIload_constant v4i32:$sbase, i32:$voff),
711 (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, (i32 0), 0, 0, 0, 0)
715 //===----------------------------------------------------------------------===//
716 // buffer_load/store_format patterns
717 //===----------------------------------------------------------------------===//
719 multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
722 (vt (name v4i32:$rsrc, 0,
723 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
724 imm:$glc, imm:$slc)),
725 (!cast<MUBUF_Pseudo>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
726 (as_i1imm $glc), (as_i1imm $slc), 0)
730 (vt (name v4i32:$rsrc, i32:$vindex,
731 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
732 imm:$glc, imm:$slc)),
733 (!cast<MUBUF_Pseudo>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
734 (as_i1imm $glc), (as_i1imm $slc), 0)
738 (vt (name v4i32:$rsrc, 0,
739 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
740 imm:$glc, imm:$slc)),
741 (!cast<MUBUF_Pseudo>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
742 (as_i1imm $glc), (as_i1imm $slc), 0)
746 (vt (name v4i32:$rsrc, i32:$vindex,
747 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
748 imm:$glc, imm:$slc)),
749 (!cast<MUBUF_Pseudo>(opcode # _BOTHEN)
750 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
751 $rsrc, $soffset, (as_i16imm $offset),
752 (as_i1imm $glc), (as_i1imm $slc), 0)
756 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">;
757 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
758 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
759 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, f32, "BUFFER_LOAD_DWORD">;
760 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
761 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
763 multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
766 (name vt:$vdata, v4i32:$rsrc, 0,
767 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
769 (!cast<MUBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (as_i16imm $offset),
770 (as_i1imm $glc), (as_i1imm $slc), 0)
774 (name vt:$vdata, v4i32:$rsrc, i32:$vindex,
775 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
777 (!cast<MUBUF_Pseudo>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
778 (as_i16imm $offset), (as_i1imm $glc),
783 (name vt:$vdata, v4i32:$rsrc, 0,
784 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
786 (!cast<MUBUF_Pseudo>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
787 (as_i16imm $offset), (as_i1imm $glc),
792 (name vt:$vdata, v4i32:$rsrc, i32:$vindex,
793 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
795 (!cast<MUBUF_Pseudo>(opcode # _BOTHEN_exact)
797 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
798 $rsrc, $soffset, (as_i16imm $offset),
799 (as_i1imm $glc), (as_i1imm $slc), 0)
803 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
804 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
805 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
806 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, f32, "BUFFER_STORE_DWORD">;
807 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
808 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
810 //===----------------------------------------------------------------------===//
811 // buffer_atomic patterns
812 //===----------------------------------------------------------------------===//
814 multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> {
816 (name i32:$vdata_in, v4i32:$rsrc, 0,
817 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
819 (!cast<MUBUF_Pseudo>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
820 (as_i16imm $offset), (as_i1imm $slc))
824 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
825 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
827 (!cast<MUBUF_Pseudo>(opcode # _RTN_IDXEN) $vdata_in, $vindex, $rsrc, $soffset,
828 (as_i16imm $offset), (as_i1imm $slc))
832 (name i32:$vdata_in, v4i32:$rsrc, 0,
833 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
835 (!cast<MUBUF_Pseudo>(opcode # _RTN_OFFEN) $vdata_in, $voffset, $rsrc, $soffset,
836 (as_i16imm $offset), (as_i1imm $slc))
840 (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex,
841 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
843 (!cast<MUBUF_Pseudo>(opcode # _RTN_BOTHEN)
845 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
846 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc))
850 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_swap, "BUFFER_ATOMIC_SWAP">;
851 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_add, "BUFFER_ATOMIC_ADD">;
852 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_sub, "BUFFER_ATOMIC_SUB">;
853 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smin, "BUFFER_ATOMIC_SMIN">;
854 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umin, "BUFFER_ATOMIC_UMIN">;
855 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_smax, "BUFFER_ATOMIC_SMAX">;
856 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_umax, "BUFFER_ATOMIC_UMAX">;
857 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_and, "BUFFER_ATOMIC_AND">;
858 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_or, "BUFFER_ATOMIC_OR">;
859 defm : BufferAtomicPatterns<int_amdgcn_buffer_atomic_xor, "BUFFER_ATOMIC_XOR">;
862 (int_amdgcn_buffer_atomic_cmpswap
863 i32:$data, i32:$cmp, v4i32:$rsrc, 0,
864 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
867 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET
868 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
869 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
874 (int_amdgcn_buffer_atomic_cmpswap
875 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
876 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
879 (BUFFER_ATOMIC_CMPSWAP_RTN_IDXEN
880 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
881 $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
886 (int_amdgcn_buffer_atomic_cmpswap
887 i32:$data, i32:$cmp, v4i32:$rsrc, 0,
888 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
891 (BUFFER_ATOMIC_CMPSWAP_RTN_OFFEN
892 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
893 $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
898 (int_amdgcn_buffer_atomic_cmpswap
899 i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex,
900 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
903 (BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN
904 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
905 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
906 $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
911 class MUBUFLoad_PatternADDR64 <MUBUF_Pseudo Instr_ADDR64, ValueType vt,
912 PatFrag constant_ld> : Pat <
913 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
914 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
915 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
918 multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET,
919 ValueType vt, PatFrag atomic_ld> {
921 (vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
922 i16:$offset, i1:$slc))),
923 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
927 (vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))),
928 (Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
932 let Predicates = [isSICI] in {
933 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
934 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
935 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
936 def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
938 defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
939 defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
940 } // End Predicates = [isSICI]
942 multiclass MUBUFLoad_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
946 (vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset,
947 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
948 (Instr_OFFSET $srsrc, $soffset, $offset, $glc, $slc, $tfe)
952 let Predicates = [Has16BitInsts] in {
954 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_constant>;
955 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_constant>;
956 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, mubuf_sextloadi8>;
957 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, mubuf_az_extloadi8>;
959 } // End Predicates = [Has16BitInsts]
961 class MUBUFScratchLoadPat <MUBUF_Pseudo Instr, ValueType vt, PatFrag ld> : Pat <
962 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
963 i32:$soffset, u16imm:$offset))),
964 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
967 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
968 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
969 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i16, sextloadi8_private>;
970 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i16, extloadi8_private>;
971 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
972 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
973 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
974 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
975 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
977 // BUFFER_LOAD_DWORD*, addr64=0
978 multiclass MUBUF_Load_Dword <ValueType vt,
982 MUBUF_Pseudo bothen> {
985 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
986 imm:$offset, 0, 0, imm:$glc, imm:$slc,
988 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
989 (as_i1imm $slc), (as_i1imm $tfe))
993 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
994 imm:$offset, 1, 0, imm:$glc, imm:$slc,
996 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
1001 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
1002 imm:$offset, 0, 1, imm:$glc, imm:$slc,
1004 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
1005 (as_i1imm $slc), (as_i1imm $tfe))
1009 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
1010 imm:$offset, 1, 1, imm:$glc, imm:$slc,
1012 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
1017 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
1018 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
1019 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
1020 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
1021 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
1022 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
1024 multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET,
1025 ValueType vt, PatFrag atomic_st> {
1026 // Store follows atomic op convention so address is forst
1028 (atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1029 i16:$offset, i1:$slc), vt:$val),
1030 (Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 1, $slc, 0)
1034 (atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val),
1035 (Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 1, 0, 0)
1038 let Predicates = [isSICI] in {
1039 defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, global_store_atomic>;
1040 defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, global_store_atomic>;
1041 } // End Predicates = [isSICI]
1044 multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
1048 (st vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1049 i16:$offset, i1:$glc, i1:$slc, i1:$tfe)),
1050 (Instr_OFFSET $vdata, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
1054 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_global>;
1055 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT_OFFSET, i16, global_store>;
1057 class MUBUFScratchStorePat <MUBUF_Pseudo Instr, ValueType vt, PatFrag st> : Pat <
1058 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
1060 (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
1063 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
1064 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
1065 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i16, truncstorei8_private>;
1066 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i16, store_private>;
1067 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
1068 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
1069 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
1071 //===----------------------------------------------------------------------===//
1073 //===----------------------------------------------------------------------===//
1075 // TBUFFER_STORE_FORMAT_*, addr64=0
1076 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF_Pseudo opcode> : Pat<
1077 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
1078 i32:$soffset, imm:$inst_offset, imm:$dfmt,
1079 imm:$nfmt, imm:$offen, imm:$idxen,
1080 imm:$glc, imm:$slc, imm:$tfe),
1082 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
1083 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
1084 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
1087 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
1088 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
1089 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
1090 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
1092 } // End let Predicates = [isGCN]
1094 //===----------------------------------------------------------------------===//
1095 // Target instructions, move to the appropriate target TD file
1096 //===----------------------------------------------------------------------===//
1098 //===----------------------------------------------------------------------===//
1100 //===----------------------------------------------------------------------===//
1102 class MUBUF_Real_si <bits<7> op, MUBUF_Pseudo ps> :
1105 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
1106 let AssemblerPredicate=isSICI;
1107 let DecoderNamespace="SICI";
1109 let Inst{11-0} = !if(ps.has_offset, offset, ?);
1110 let Inst{12} = ps.offen;
1111 let Inst{13} = ps.idxen;
1112 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
1113 let Inst{15} = ps.addr64;
1115 let Inst{24-18} = op;
1116 let Inst{31-26} = 0x38; //encoding
1117 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
1118 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
1119 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
1120 let Inst{54} = !if(ps.has_slc, slc, ?);
1121 let Inst{55} = !if(ps.has_tfe, tfe, ?);
1122 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
1125 multiclass MUBUF_Real_AllAddr_si<bits<7> op> {
1126 def _OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
1127 def _ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>;
1128 def _OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
1129 def _IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
1130 def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
1133 multiclass MUBUF_Real_Atomic_si<bits<7> op> : MUBUF_Real_AllAddr_si<op> {
1134 def _RTN_OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_OFFSET")>;
1135 def _RTN_ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_ADDR64")>;
1136 def _RTN_OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_OFFEN")>;
1137 def _RTN_IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_IDXEN")>;
1138 def _RTN_BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_BOTHEN")>;
1141 defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_si <0x00>;
1142 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_si <0x01>;
1143 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x02>;
1144 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x03>;
1145 defm BUFFER_STORE_FORMAT_X : MUBUF_Real_AllAddr_si <0x04>;
1146 defm BUFFER_STORE_FORMAT_XY : MUBUF_Real_AllAddr_si <0x05>;
1147 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x06>;
1148 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x07>;
1149 defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_si <0x08>;
1150 defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_si <0x09>;
1151 defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_si <0x0a>;
1152 defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_si <0x0b>;
1153 defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_si <0x0c>;
1154 defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_si <0x0d>;
1155 defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_si <0x0e>;
1156 defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_si <0x0f>;
1157 defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_si <0x18>;
1158 defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_si <0x1a>;
1159 defm BUFFER_STORE_DWORD : MUBUF_Real_AllAddr_si <0x1c>;
1160 defm BUFFER_STORE_DWORDX2 : MUBUF_Real_AllAddr_si <0x1d>;
1161 defm BUFFER_STORE_DWORDX4 : MUBUF_Real_AllAddr_si <0x1e>;
1162 defm BUFFER_STORE_DWORDX3 : MUBUF_Real_AllAddr_si <0x1f>;
1164 defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_si <0x30>;
1165 defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_si <0x31>;
1166 defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_si <0x32>;
1167 defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomic_si <0x33>;
1168 //defm BUFFER_ATOMIC_RSUB : MUBUF_Real_Atomic_si <0x34>; // isn't on CI & VI
1169 defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomic_si <0x35>;
1170 defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomic_si <0x36>;
1171 defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomic_si <0x37>;
1172 defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomic_si <0x38>;
1173 defm BUFFER_ATOMIC_AND : MUBUF_Real_Atomic_si <0x39>;
1174 defm BUFFER_ATOMIC_OR : MUBUF_Real_Atomic_si <0x3a>;
1175 defm BUFFER_ATOMIC_XOR : MUBUF_Real_Atomic_si <0x3b>;
1176 defm BUFFER_ATOMIC_INC : MUBUF_Real_Atomic_si <0x3c>;
1177 defm BUFFER_ATOMIC_DEC : MUBUF_Real_Atomic_si <0x3d>;
1179 //defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Real_Atomic_si <0x3e>; // isn't on VI
1180 //defm BUFFER_ATOMIC_FMIN : MUBUF_Real_Atomic_si <0x3f>; // isn't on VI
1181 //defm BUFFER_ATOMIC_FMAX : MUBUF_Real_Atomic_si <0x40>; // isn't on VI
1182 defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Real_Atomic_si <0x50>;
1183 defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Real_Atomic_si <0x51>;
1184 defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Real_Atomic_si <0x52>;
1185 defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Real_Atomic_si <0x53>;
1186 //defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Real_Atomic_si <0x54>; // isn't on CI & VI
1187 defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Real_Atomic_si <0x55>;
1188 defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Real_Atomic_si <0x56>;
1189 defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Real_Atomic_si <0x57>;
1190 defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Real_Atomic_si <0x58>;
1191 defm BUFFER_ATOMIC_AND_X2 : MUBUF_Real_Atomic_si <0x59>;
1192 defm BUFFER_ATOMIC_OR_X2 : MUBUF_Real_Atomic_si <0x5a>;
1193 defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_si <0x5b>;
1194 defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_si <0x5c>;
1195 defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_si <0x5d>;
1196 // FIXME: Need to handle hazard for BUFFER_ATOMIC_FCMPSWAP_X2 on CI.
1197 //defm BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_Real_Atomic_si <0x5e">; // isn't on VI
1198 //defm BUFFER_ATOMIC_FMIN_X2 : MUBUF_Real_Atomic_si <0x5f>; // isn't on VI
1199 //defm BUFFER_ATOMIC_FMAX_X2 : MUBUF_Real_Atomic_si <0x60>; // isn't on VI
1201 def BUFFER_WBINVL1_SC_si : MUBUF_Real_si <0x70, BUFFER_WBINVL1_SC>;
1202 def BUFFER_WBINVL1_si : MUBUF_Real_si <0x71, BUFFER_WBINVL1>;
1204 class MTBUF_Real_si <bits<3> op, MTBUF_Pseudo ps> :
1206 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
1207 let AssemblerPredicate=isSICI;
1208 let DecoderNamespace="SICI";
1211 let Inst{15} = addr64;
1212 let Inst{18-16} = op;
1215 def TBUFFER_LOAD_FORMAT_XYZW_si : MTBUF_Real_si <3, TBUFFER_LOAD_FORMAT_XYZW>;
1216 def TBUFFER_STORE_FORMAT_X_si : MTBUF_Real_si <4, TBUFFER_STORE_FORMAT_X>;
1217 def TBUFFER_STORE_FORMAT_XY_si : MTBUF_Real_si <5, TBUFFER_STORE_FORMAT_XY>;
1218 def TBUFFER_STORE_FORMAT_XYZ_si : MTBUF_Real_si <6, TBUFFER_STORE_FORMAT_XYZ>;
1219 def TBUFFER_STORE_FORMAT_XYZW_si : MTBUF_Real_si <7, TBUFFER_STORE_FORMAT_XYZW>;
1222 //===----------------------------------------------------------------------===//
1224 //===----------------------------------------------------------------------===//
1226 class MUBUF_Real_ci <bits<7> op, MUBUF_Pseudo ps> :
1227 MUBUF_Real_si<op, ps> {
1228 let AssemblerPredicate=isCIOnly;
1229 let DecoderNamespace="CI";
1232 def BUFFER_WBINVL1_VOL_ci : MUBUF_Real_ci <0x70, BUFFER_WBINVL1_VOL>;
1235 //===----------------------------------------------------------------------===//
1237 //===----------------------------------------------------------------------===//
1239 class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> :
1242 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
1243 let AssemblerPredicate=isVI;
1244 let DecoderNamespace="VI";
1246 let Inst{11-0} = !if(ps.has_offset, offset, ?);
1247 let Inst{12} = ps.offen;
1248 let Inst{13} = ps.idxen;
1249 let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
1251 let Inst{17} = !if(ps.has_slc, slc, ?);
1252 let Inst{24-18} = op;
1253 let Inst{31-26} = 0x38; //encoding
1254 let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
1255 let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
1256 let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
1257 let Inst{55} = !if(ps.has_tfe, tfe, ?);
1258 let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
1261 multiclass MUBUF_Real_AllAddr_vi<bits<7> op> {
1262 def _OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
1263 def _OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
1264 def _IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
1265 def _BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
1268 multiclass MUBUF_Real_Atomic_vi<bits<7> op> :
1269 MUBUF_Real_AllAddr_vi<op> {
1270 def _RTN_OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_OFFSET")>;
1271 def _RTN_OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_OFFEN")>;
1272 def _RTN_IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_IDXEN")>;
1273 def _RTN_BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_RTN_BOTHEN")>;
1276 defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_vi <0x00>;
1277 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_vi <0x01>;
1278 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_vi <0x02>;
1279 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_vi <0x03>;
1280 defm BUFFER_STORE_FORMAT_X : MUBUF_Real_AllAddr_vi <0x04>;
1281 defm BUFFER_STORE_FORMAT_XY : MUBUF_Real_AllAddr_vi <0x05>;
1282 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Real_AllAddr_vi <0x06>;
1283 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Real_AllAddr_vi <0x07>;
1284 defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_vi <0x10>;
1285 defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_vi <0x11>;
1286 defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_vi <0x12>;
1287 defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_vi <0x13>;
1288 defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_vi <0x14>;
1289 defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_vi <0x15>;
1290 defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_vi <0x16>;
1291 defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_vi <0x17>;
1292 defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_vi <0x18>;
1293 defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_vi <0x1a>;
1294 defm BUFFER_STORE_DWORD : MUBUF_Real_AllAddr_vi <0x1c>;
1295 defm BUFFER_STORE_DWORDX2 : MUBUF_Real_AllAddr_vi <0x1d>;
1296 defm BUFFER_STORE_DWORDX3 : MUBUF_Real_AllAddr_vi <0x1e>;
1297 defm BUFFER_STORE_DWORDX4 : MUBUF_Real_AllAddr_vi <0x1f>;
1299 defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_vi <0x40>;
1300 defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_vi <0x41>;
1301 defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_vi <0x42>;
1302 defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomic_vi <0x43>;
1303 defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomic_vi <0x44>;
1304 defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomic_vi <0x45>;
1305 defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomic_vi <0x46>;
1306 defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomic_vi <0x47>;
1307 defm BUFFER_ATOMIC_AND : MUBUF_Real_Atomic_vi <0x48>;
1308 defm BUFFER_ATOMIC_OR : MUBUF_Real_Atomic_vi <0x49>;
1309 defm BUFFER_ATOMIC_XOR : MUBUF_Real_Atomic_vi <0x4a>;
1310 defm BUFFER_ATOMIC_INC : MUBUF_Real_Atomic_vi <0x4b>;
1311 defm BUFFER_ATOMIC_DEC : MUBUF_Real_Atomic_vi <0x4c>;
1313 defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Real_Atomic_vi <0x60>;
1314 defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Real_Atomic_vi <0x61>;
1315 defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Real_Atomic_vi <0x62>;
1316 defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Real_Atomic_vi <0x63>;
1317 defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Real_Atomic_vi <0x64>;
1318 defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Real_Atomic_vi <0x65>;
1319 defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Real_Atomic_vi <0x66>;
1320 defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Real_Atomic_vi <0x67>;
1321 defm BUFFER_ATOMIC_AND_X2 : MUBUF_Real_Atomic_vi <0x68>;
1322 defm BUFFER_ATOMIC_OR_X2 : MUBUF_Real_Atomic_vi <0x69>;
1323 defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_vi <0x6a>;
1324 defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_vi <0x6b>;
1325 defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_vi <0x6c>;
1327 def BUFFER_WBINVL1_vi : MUBUF_Real_vi <0x3e, BUFFER_WBINVL1>;
1328 def BUFFER_WBINVL1_VOL_vi : MUBUF_Real_vi <0x3f, BUFFER_WBINVL1_VOL>;
1330 class MTBUF_Real_vi <bits<4> op, MTBUF_Pseudo ps> :
1332 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
1333 let AssemblerPredicate=isVI;
1334 let DecoderNamespace="VI";
1336 let Inst{18-15} = op;
1339 def TBUFFER_LOAD_FORMAT_XYZW_vi : MTBUF_Real_vi <3, TBUFFER_LOAD_FORMAT_XYZW>;
1340 def TBUFFER_STORE_FORMAT_X_vi : MTBUF_Real_vi <4, TBUFFER_STORE_FORMAT_X>;
1341 def TBUFFER_STORE_FORMAT_XY_vi : MTBUF_Real_vi <5, TBUFFER_STORE_FORMAT_XY>;
1342 def TBUFFER_STORE_FORMAT_XYZ_vi : MTBUF_Real_vi <6, TBUFFER_STORE_FORMAT_XYZ>;
1343 def TBUFFER_STORE_FORMAT_XYZW_vi : MTBUF_Real_vi <7, TBUFFER_STORE_FORMAT_XYZW>;