1 //===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
14 let SubtargetPredicate = isGCN;
19 let UseNamedOperandTable = 1;
20 let Uses = [M0, EXEC];
22 // Most instruction load and store data, so set this as the default.
26 let hasSideEffects = 0;
27 let SchedRW = [WriteLDS];
30 let isCodeGenOnly = 1;
32 let AsmMatchConverter = "cvtDS";
34 string Mnemonic = opName;
35 string AsmOperands = asmOps;
37 // Well these bits a kind of hack because it would be more natural
38 // to test "outs" and "ins" dags for the presence of particular operands
41 bits<1> has_data0 = 1;
42 bits<1> has_data1 = 1;
44 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
45 bits<1> has_offset0 = 1;
46 bits<1> has_offset1 = 1;
49 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
52 class DS_Real <DS_Pseudo ds> :
53 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
57 let isCodeGenOnly = 0;
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ds.SubtargetPredicate;
61 let AsmMatchConverter = ds.AsmMatchConverter;
73 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
78 // DS Pseudo instructions
80 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
83 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84 "$addr, $data0$offset$gds">,
85 AtomicNoRet<opName, 0> {
91 class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
94 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
95 "$addr, $data0, $data1"#"$offset"#"$gds">,
96 AtomicNoRet<opName, 0> {
101 class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
104 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
105 offset0:$offset0, offset1:$offset1, gds:$gds),
106 "$addr, $data0, $data1$offset0$offset1$gds"> {
110 let AsmMatchConverter = "cvtDSOffset01";
113 class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
116 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
117 "$vdst, $addr, $data0$offset$gds"> {
119 let hasPostISelHook = 1;
123 class DS_1A2D_RET<string opName,
124 RegisterClass rc = VGPR_32,
125 RegisterClass src = rc>
128 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
129 "$vdst, $addr, $data0, $data1$offset$gds"> {
131 let hasPostISelHook = 1;
134 class DS_1A2D_Off8_RET<string opName,
135 RegisterClass rc = VGPR_32,
136 RegisterClass src = rc>
139 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
140 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
143 let AsmMatchConverter = "cvtDSOffset01";
145 let hasPostISelHook = 1;
148 class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
151 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
152 "$vdst, $addr$offset$gds"> {
158 class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
161 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
162 "$vdst, $addr$offset0$offset1$gds"> {
167 let AsmMatchConverter = "cvtDSOffset01";
170 class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
171 (outs VGPR_32:$vdst),
172 (ins VGPR_32:$addr, offset:$offset),
173 "$vdst, $addr$offset gds"> {
179 let AsmMatchConverter = "cvtDSGds";
182 class DS_0A_RET <string opName> : DS_Pseudo<opName,
183 (outs VGPR_32:$vdst),
184 (ins offset:$offset, gds:$gds),
185 "$vdst$offset$gds"> {
195 class DS_1A <string opName> : DS_Pseudo<opName,
197 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
198 "$addr$offset$gds"> {
208 class DS_GWS <string opName, dag ins, string asmOps>
209 : DS_Pseudo<opName, (outs), ins, asmOps> {
218 let AsmMatchConverter = "cvtDSGds";
221 class DS_GWS_0D <string opName>
223 (ins offset:$offset, gds:$gds), "$offset gds">;
225 class DS_GWS_1D <string opName>
227 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
232 class DS_VOID <string opName> : DS_Pseudo<opName,
236 let hasSideEffects = 1;
237 let UseNamedOperandTable = 0;
238 let AsmMatchConverter = "";
250 class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
252 (outs VGPR_32:$vdst),
253 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
254 "$vdst, $addr, $data0$offset",
256 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
260 let isConvergent = 1;
266 def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
267 def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
268 def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
269 def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
270 def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
271 def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
272 def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
273 def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
274 def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
275 def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
276 def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
277 def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
278 def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
279 def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
280 def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
283 def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
284 def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
285 def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
286 def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
287 def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
290 def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
291 def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
292 def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
294 def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
295 def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
296 def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
297 def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
298 def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
299 def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
300 def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
301 def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
302 def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
303 def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
304 def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
305 def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
306 def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
308 def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
309 def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
310 def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
312 def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
313 def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
314 def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
315 def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
317 def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
318 AtomicNoRet<"ds_add_u32", 1>;
319 def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
320 AtomicNoRet<"ds_add_f32", 1>;
321 def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
322 AtomicNoRet<"ds_sub_u32", 1>;
323 def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
324 AtomicNoRet<"ds_rsub_u32", 1>;
325 def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
326 AtomicNoRet<"ds_inc_u32", 1>;
327 def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
328 AtomicNoRet<"ds_dec_u32", 1>;
329 def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
330 AtomicNoRet<"ds_min_i32", 1>;
331 def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
332 AtomicNoRet<"ds_max_i32", 1>;
333 def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
334 AtomicNoRet<"ds_min_u32", 1>;
335 def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
336 AtomicNoRet<"ds_max_u32", 1>;
337 def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
338 AtomicNoRet<"ds_and_b32", 1>;
339 def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
340 AtomicNoRet<"ds_or_b32", 1>;
341 def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
342 AtomicNoRet<"ds_xor_b32", 1>;
343 def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
344 AtomicNoRet<"ds_mskor_b32", 1>;
345 def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
346 AtomicNoRet<"ds_cmpst_b32", 1>;
347 def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
348 AtomicNoRet<"ds_cmpst_f32", 1>;
349 def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
350 AtomicNoRet<"ds_min_f32", 1>;
351 def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
352 AtomicNoRet<"ds_max_f32", 1>;
354 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
356 def DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
358 def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
361 def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
362 AtomicNoRet<"ds_add_u64", 1>;
363 def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
364 AtomicNoRet<"ds_sub_u64", 1>;
365 def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
366 AtomicNoRet<"ds_rsub_u64", 1>;
367 def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
368 AtomicNoRet<"ds_inc_u64", 1>;
369 def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
370 AtomicNoRet<"ds_dec_u64", 1>;
371 def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
372 AtomicNoRet<"ds_min_i64", 1>;
373 def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
374 AtomicNoRet<"ds_max_i64", 1>;
375 def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
376 AtomicNoRet<"ds_min_u64", 1>;
377 def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
378 AtomicNoRet<"ds_max_u64", 1>;
379 def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
380 AtomicNoRet<"ds_and_b64", 1>;
381 def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
382 AtomicNoRet<"ds_or_b64", 1>;
383 def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
384 AtomicNoRet<"ds_xor_b64", 1>;
385 def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
386 AtomicNoRet<"ds_mskor_b64", 1>;
387 def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
388 AtomicNoRet<"ds_cmpst_b64", 1>;
389 def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
390 AtomicNoRet<"ds_cmpst_f64", 1>;
391 def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
392 AtomicNoRet<"ds_min_f64", 1>;
393 def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
394 AtomicNoRet<"ds_max_f64", 1>;
396 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
398 def DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
400 def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
403 def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
404 def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
405 def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
406 def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
407 def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
409 def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
410 def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
411 def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
412 def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
413 def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
414 def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
415 def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
416 def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
417 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
418 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
419 def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
420 def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
421 def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
422 def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
424 def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
425 def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
426 def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
427 def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
428 def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
429 def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
430 def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
431 def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
432 def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
433 def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
434 def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
435 def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
436 def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
437 def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
439 def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
440 def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
442 let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
443 def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
446 let mayStore = 0 in {
447 def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
448 def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
449 def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
450 def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
451 def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
452 def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
454 def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
455 def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
457 def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
458 def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
461 def DS_CONSUME : DS_0A_RET<"ds_consume">;
462 def DS_APPEND : DS_0A_RET<"ds_append">;
463 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
465 //===----------------------------------------------------------------------===//
466 // Instruction definitions for CI and newer.
467 //===----------------------------------------------------------------------===//
469 let SubtargetPredicate = isCIVI in {
471 def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
473 def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
476 def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
478 let mayStore = 0 in {
479 def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
480 def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>;
481 } // End mayStore = 0
484 def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>;
485 def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>;
488 def DS_NOP : DS_VOID<"ds_nop">;
490 } // let SubtargetPredicate = isCIVI
492 //===----------------------------------------------------------------------===//
493 // Instruction definitions for VI and newer.
494 //===----------------------------------------------------------------------===//
496 let SubtargetPredicate = isVI in {
498 let Uses = [EXEC] in {
499 def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
500 int_amdgcn_ds_permute>;
501 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
502 int_amdgcn_ds_bpermute>;
505 } // let SubtargetPredicate = isVI
507 //===----------------------------------------------------------------------===//
509 //===----------------------------------------------------------------------===//
511 let Predicates = [isGCN] in {
514 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
515 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
518 class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
519 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
520 (inst $ptr, (as_i16imm $offset), (i1 0))
523 def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
524 def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
525 def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>;
526 def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>;
527 def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
528 def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
529 def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
530 def : DSReadPat <DS_READ_U16, i16, si_load_local>;
531 def : DSReadPat <DS_READ_B32, i32, si_load_local>;
533 let AddedComplexity = 100 in {
535 def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
537 } // End AddedComplexity = 100
540 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
542 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
545 class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
546 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
547 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
550 def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
551 def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
552 def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
553 def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
554 def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
556 let AddedComplexity = 100 in {
558 def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
559 } // End AddedComplexity = 100
562 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
564 (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
565 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
569 class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
570 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
571 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
574 class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
575 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
576 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
581 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
582 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
583 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
584 def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
585 def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
586 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
587 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
588 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
589 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
590 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
591 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
592 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
593 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
596 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
597 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
598 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
599 def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
600 def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
601 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
602 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
603 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
604 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
605 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
606 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
607 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
609 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
611 } // let Predicates = [isGCN]
613 //===----------------------------------------------------------------------===//
615 //===----------------------------------------------------------------------===//
617 //===----------------------------------------------------------------------===//
619 //===----------------------------------------------------------------------===//
621 class DS_Real_si <bits<8> op, DS_Pseudo ds> :
623 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
624 let AssemblerPredicates=[isSICI];
625 let DecoderNamespace="SICI";
628 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
629 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
630 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
631 let Inst{25-18} = op;
632 let Inst{31-26} = 0x36; // ds prefix
633 let Inst{39-32} = !if(ds.has_addr, addr, 0);
634 let Inst{47-40} = !if(ds.has_data0, data0, 0);
635 let Inst{55-48} = !if(ds.has_data1, data1, 0);
636 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
639 def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
640 def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
641 def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
642 def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
643 def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
644 def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
645 def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
646 def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
647 def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
648 def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
649 def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
650 def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
651 def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
652 def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
653 def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
654 def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
655 def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
656 def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
657 def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
658 def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
659 def DS_NOP_si : DS_Real_si<0x14, DS_NOP>;
660 def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
661 def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
662 def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
663 def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
664 def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
665 def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
666 def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
667 def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
668 def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
669 def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
670 def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
671 def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
672 def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
673 def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
674 def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
675 def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
676 def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
677 def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
678 def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
679 def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
680 def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
681 def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
682 def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
683 def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
684 def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
685 def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
686 def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
688 // These instruction are CI/VI only
689 def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
690 def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
691 def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
693 def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
694 def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
695 def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
696 def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
697 def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
698 def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
699 def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
700 def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
701 def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
702 def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
703 def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
704 def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
705 def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
706 def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
707 def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
708 def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
709 def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
710 def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
711 def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
712 def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
713 def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
714 def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
715 def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
716 def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
717 def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
718 def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
719 def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
720 def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
721 def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
722 def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
723 def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
725 def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
726 def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
727 def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
728 def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
729 def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
730 def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
731 def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
732 def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
733 def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
734 def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
735 def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
736 def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
737 def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
738 def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
739 def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
740 def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
741 def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
742 def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
743 def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
744 def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
746 def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
747 def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
748 def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
750 def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
751 def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
752 def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
753 def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
754 def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
755 def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
756 def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
757 def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
758 def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
759 def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
760 def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
761 def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
762 def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
764 def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
765 def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
767 def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
768 def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
769 def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
770 def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
771 def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
772 def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
773 def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
774 def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
775 def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
776 def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
777 def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
778 def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
779 def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
781 def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
782 def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
783 def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>;
784 def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>;
785 def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>;
786 def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
788 //===----------------------------------------------------------------------===//
790 //===----------------------------------------------------------------------===//
792 class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
794 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
795 let AssemblerPredicates = [isVI];
796 let DecoderNamespace="VI";
799 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
800 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
801 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
802 let Inst{24-17} = op;
803 let Inst{31-26} = 0x36; // ds prefix
804 let Inst{39-32} = !if(ds.has_addr, addr, 0);
805 let Inst{47-40} = !if(ds.has_data0, data0, 0);
806 let Inst{55-48} = !if(ds.has_data1, data1, 0);
807 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
810 def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
811 def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
812 def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
813 def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
814 def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
815 def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
816 def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
817 def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
818 def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
819 def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
820 def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
821 def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
822 def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
823 def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
824 def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
825 def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
826 def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
827 def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
828 def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
829 def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
830 def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
831 def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
832 def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
833 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
834 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
835 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
836 def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
837 def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
838 def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
839 def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
840 def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
841 def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
842 def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
843 def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
844 def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
845 def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
846 def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
847 def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
848 def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
849 def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
850 def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
851 def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
852 def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
853 def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
854 def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
855 def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
856 def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
857 def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
858 def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
859 def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
860 def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
861 def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
862 def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
863 def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
864 def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
865 def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
866 def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
867 def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
868 def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
869 def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
870 def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
871 def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
872 def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
873 def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
875 def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
876 def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
877 def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
878 def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
879 def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
880 def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
881 def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
882 def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
883 def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
884 def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
885 def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
886 def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
887 def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
888 def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
889 def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
890 def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
891 def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
892 def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
893 def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
894 def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
896 def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
897 def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
898 def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
899 def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
900 def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
901 def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
902 def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
903 def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
904 def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
905 def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
906 def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
907 def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
908 def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
909 def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
910 def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
911 def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
912 def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
913 def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
914 def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
915 def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
916 def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
917 def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
919 def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
920 def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
921 def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
923 def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
924 def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
925 def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
926 def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
927 def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
928 def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
929 def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
930 def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
931 def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
932 def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
933 def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
934 def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
935 def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
936 def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
937 def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
938 def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
939 def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
940 def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
941 def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
942 def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
943 def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
944 def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
945 def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
946 def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
947 def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
948 def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
949 def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
950 def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
951 def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
952 def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
953 def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
954 def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
955 def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
956 def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;