1 //===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
14 let SubtargetPredicate = isGCN;
19 let UseNamedOperandTable = 1;
21 // Most instruction load and store data, so set this as the default.
25 let hasSideEffects = 0;
26 let SchedRW = [WriteLDS];
29 let isCodeGenOnly = 1;
31 let AsmMatchConverter = "cvtDS";
33 string Mnemonic = opName;
34 string AsmOperands = asmOps;
36 // Well these bits a kind of hack because it would be more natural
37 // to test "outs" and "ins" dags for the presence of particular operands
40 bits<1> has_data0 = 1;
41 bits<1> has_data1 = 1;
43 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
44 bits<1> has_offset0 = 1;
45 bits<1> has_offset1 = 1;
48 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50 bits<1> has_m0_read = 1;
52 let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
55 class DS_Real <DS_Pseudo ds> :
56 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
60 let isCodeGenOnly = 0;
62 // copy relevant pseudo op flags
63 let SubtargetPredicate = ds.SubtargetPredicate;
64 let AsmMatchConverter = ds.AsmMatchConverter;
76 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
77 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
81 // DS Pseudo instructions
83 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
86 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
87 "$addr, $data0$offset$gds"> {
93 multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
94 def "" : DS_1A1D_NORET<opName, rc>,
95 AtomicNoRet<opName, 0>;
97 let has_m0_read = 0 in {
98 def _gfx9 : DS_1A1D_NORET<opName, rc>,
99 AtomicNoRet<opName#"_gfx9", 0>;
103 class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
106 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
107 "$addr, $data0, $data1"#"$offset"#"$gds"> {
112 multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
113 def "" : DS_1A2D_NORET<opName, rc>,
114 AtomicNoRet<opName, 0>;
116 let has_m0_read = 0 in {
117 def _gfx9 : DS_1A2D_NORET<opName, rc>,
118 AtomicNoRet<opName#"_gfx9", 0>;
122 class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
125 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
126 offset0:$offset0, offset1:$offset1, gds:$gds),
127 "$addr, $data0, $data1$offset0$offset1$gds"> {
131 let AsmMatchConverter = "cvtDSOffset01";
134 multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
135 def "" : DS_1A2D_Off8_NORET<opName, rc>;
137 let has_m0_read = 0 in {
138 def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
142 class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
145 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
146 "$vdst, $addr, $data0$offset$gds"> {
148 let hasPostISelHook = 1;
152 multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
153 string NoRetOp = ""> {
154 def "" : DS_1A1D_RET<opName, rc>,
155 AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
157 let has_m0_read = 0 in {
158 def _gfx9 : DS_1A1D_RET<opName, rc>,
159 AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
160 !if(!eq(NoRetOp, ""), 0, 1)>;
164 class DS_1A2D_RET<string opName,
165 RegisterClass rc = VGPR_32,
166 RegisterClass src = rc>
169 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
170 "$vdst, $addr, $data0, $data1$offset$gds"> {
172 let hasPostISelHook = 1;
175 multiclass DS_1A2D_RET_mc<string opName,
176 RegisterClass rc = VGPR_32,
178 RegisterClass src = rc> {
179 def "" : DS_1A2D_RET<opName, rc, src>,
180 AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
182 let has_m0_read = 0 in {
183 def _gfx9 : DS_1A2D_RET<opName, rc, src>,
184 AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>;
188 class DS_1A2D_Off8_RET<string opName,
189 RegisterClass rc = VGPR_32,
190 RegisterClass src = rc>
193 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
194 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
197 let AsmMatchConverter = "cvtDSOffset01";
199 let hasPostISelHook = 1;
202 multiclass DS_1A2D_Off8_RET_mc<string opName,
203 RegisterClass rc = VGPR_32,
204 RegisterClass src = rc> {
205 def "" : DS_1A2D_Off8_RET<opName, rc, src>;
207 let has_m0_read = 0 in {
208 def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
213 class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
217 (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
218 (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
219 "$vdst, $addr$offset$gds"> {
220 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
221 let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
226 multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
227 def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
229 let has_m0_read = 0 in {
230 def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
234 class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
235 DS_1A_RET<opName, rc, 1>;
237 class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
240 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
241 "$vdst, $addr$offset0$offset1$gds"> {
246 let AsmMatchConverter = "cvtDSOffset01";
249 multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
250 def "" : DS_1A_Off8_RET<opName, rc>;
252 let has_m0_read = 0 in {
253 def _gfx9 : DS_1A_Off8_RET<opName, rc>;
257 class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
258 (outs VGPR_32:$vdst),
259 (ins VGPR_32:$addr, offset:$offset),
260 "$vdst, $addr$offset gds"> {
266 let AsmMatchConverter = "cvtDSGds";
269 class DS_0A_RET <string opName> : DS_Pseudo<opName,
270 (outs VGPR_32:$vdst),
271 (ins offset:$offset, gds:$gds),
272 "$vdst$offset$gds"> {
282 class DS_1A <string opName> : DS_Pseudo<opName,
284 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
285 "$addr$offset$gds"> {
295 multiclass DS_1A_mc <string opName> {
296 def "" : DS_1A<opName>;
298 let has_m0_read = 0 in {
299 def _gfx9 : DS_1A<opName>;
304 class DS_GWS <string opName, dag ins, string asmOps>
305 : DS_Pseudo<opName, (outs), ins, asmOps> {
314 let AsmMatchConverter = "cvtDSGds";
317 class DS_GWS_0D <string opName>
319 (ins offset:$offset, gds:$gds), "$offset gds">;
321 class DS_GWS_1D <string opName>
323 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
328 class DS_VOID <string opName> : DS_Pseudo<opName,
332 let hasSideEffects = 1;
333 let UseNamedOperandTable = 0;
334 let AsmMatchConverter = "";
346 class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
348 (outs VGPR_32:$vdst),
349 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
350 "$vdst, $addr, $data0$offset",
352 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
356 let isConvergent = 1;
362 defm DS_ADD_U32 : DS_1A1D_NORET_mc<"ds_add_u32">;
363 defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">;
364 defm DS_RSUB_U32 : DS_1A1D_NORET_mc<"ds_rsub_u32">;
365 defm DS_INC_U32 : DS_1A1D_NORET_mc<"ds_inc_u32">;
366 defm DS_DEC_U32 : DS_1A1D_NORET_mc<"ds_dec_u32">;
367 defm DS_MIN_I32 : DS_1A1D_NORET_mc<"ds_min_i32">;
368 defm DS_MAX_I32 : DS_1A1D_NORET_mc<"ds_max_i32">;
369 defm DS_MIN_U32 : DS_1A1D_NORET_mc<"ds_min_u32">;
370 defm DS_MAX_U32 : DS_1A1D_NORET_mc<"ds_max_u32">;
371 defm DS_AND_B32 : DS_1A1D_NORET_mc<"ds_and_b32">;
372 defm DS_OR_B32 : DS_1A1D_NORET_mc<"ds_or_b32">;
373 defm DS_XOR_B32 : DS_1A1D_NORET_mc<"ds_xor_b32">;
374 defm DS_ADD_F32 : DS_1A1D_NORET_mc<"ds_add_f32">;
375 defm DS_MIN_F32 : DS_1A1D_NORET_mc<"ds_min_f32">;
376 defm DS_MAX_F32 : DS_1A1D_NORET_mc<"ds_max_f32">;
379 defm DS_WRITE_B8 : DS_1A1D_NORET_mc<"ds_write_b8">;
380 defm DS_WRITE_B16 : DS_1A1D_NORET_mc<"ds_write_b16">;
381 defm DS_WRITE_B32 : DS_1A1D_NORET_mc<"ds_write_b32">;
382 defm DS_WRITE2_B32 : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
383 defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
386 let has_m0_read = 0 in {
388 let SubtargetPredicate = HasD16LoadStore in {
389 def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
390 def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
393 let SubtargetPredicate = HasDSAddTid in {
394 def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
397 } // End has_m0_read = 0
400 defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">;
401 defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
402 defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
404 defm DS_ADD_U64 : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
405 defm DS_SUB_U64 : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
406 defm DS_RSUB_U64 : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
407 defm DS_INC_U64 : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
408 defm DS_DEC_U64 : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
409 defm DS_MIN_I64 : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
410 defm DS_MAX_I64 : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
411 defm DS_MIN_U64 : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
412 defm DS_MAX_U64 : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
413 defm DS_AND_B64 : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
414 defm DS_OR_B64 : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
415 defm DS_XOR_B64 : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
416 defm DS_MSKOR_B64 : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
418 defm DS_WRITE_B64 : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
419 defm DS_WRITE2_B64 : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
420 defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
422 defm DS_CMPST_B64 : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
423 defm DS_CMPST_F64 : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
424 defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
425 defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
427 defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
428 defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
429 defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
430 defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
431 defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
432 defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
433 defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
434 defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
435 defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
436 defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
437 defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
438 defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
439 defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
440 defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
441 defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
442 defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
443 defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
444 defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
446 defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
447 defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
448 defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
450 defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
451 defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
452 defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
453 defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
454 defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
455 defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
456 defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
457 defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
458 defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
459 defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
460 defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
461 defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
462 defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
463 defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
464 defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
465 defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
466 defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
468 defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
469 defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
470 defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
472 def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
473 def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
474 def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
475 def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
476 def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
478 def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
479 def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
480 def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
481 def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
482 def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
483 def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
484 def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
485 def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
486 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
487 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
488 def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
489 def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
490 def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
491 def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
493 def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
494 def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
495 def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
496 def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
497 def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
498 def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
499 def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
500 def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
501 def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
502 def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
503 def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
504 def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
505 def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
506 def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
508 def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
509 def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
511 let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
512 def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
515 let mayStore = 0 in {
516 defm DS_READ_I8 : DS_1A_RET_mc<"ds_read_i8">;
517 defm DS_READ_U8 : DS_1A_RET_mc<"ds_read_u8">;
518 defm DS_READ_I16 : DS_1A_RET_mc<"ds_read_i16">;
519 defm DS_READ_U16 : DS_1A_RET_mc<"ds_read_u16">;
520 defm DS_READ_B32 : DS_1A_RET_mc<"ds_read_b32">;
521 defm DS_READ_B64 : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
523 defm DS_READ2_B32 : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
524 defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
526 defm DS_READ2_B64 : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
527 defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
529 let has_m0_read = 0 in {
530 let SubtargetPredicate = HasD16LoadStore in {
531 def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">;
532 def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
533 def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">;
534 def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
535 def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">;
536 def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
539 let SubtargetPredicate = HasDSAddTid in {
540 def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
542 } // End has_m0_read = 0
545 def DS_CONSUME : DS_0A_RET<"ds_consume">;
546 def DS_APPEND : DS_0A_RET<"ds_append">;
547 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
549 //===----------------------------------------------------------------------===//
550 // Instruction definitions for CI and newer.
551 //===----------------------------------------------------------------------===//
553 let SubtargetPredicate = isCIVI in {
555 defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
556 defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
558 def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
560 let mayStore = 0 in {
561 defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
562 defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
563 } // End mayStore = 0
566 defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
567 defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
570 def DS_NOP : DS_VOID<"ds_nop">;
572 } // let SubtargetPredicate = isCIVI
574 //===----------------------------------------------------------------------===//
575 // Instruction definitions for VI and newer.
576 //===----------------------------------------------------------------------===//
578 let SubtargetPredicate = isVI in {
580 let Uses = [EXEC] in {
581 def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
582 int_amdgcn_ds_permute>;
583 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
584 int_amdgcn_ds_bpermute>;
587 def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
589 } // let SubtargetPredicate = isVI
591 //===----------------------------------------------------------------------===//
593 //===----------------------------------------------------------------------===//
596 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
597 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
600 class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
601 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
602 (inst $ptr, (as_i16imm $offset), (i1 0))
605 multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
607 let OtherPredicates = [LDSRequiresM0Init] in {
608 def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
611 let OtherPredicates = [NotLDSRequiresM0Init] in {
612 def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
617 multiclass DSReadPat_Hi16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> {
619 (build_vector vt:$lo, (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))),
620 (v2i16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo))
624 (build_vector f16:$lo, (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))))),
625 (v2f16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo))
629 multiclass DSReadPat_Lo16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> {
631 (build_vector (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), (vt (Hi16Elt vt:$hi))),
632 (v2i16 (inst $ptr, (as_i16imm $offset), 0, $hi))
636 (build_vector (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))))), (f16 (Hi16Elt f16:$hi))),
637 (v2f16 (inst $ptr, (as_i16imm $offset), 0, $hi))
641 defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
642 defm : DSReadPat_mc <DS_READ_U8, i32, "az_extloadi8_local">;
643 defm : DSReadPat_mc <DS_READ_I8, i16, "sextloadi8_local">;
644 defm : DSReadPat_mc <DS_READ_U8, i16, "az_extloadi8_local">;
645 defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
646 defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
647 defm : DSReadPat_mc <DS_READ_U16, i32, "az_extloadi16_local">;
648 defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
649 defm : DSReadPat_mc <DS_READ_B32, i32, "load_local">;
650 defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
651 defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
653 let AddedComplexity = 100 in {
655 defm : DSReadPat_mc <DS_READ_B64, v2i32, "load_align8_local">;
656 defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">;
658 } // End AddedComplexity = 100
660 let OtherPredicates = [D16PreservesUnusedBits] in {
661 let AddedComplexity = 100 in {
662 defm : DSReadPat_Hi16<DS_READ_U16_D16_HI, load_local>;
663 defm : DSReadPat_Hi16<DS_READ_U8_D16_HI, az_extloadi8_local>;
664 defm : DSReadPat_Hi16<DS_READ_I8_D16_HI, sextloadi8_local>;
666 defm : DSReadPat_Lo16<DS_READ_U16_D16, load_local>;
667 defm : DSReadPat_Lo16<DS_READ_U8_D16, az_extloadi8_local>;
668 defm : DSReadPat_Lo16<DS_READ_I8_D16, sextloadi8_local>;
673 class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
674 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
675 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
678 multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
679 let OtherPredicates = [LDSRequiresM0Init] in {
680 def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
683 let OtherPredicates = [NotLDSRequiresM0Init] in {
684 def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
688 // Irritatingly, atomic_store reverses the order of operands from a
690 class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
691 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
692 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
695 multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
696 let OtherPredicates = [LDSRequiresM0Init] in {
697 def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
700 let OtherPredicates = [NotLDSRequiresM0Init] in {
701 def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
705 defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
706 defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
707 defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
708 defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
709 defm : DSWritePat_mc <DS_WRITE_B32, i32, "store_local">;
710 defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local">;
711 defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local">;
713 let OtherPredicates = [D16PreservesUnusedBits] in {
714 def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
715 def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
719 class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, PatFrag frag> : GCNPat <
720 (v2i32 (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
721 (inst $ptr, $offset0, $offset1, (i1 0))
724 class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, PatFrag frag> : GCNPat<
725 (frag v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
726 (inst $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
727 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
731 // v2i32 loads are split into i32 loads on SI during lowering, due to a bug
732 // related to bounds checking.
733 let OtherPredicates = [LDSRequiresM0Init, isCIVI] in {
734 def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, load_local_m0>;
735 def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, store_local_m0>;
738 let OtherPredicates = [NotLDSRequiresM0Init] in {
739 def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, load_local>;
740 def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, store_local>;
744 let AddedComplexity = 100 in {
746 defm : DSWritePat_mc <DS_WRITE_B64, v2i32, "store_align8_local">;
747 defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
749 } // End AddedComplexity = 100
750 class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
751 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
752 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
755 multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
756 let OtherPredicates = [LDSRequiresM0Init] in {
757 def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
760 let OtherPredicates = [NotLDSRequiresM0Init] in {
761 def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
762 !cast<PatFrag>(frag)>;
768 class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
769 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
770 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
773 multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
774 let OtherPredicates = [LDSRequiresM0Init] in {
775 def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_m0")>;
778 let OtherPredicates = [NotLDSRequiresM0Init] in {
779 def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
780 !cast<PatFrag>(frag)>;
787 defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap_local">;
788 defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add_local">;
789 defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub_local">;
790 defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc_local">;
791 defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec_local">;
792 defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and_local">;
793 defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or_local">;
794 defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor_local">;
795 defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min_local">;
796 defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max_local">;
797 defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin_local">;
798 defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax_local">;
799 defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap_local">;
800 defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin_local">;
801 defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax_local">;
802 defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd_local">;
805 defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap_local">;
806 defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add_local">;
807 defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub_local">;
808 defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc_local">;
809 defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec_local">;
810 defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and_local">;
811 defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or_local">;
812 defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor_local">;
813 defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min_local">;
814 defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max_local">;
815 defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin_local">;
816 defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax_local">;
818 defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap_local">;
821 (SIds_ordered_count i32:$value, i16:$offset),
822 (DS_ORDERED_COUNT $value, (as_i16imm $offset))
825 //===----------------------------------------------------------------------===//
827 //===----------------------------------------------------------------------===//
829 //===----------------------------------------------------------------------===//
831 //===----------------------------------------------------------------------===//
833 class DS_Real_si <bits<8> op, DS_Pseudo ds> :
835 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
836 let AssemblerPredicates=[isSICI];
837 let DecoderNamespace="SICI";
840 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
841 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
842 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
843 let Inst{25-18} = op;
844 let Inst{31-26} = 0x36; // ds prefix
845 let Inst{39-32} = !if(ds.has_addr, addr, 0);
846 let Inst{47-40} = !if(ds.has_data0, data0, 0);
847 let Inst{55-48} = !if(ds.has_data1, data1, 0);
848 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
851 def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
852 def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
853 def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
854 def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
855 def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
856 def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
857 def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
858 def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
859 def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
860 def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
861 def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
862 def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
863 def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
864 def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
865 def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
866 def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
867 def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
868 def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
869 def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
870 def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
871 def DS_NOP_si : DS_Real_si<0x14, DS_NOP>;
872 def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
873 def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
874 def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
875 def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
876 def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
877 def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
878 def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
879 def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
880 def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
881 def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
882 def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
883 def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
884 def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
885 def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
886 def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
887 def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
888 def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
889 def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
890 def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
891 def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
892 def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
893 def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
894 def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
895 def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
896 def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
897 def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
898 def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
900 // These instruction are CI/VI only
901 def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
902 def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
903 def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
905 def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
906 def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
907 def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
908 def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
909 def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
910 def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
911 def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
912 def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
913 def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
914 def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
915 def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
916 def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
917 def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
918 def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
919 def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
920 def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
921 def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
922 def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
923 def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
924 def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
925 def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
926 def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
927 def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
928 def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
929 def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
930 def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
931 def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
932 def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
933 def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
934 def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
935 def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
937 def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
938 def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
939 def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
940 def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
941 def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
942 def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
943 def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
944 def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
945 def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
946 def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
947 def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
948 def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
949 def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
950 def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
951 def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
952 def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
953 def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
954 def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
955 def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
956 def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
958 def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
959 def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
960 def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
962 def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
963 def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
964 def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
965 def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
966 def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
967 def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
968 def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
969 def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
970 def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
971 def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
972 def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
973 def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
974 def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
976 def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
977 def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
979 def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
980 def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
981 def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
982 def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
983 def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
984 def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
985 def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
986 def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
987 def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
988 def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
989 def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
990 def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
991 def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
993 def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
994 def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
995 def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>;
996 def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>;
997 def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>;
998 def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
1000 //===----------------------------------------------------------------------===//
1001 // VIInstructions.td
1002 //===----------------------------------------------------------------------===//
1004 class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
1006 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
1007 let AssemblerPredicates = [isVI];
1008 let DecoderNamespace="VI";
1011 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
1012 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
1013 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
1014 let Inst{24-17} = op;
1015 let Inst{31-26} = 0x36; // ds prefix
1016 let Inst{39-32} = !if(ds.has_addr, addr, 0);
1017 let Inst{47-40} = !if(ds.has_data0, data0, 0);
1018 let Inst{55-48} = !if(ds.has_data1, data1, 0);
1019 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
1022 def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
1023 def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
1024 def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
1025 def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
1026 def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
1027 def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
1028 def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
1029 def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
1030 def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
1031 def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
1032 def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
1033 def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
1034 def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
1035 def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
1036 def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
1037 def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
1038 def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
1039 def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
1040 def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
1041 def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
1042 def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
1043 def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
1044 def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
1045 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1046 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1047 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1048 def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1049 def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1050 def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
1051 def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
1052 def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1053 def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1054 def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1055 def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1056 def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1057 def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1058 def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1059 def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1060 def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1061 def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1062 def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1063 def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1064 def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1065 def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1066 def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1067 def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1068 def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1069 def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1070 def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1071 def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1072 def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1073 def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1074 def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
1075 def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
1076 def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1077 def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
1078 def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
1079 def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
1080 def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
1081 def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1082 def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
1083 def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
1084 def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1085 def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1086 def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1087 def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1089 def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
1090 def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
1091 def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
1092 def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
1093 def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
1094 def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
1095 def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
1096 def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
1097 def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
1098 def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
1099 def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
1100 def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
1101 def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1102 def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
1103 def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1104 def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1105 def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
1106 def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
1107 def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
1108 def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
1110 def DS_WRITE_B8_D16_HI_vi : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1111 def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1113 def DS_READ_U8_D16_vi : DS_Real_vi<0x56, DS_READ_U8_D16>;
1114 def DS_READ_U8_D16_HI_vi : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1115 def DS_READ_I8_D16_vi : DS_Real_vi<0x58, DS_READ_I8_D16>;
1116 def DS_READ_I8_D16_HI_vi : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1117 def DS_READ_U16_D16_vi : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1118 def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1120 def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1121 def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1122 def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1123 def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1124 def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1125 def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1126 def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1127 def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1128 def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1129 def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1130 def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1131 def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1132 def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1133 def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1134 def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1135 def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1136 def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1137 def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1138 def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1139 def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1140 def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1141 def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1143 def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
1144 def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
1145 def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1147 def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1148 def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1149 def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1150 def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1151 def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1152 def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1153 def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1154 def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1155 def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1156 def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1157 def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1158 def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1159 def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1160 def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1161 def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1162 def DS_ADD_SRC2_F32_vi : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1163 def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1164 def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1165 def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1166 def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1167 def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1168 def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1169 def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1170 def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1171 def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1172 def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1173 def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1174 def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1175 def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1176 def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1177 def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1178 def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
1179 def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
1180 def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
1181 def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;