1 //===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
14 let SubtargetPredicate = isGCN;
19 let UseNamedOperandTable = 1;
20 let Uses = [M0, EXEC];
22 // Most instruction load and store data, so set this as the default.
26 let hasSideEffects = 0;
27 let SchedRW = [WriteLDS];
30 let isCodeGenOnly = 1;
32 let AsmMatchConverter = "cvtDS";
34 string Mnemonic = opName;
35 string AsmOperands = asmOps;
37 // Well these bits a kind of hack because it would be more natural
38 // to test "outs" and "ins" dags for the presence of particular operands
41 bits<1> has_data0 = 1;
42 bits<1> has_data1 = 1;
44 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
45 bits<1> has_offset0 = 1;
46 bits<1> has_offset1 = 1;
49 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
52 class DS_Real <DS_Pseudo ds> :
53 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
57 let isCodeGenOnly = 0;
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ds.SubtargetPredicate;
61 let AsmMatchConverter = ds.AsmMatchConverter;
73 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
78 // DS Pseudo instructions
80 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
83 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84 "$addr, $data0$offset$gds">,
85 AtomicNoRet<opName, 0> {
91 class DS_1A_Off8_NORET<string opName> : DS_Pseudo<opName,
93 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
94 "$addr $offset0$offset1$gds"> {
100 let AsmMatchConverter = "cvtDSOffset01";
103 class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
106 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
107 "$addr, $data0, $data1"#"$offset"#"$gds">,
108 AtomicNoRet<opName, 0> {
113 class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
116 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
117 offset0:$offset0, offset1:$offset1, gds:$gds),
118 "$addr, $data0, $data1$offset0$offset1$gds"> {
122 let AsmMatchConverter = "cvtDSOffset01";
125 class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
128 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
129 "$vdst, $addr, $data0$offset$gds"> {
131 let hasPostISelHook = 1;
135 class DS_1A2D_RET<string opName,
136 RegisterClass rc = VGPR_32,
137 RegisterClass src = rc>
140 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
141 "$vdst, $addr, $data0, $data1$offset$gds"> {
143 let hasPostISelHook = 1;
146 class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
149 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
150 "$vdst, $addr$offset$gds"> {
156 class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
159 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
160 "$vdst, $addr$offset0$offset1$gds"> {
165 let AsmMatchConverter = "cvtDSOffset01";
168 class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
169 (outs VGPR_32:$vdst),
170 (ins VGPR_32:$addr, offset:$offset),
171 "$vdst, $addr$offset gds"> {
179 class DS_0A_RET <string opName> : DS_Pseudo<opName,
180 (outs VGPR_32:$vdst),
181 (ins offset:$offset, gds:$gds),
182 "$vdst$offset$gds"> {
192 class DS_1A <string opName> : DS_Pseudo<opName,
194 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
195 "$addr$offset$gds"> {
205 class DS_1A_GDS <string opName> : DS_Pseudo<opName,
221 class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
223 (outs VGPR_32:$vdst),
224 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
225 "$vdst, $addr, $data0$offset",
227 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
231 let isConvergent = 1;
237 def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
238 def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
239 def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
240 def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
241 def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
242 def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
243 def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
244 def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
245 def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
246 def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
247 def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
248 def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
249 def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
250 def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
251 def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
254 def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
255 def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
256 def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
257 def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
258 def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
261 def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
262 def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
263 def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
265 def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
266 def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
267 def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
268 def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
269 def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
270 def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
271 def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
272 def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
273 def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
274 def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
275 def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
276 def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
277 def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
279 def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
280 def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
281 def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
283 def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
284 def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
285 def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
286 def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
288 def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
289 AtomicNoRet<"ds_add_u32", 1>;
290 def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
291 AtomicNoRet<"ds_add_f32", 1>;
292 def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
293 AtomicNoRet<"ds_sub_u32", 1>;
294 def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
295 AtomicNoRet<"ds_rsub_u32", 1>;
296 def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
297 AtomicNoRet<"ds_inc_u32", 1>;
298 def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
299 AtomicNoRet<"ds_dec_u32", 1>;
300 def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
301 AtomicNoRet<"ds_min_i32", 1>;
302 def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
303 AtomicNoRet<"ds_max_i32", 1>;
304 def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
305 AtomicNoRet<"ds_min_u32", 1>;
306 def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
307 AtomicNoRet<"ds_max_u32", 1>;
308 def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
309 AtomicNoRet<"ds_and_b32", 1>;
310 def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
311 AtomicNoRet<"ds_or_b32", 1>;
312 def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
313 AtomicNoRet<"ds_xor_b32", 1>;
314 def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
315 AtomicNoRet<"ds_mskor_b32", 1>;
316 def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
317 AtomicNoRet<"ds_cmpst_b32", 1>;
318 def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
319 AtomicNoRet<"ds_cmpst_f32", 1>;
320 def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
321 AtomicNoRet<"ds_min_f32", 1>;
322 def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
323 AtomicNoRet<"ds_max_f32", 1>;
325 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
327 def DS_WRXCHG2_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
329 def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
332 def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
333 AtomicNoRet<"ds_add_u64", 1>;
334 def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
335 AtomicNoRet<"ds_sub_u64", 1>;
336 def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
337 AtomicNoRet<"ds_rsub_u64", 1>;
338 def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
339 AtomicNoRet<"ds_inc_u64", 1>;
340 def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
341 AtomicNoRet<"ds_dec_u64", 1>;
342 def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
343 AtomicNoRet<"ds_min_i64", 1>;
344 def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
345 AtomicNoRet<"ds_max_i64", 1>;
346 def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
347 AtomicNoRet<"ds_min_u64", 1>;
348 def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
349 AtomicNoRet<"ds_max_u64", 1>;
350 def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
351 AtomicNoRet<"ds_and_b64", 1>;
352 def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
353 AtomicNoRet<"ds_or_b64", 1>;
354 def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
355 AtomicNoRet<"ds_xor_b64", 1>;
356 def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
357 AtomicNoRet<"ds_mskor_b64", 1>;
358 def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
359 AtomicNoRet<"ds_cmpst_b64", 1>;
360 def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
361 AtomicNoRet<"ds_cmpst_f64", 1>;
362 def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
363 AtomicNoRet<"ds_min_f64", 1>;
364 def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
365 AtomicNoRet<"ds_max_f64", 1>;
367 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
368 AtomicNoRet<"ds_wrxchg_b64", 1>;
369 def DS_WRXCHG2_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
370 AtomicNoRet<"ds_wrxchg2_b64", 1>;
371 def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
372 AtomicNoRet<"ds_wrxchg2st64_b64", 1>;
374 def DS_GWS_INIT : DS_1A_GDS<"ds_gws_init">;
375 def DS_GWS_SEMA_V : DS_1A_GDS<"ds_gws_sema_v">;
376 def DS_GWS_SEMA_BR : DS_1A_GDS<"ds_gws_sema_br">;
377 def DS_GWS_SEMA_P : DS_1A_GDS<"ds_gws_sema_p">;
378 def DS_GWS_BARRIER : DS_1A_GDS<"ds_gws_barrier">;
380 def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
381 def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
382 def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
383 def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
384 def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
385 def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
386 def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
387 def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
388 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
389 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src_b32">;
390 def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
391 def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
392 def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
393 def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
395 def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
396 def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
397 def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
398 def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
399 def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
400 def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
401 def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
402 def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
403 def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
404 def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
405 def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
406 def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
407 def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
408 def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
410 def DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET<"ds_write_src2_b32">;
411 def DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET<"ds_write_src2_b64">;
413 let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
414 def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
417 let mayStore = 0 in {
418 def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
419 def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
420 def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
421 def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
422 def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
423 def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
425 def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
426 def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
428 def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
429 def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
432 let SubtargetPredicate = isSICI in {
433 def DS_CONSUME : DS_0A_RET<"ds_consume">;
434 def DS_APPEND : DS_0A_RET<"ds_append">;
435 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
438 //===----------------------------------------------------------------------===//
439 // Instruction definitions for CI and newer.
440 //===----------------------------------------------------------------------===//
441 // Remaining instructions:
443 // DS_GWS_SEMA_RELEASE_ALL
445 // DS_CNDXCHG32_RTN_B64
448 // DS_CONDXCHG32_RTN_B128
452 let SubtargetPredicate = isCIVI in {
454 def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">,
455 AtomicNoRet<"ds_wrap_f32", 1>;
457 } // let SubtargetPredicate = isCIVI
459 //===----------------------------------------------------------------------===//
460 // Instruction definitions for VI and newer.
461 //===----------------------------------------------------------------------===//
463 let SubtargetPredicate = isVI in {
465 let Uses = [EXEC] in {
466 def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
467 int_amdgcn_ds_permute>;
468 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
469 int_amdgcn_ds_bpermute>;
472 } // let SubtargetPredicate = isVI
474 //===----------------------------------------------------------------------===//
476 //===----------------------------------------------------------------------===//
478 let Predicates = [isGCN] in {
481 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
482 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
485 class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
486 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
487 (inst $ptr, (as_i16imm $offset), (i1 0))
490 def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
491 def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
492 def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>;
493 def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>;
494 def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
495 def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
496 def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
497 def : DSReadPat <DS_READ_U16, i16, si_load_local>;
498 def : DSReadPat <DS_READ_B32, i32, si_load_local>;
500 let AddedComplexity = 100 in {
502 def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
504 } // End AddedComplexity = 100
507 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
509 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
512 class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
513 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
514 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
517 def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
518 def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
519 def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
520 def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
521 def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
523 let AddedComplexity = 100 in {
525 def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
526 } // End AddedComplexity = 100
529 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
531 (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
532 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
536 class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
537 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
538 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
541 class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
542 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
543 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
548 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
549 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
550 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
551 def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
552 def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
553 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
554 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
555 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
556 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
557 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
558 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
559 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
560 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
563 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
564 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
565 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
566 def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
567 def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
568 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
569 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
570 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
571 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
572 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
573 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
574 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
576 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
578 } // let Predicates = [isGCN]
580 //===----------------------------------------------------------------------===//
582 //===----------------------------------------------------------------------===//
584 //===----------------------------------------------------------------------===//
586 //===----------------------------------------------------------------------===//
588 class DS_Real_si <bits<8> op, DS_Pseudo ds> :
590 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
591 let AssemblerPredicates=[isSICI];
592 let DecoderNamespace="SICI";
595 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
596 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
597 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
598 let Inst{25-18} = op;
599 let Inst{31-26} = 0x36; // ds prefix
600 let Inst{39-32} = !if(ds.has_addr, addr, 0);
601 let Inst{47-40} = !if(ds.has_data0, data0, 0);
602 let Inst{55-48} = !if(ds.has_data1, data1, 0);
603 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
606 def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
607 def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
608 def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
609 def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
610 def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
611 def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
612 def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
613 def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
614 def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
615 def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
616 def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
617 def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
618 def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
619 def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
620 def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
621 def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
622 def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
623 def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
624 def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
625 def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
626 def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
627 def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
628 def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
629 def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
630 def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
631 def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
632 def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
633 def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
634 def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
635 def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
636 def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
637 def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
638 def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
639 def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
640 def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
641 def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
642 def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
643 def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
644 def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
645 def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
646 def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
647 def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
648 def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
649 def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
650 def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
651 def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
652 def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
654 // FIXME: this instruction is actually CI/VI
655 def DS_WRAP_RTN_F32_si : DS_Real_si<0x34, DS_WRAP_RTN_F32>;
657 def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
658 def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
659 def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
660 def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
661 def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
662 def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
663 def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
664 def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
665 def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
666 def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
667 def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
668 def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
669 def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
670 def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
671 def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
672 def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
673 def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
674 def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
675 def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
676 def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
677 def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
678 def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
679 def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
680 def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
681 def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
682 def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
683 def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
684 def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
685 def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
686 def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
687 def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
689 def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
690 def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
691 def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
692 def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
693 def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
694 def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
695 def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
696 def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
697 def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
698 def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
699 def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
700 def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
701 def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
702 def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
703 def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
704 def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
705 def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
706 def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
707 def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
708 def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
710 def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
711 def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
712 def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
714 def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
715 def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
716 def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
717 def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
718 def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
719 def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
720 def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
721 def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
722 def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
723 def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
724 def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
725 def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
726 def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
728 def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
729 def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
731 def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
732 def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
733 def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
734 def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
735 def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
736 def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
737 def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
738 def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
739 def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
740 def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
741 def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
742 def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
743 def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
745 def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
746 def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
748 //===----------------------------------------------------------------------===//
750 //===----------------------------------------------------------------------===//
752 class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
754 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
755 let AssemblerPredicates = [isVI];
756 let DecoderNamespace="VI";
759 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
760 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
761 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
762 let Inst{24-17} = op;
763 let Inst{31-26} = 0x36; // ds prefix
764 let Inst{39-32} = !if(ds.has_addr, addr, 0);
765 let Inst{47-40} = !if(ds.has_data0, data0, 0);
766 let Inst{55-48} = !if(ds.has_data1, data1, 0);
767 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
770 def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
771 def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
772 def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
773 def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
774 def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
775 def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
776 def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
777 def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
778 def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
779 def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
780 def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
781 def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
782 def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
783 def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
784 def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
785 def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
786 def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
787 def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
788 def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
789 def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
790 def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
791 def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>;
792 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
793 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
794 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>;
795 def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>;
796 def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
797 def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
798 def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
799 def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
800 def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
801 def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
802 def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
803 def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
804 def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
805 def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
806 def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
807 def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
808 def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
809 def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
810 def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
811 def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
812 def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
813 def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
814 def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
815 def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
816 def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
817 def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
818 def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
819 def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
820 def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
821 def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
822 def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
823 def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
824 def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
825 def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
826 def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
827 def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
828 def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
829 def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
831 def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
832 def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
833 def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
834 def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
835 def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
836 def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
837 def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
838 def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
839 def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
840 def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
841 def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
842 def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
843 def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
844 def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
845 def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
846 def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
847 def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
848 def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
849 def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
850 def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
852 def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
853 def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
854 def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
855 def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
856 def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
857 def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
858 def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
859 def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
860 def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
861 def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
862 def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
863 def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
864 def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
865 def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
866 def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
867 def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
868 def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
869 def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
870 def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
871 def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
873 def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
874 def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
875 def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
877 def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
878 def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
879 def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
880 def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
881 def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
882 def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
883 def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
884 def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
885 def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
886 def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
887 def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
888 def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
889 def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
890 def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
891 def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
892 def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
893 def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
894 def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
895 def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
896 def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
897 def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
898 def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
899 def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
900 def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
901 def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
902 def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
903 def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
904 def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
905 def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
906 def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;