1 //===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10 InstSI <outs, ins, "", pattern>,
11 SIMCInstr <opName, SIEncodingFamily.NONE> {
16 let UseNamedOperandTable = 1;
18 // Most instruction load and store data, so set this as the default.
23 let hasSideEffects = 0;
24 let SchedRW = [WriteLDS];
27 let isCodeGenOnly = 1;
29 let AsmMatchConverter = "cvtDS";
31 string Mnemonic = opName;
32 string AsmOperands = asmOps;
34 // Well these bits a kind of hack because it would be more natural
35 // to test "outs" and "ins" dags for the presence of particular operands
38 bits<1> has_data0 = 1;
39 bits<1> has_data1 = 1;
41 bits<1> has_gws_data0 = 0; // data0 is encoded as addr
43 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
44 bits<1> has_offset0 = 1;
45 bits<1> has_offset1 = 1;
48 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50 bits<1> has_m0_read = 1;
52 let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
55 class DS_Real <DS_Pseudo ds> :
56 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
60 let isCodeGenOnly = 0;
62 // copy relevant pseudo op flags
63 let SubtargetPredicate = ds.SubtargetPredicate;
64 let OtherPredicates = ds.OtherPredicates;
65 let AsmMatchConverter = ds.AsmMatchConverter;
77 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
78 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
82 // DS Pseudo instructions
84 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
87 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
88 "$addr, $data0$offset$gds"> {
94 multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
95 def "" : DS_1A1D_NORET<opName, rc>,
96 AtomicNoRet<opName, 0>;
98 let has_m0_read = 0 in {
99 def _gfx9 : DS_1A1D_NORET<opName, rc>,
100 AtomicNoRet<opName#"_gfx9", 0>;
104 class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
107 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
108 "$addr, $data0, $data1"#"$offset"#"$gds"> {
113 multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
114 def "" : DS_1A2D_NORET<opName, rc>,
115 AtomicNoRet<opName, 0>;
117 let has_m0_read = 0 in {
118 def _gfx9 : DS_1A2D_NORET<opName, rc>,
119 AtomicNoRet<opName#"_gfx9", 0>;
123 class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
126 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
127 offset0:$offset0, offset1:$offset1, gds:$gds),
128 "$addr, $data0, $data1$offset0$offset1$gds"> {
132 let AsmMatchConverter = "cvtDSOffset01";
135 multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
136 def "" : DS_1A2D_Off8_NORET<opName, rc>;
138 let has_m0_read = 0 in {
139 def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
143 class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
146 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
147 "$vdst, $addr, $data0$offset$gds"> {
149 let hasPostISelHook = 1;
153 multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
154 string NoRetOp = ""> {
155 def "" : DS_1A1D_RET<opName, rc>,
156 AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
158 let has_m0_read = 0 in {
159 def _gfx9 : DS_1A1D_RET<opName, rc>,
160 AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
161 !if(!eq(NoRetOp, ""), 0, 1)>;
165 class DS_1A2D_RET<string opName,
166 RegisterClass rc = VGPR_32,
167 RegisterClass src = rc>
170 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
171 "$vdst, $addr, $data0, $data1$offset$gds"> {
173 let hasPostISelHook = 1;
176 multiclass DS_1A2D_RET_mc<string opName,
177 RegisterClass rc = VGPR_32,
179 RegisterClass src = rc> {
180 def "" : DS_1A2D_RET<opName, rc, src>,
181 AtomicNoRet<NoRetOp, !if(!eq(NoRetOp, ""), 0, 1)>;
183 let has_m0_read = 0 in {
184 def _gfx9 : DS_1A2D_RET<opName, rc, src>,
185 AtomicNoRet<NoRetOp#"_gfx9", !if(!eq(NoRetOp, ""), 0, 1)>;
189 class DS_1A2D_Off8_RET<string opName,
190 RegisterClass rc = VGPR_32,
191 RegisterClass src = rc>
194 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
195 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
198 let AsmMatchConverter = "cvtDSOffset01";
200 let hasPostISelHook = 1;
203 multiclass DS_1A2D_Off8_RET_mc<string opName,
204 RegisterClass rc = VGPR_32,
205 RegisterClass src = rc> {
206 def "" : DS_1A2D_Off8_RET<opName, rc, src>;
208 let has_m0_read = 0 in {
209 def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
214 class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset>
218 (ins VGPR_32:$addr, ofs:$offset, gds:$gds, rc:$vdst_in),
219 (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
220 "$vdst, $addr$offset$gds"> {
221 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
222 let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
227 multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
228 def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
230 let has_m0_read = 0 in {
231 def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
235 class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
236 DS_1A_RET<opName, rc, 1>;
238 class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
241 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
242 "$vdst, $addr$offset0$offset1$gds"> {
247 let AsmMatchConverter = "cvtDSOffset01";
250 multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
251 def "" : DS_1A_Off8_RET<opName, rc>;
253 let has_m0_read = 0 in {
254 def _gfx9 : DS_1A_Off8_RET<opName, rc>;
258 class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
259 (outs VGPR_32:$vdst),
260 (ins VGPR_32:$addr, offset:$offset),
261 "$vdst, $addr$offset gds"> {
267 let AsmMatchConverter = "cvtDSGds";
270 class DS_0A_RET <string opName> : DS_Pseudo<opName,
271 (outs VGPR_32:$vdst),
272 (ins offset:$offset, gds:$gds),
273 "$vdst$offset$gds"> {
283 class DS_1A <string opName> : DS_Pseudo<opName,
285 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
286 "$addr$offset$gds"> {
296 multiclass DS_1A_mc <string opName> {
297 def "" : DS_1A<opName>;
299 let has_m0_read = 0 in {
300 def _gfx9 : DS_1A<opName>;
305 class DS_GWS <string opName, dag ins, string asmOps>
306 : DS_Pseudo<opName, (outs), ins, asmOps> {
315 let AsmMatchConverter = "cvtDSGds";
318 class DS_GWS_0D <string opName>
320 (ins offset:$offset, gds:$gds), "$offset gds">;
322 class DS_GWS_1D <string opName>
324 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
326 let has_gws_data0 = 1;
329 class DS_VOID <string opName> : DS_Pseudo<opName,
333 let hasSideEffects = 1;
334 let UseNamedOperandTable = 0;
335 let AsmMatchConverter = "";
347 class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
349 (outs VGPR_32:$vdst),
350 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
351 "$vdst, $addr, $data0$offset",
353 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
357 let isConvergent = 1;
363 defm DS_ADD_U32 : DS_1A1D_NORET_mc<"ds_add_u32">;
364 defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">;
365 defm DS_RSUB_U32 : DS_1A1D_NORET_mc<"ds_rsub_u32">;
366 defm DS_INC_U32 : DS_1A1D_NORET_mc<"ds_inc_u32">;
367 defm DS_DEC_U32 : DS_1A1D_NORET_mc<"ds_dec_u32">;
368 defm DS_MIN_I32 : DS_1A1D_NORET_mc<"ds_min_i32">;
369 defm DS_MAX_I32 : DS_1A1D_NORET_mc<"ds_max_i32">;
370 defm DS_MIN_U32 : DS_1A1D_NORET_mc<"ds_min_u32">;
371 defm DS_MAX_U32 : DS_1A1D_NORET_mc<"ds_max_u32">;
372 defm DS_AND_B32 : DS_1A1D_NORET_mc<"ds_and_b32">;
373 defm DS_OR_B32 : DS_1A1D_NORET_mc<"ds_or_b32">;
374 defm DS_XOR_B32 : DS_1A1D_NORET_mc<"ds_xor_b32">;
375 defm DS_ADD_F32 : DS_1A1D_NORET_mc<"ds_add_f32">;
376 defm DS_MIN_F32 : DS_1A1D_NORET_mc<"ds_min_f32">;
377 defm DS_MAX_F32 : DS_1A1D_NORET_mc<"ds_max_f32">;
380 defm DS_WRITE_B8 : DS_1A1D_NORET_mc<"ds_write_b8">;
381 defm DS_WRITE_B16 : DS_1A1D_NORET_mc<"ds_write_b16">;
382 defm DS_WRITE_B32 : DS_1A1D_NORET_mc<"ds_write_b32">;
383 defm DS_WRITE2_B32 : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
384 defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
387 let has_m0_read = 0 in {
389 let SubtargetPredicate = HasD16LoadStore in {
390 def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
391 def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
394 let SubtargetPredicate = HasDSAddTid in {
395 def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
398 } // End has_m0_read = 0
401 defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">;
402 defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
403 defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
405 defm DS_ADD_U64 : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
406 defm DS_SUB_U64 : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
407 defm DS_RSUB_U64 : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
408 defm DS_INC_U64 : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
409 defm DS_DEC_U64 : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
410 defm DS_MIN_I64 : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
411 defm DS_MAX_I64 : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
412 defm DS_MIN_U64 : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
413 defm DS_MAX_U64 : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
414 defm DS_AND_B64 : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
415 defm DS_OR_B64 : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
416 defm DS_XOR_B64 : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
417 defm DS_MSKOR_B64 : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
419 defm DS_WRITE_B64 : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
420 defm DS_WRITE2_B64 : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
421 defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
423 defm DS_CMPST_B64 : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
424 defm DS_CMPST_F64 : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
425 defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
426 defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
428 defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
429 defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
430 defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
431 defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
432 defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
433 defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
434 defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
435 defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
436 defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
437 defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
438 defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
439 defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
440 defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
441 defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
442 defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
443 defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
444 defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
445 defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
447 defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
448 defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
449 defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
451 defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
452 defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
453 defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
454 defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
455 defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
456 defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
457 defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
458 defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
459 defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
460 defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
461 defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
462 defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
463 defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
464 defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
465 defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
466 defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
467 defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
469 defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
470 defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
471 defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
473 let isConvergent = 1, usesCustomInserter = 1 in {
474 def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init"> {
477 def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
478 def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
479 def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
480 def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
483 def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
484 def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
485 def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
486 def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
487 def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
488 def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
489 def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
490 def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
491 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
492 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
493 def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
494 def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
495 def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
496 def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
498 def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
499 def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
500 def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
501 def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
502 def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
503 def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
504 def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
505 def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
506 def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
507 def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
508 def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
509 def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
510 def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
511 def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
513 def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
514 def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
516 let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
517 def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
520 let mayStore = 0 in {
521 defm DS_READ_I8 : DS_1A_RET_mc<"ds_read_i8">;
522 defm DS_READ_U8 : DS_1A_RET_mc<"ds_read_u8">;
523 defm DS_READ_I16 : DS_1A_RET_mc<"ds_read_i16">;
524 defm DS_READ_U16 : DS_1A_RET_mc<"ds_read_u16">;
525 defm DS_READ_B32 : DS_1A_RET_mc<"ds_read_b32">;
526 defm DS_READ_B64 : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
528 defm DS_READ2_B32 : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
529 defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
531 defm DS_READ2_B64 : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
532 defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
534 let has_m0_read = 0 in {
535 let SubtargetPredicate = HasD16LoadStore in {
536 def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">;
537 def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
538 def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">;
539 def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
540 def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">;
541 def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
544 let SubtargetPredicate = HasDSAddTid in {
545 def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
547 } // End has_m0_read = 0
550 def DS_CONSUME : DS_0A_RET<"ds_consume">;
551 def DS_APPEND : DS_0A_RET<"ds_append">;
552 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
554 //===----------------------------------------------------------------------===//
555 // Instruction definitions for CI and newer.
556 //===----------------------------------------------------------------------===//
558 let SubtargetPredicate = isGFX7Plus in {
560 defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
561 defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
563 let isConvergent = 1, usesCustomInserter = 1 in {
564 def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
567 let mayStore = 0 in {
568 defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
569 defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
570 } // End mayStore = 0
573 defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
574 defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
577 def DS_NOP : DS_VOID<"ds_nop">;
579 } // let SubtargetPredicate = isGFX7Plus
581 //===----------------------------------------------------------------------===//
582 // Instruction definitions for VI and newer.
583 //===----------------------------------------------------------------------===//
585 let SubtargetPredicate = isGFX8Plus in {
587 let Uses = [EXEC] in {
588 def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
589 int_amdgcn_ds_permute>;
590 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
591 int_amdgcn_ds_bpermute>;
594 def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
596 } // let SubtargetPredicate = isGFX8Plus
598 //===----------------------------------------------------------------------===//
600 //===----------------------------------------------------------------------===//
603 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
604 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
607 class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
608 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
609 (inst $ptr, (as_i16imm $offset), (i1 gds))
612 multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
614 let OtherPredicates = [LDSRequiresM0Init] in {
615 def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
618 let OtherPredicates = [NotLDSRequiresM0Init] in {
619 def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
623 class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
624 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$in),
625 (inst $ptr, (as_i16imm $offset), (i1 0), $in)
628 defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
629 defm : DSReadPat_mc <DS_READ_I8, i16, "sextloadi8_local">;
630 defm : DSReadPat_mc <DS_READ_U8, i32, "extloadi8_local">;
631 defm : DSReadPat_mc <DS_READ_U8, i32, "zextloadi8_local">;
632 defm : DSReadPat_mc <DS_READ_U8, i16, "extloadi8_local">;
633 defm : DSReadPat_mc <DS_READ_U8, i16, "zextloadi8_local">;
634 defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
635 defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
636 defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
637 defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
638 defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
639 defm : DSReadPat_mc <DS_READ_B32, i32, "load_local">;
640 defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
641 defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
643 let AddedComplexity = 100 in {
645 defm : DSReadPat_mc <DS_READ_B64, v2i32, "load_align8_local">;
646 defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">;
648 } // End AddedComplexity = 100
650 let OtherPredicates = [D16PreservesUnusedBits] in {
651 def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
652 def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
653 def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
654 def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
655 def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
656 def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
658 def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
659 def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
660 def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
661 def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
662 def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
663 def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
666 class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
667 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
668 (inst $ptr, $value, (as_i16imm $offset), (i1 gds))
671 multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
672 let OtherPredicates = [LDSRequiresM0Init] in {
673 def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
676 let OtherPredicates = [NotLDSRequiresM0Init] in {
677 def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
681 // Irritatingly, atomic_store reverses the order of operands from a
683 class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
684 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
685 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
688 multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
689 let OtherPredicates = [LDSRequiresM0Init] in {
690 def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
693 let OtherPredicates = [NotLDSRequiresM0Init] in {
694 def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
698 defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
699 defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
700 defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
701 defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
702 defm : DSWritePat_mc <DS_WRITE_B32, i32, "store_local">;
703 defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local">;
704 defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local">;
706 let OtherPredicates = [D16PreservesUnusedBits] in {
707 def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
708 def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
712 class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, PatFrag frag> : GCNPat <
713 (v2i32 (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
714 (inst $ptr, $offset0, $offset1, (i1 0))
717 class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, PatFrag frag> : GCNPat<
718 (frag v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
719 (inst $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
720 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
724 // v2i32 loads are split into i32 loads on SI during lowering, due to a bug
725 // related to bounds checking.
726 let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
727 def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, load_local_m0>;
728 def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, store_local_m0>;
731 let OtherPredicates = [NotLDSRequiresM0Init] in {
732 def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, load_local>;
733 def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, store_local>;
737 let AddedComplexity = 100 in {
739 defm : DSWritePat_mc <DS_WRITE_B64, v2i32, "store_align8_local">;
740 defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
742 } // End AddedComplexity = 100
743 class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
744 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
745 (inst $ptr, $value, (as_i16imm $offset), (i1 gds))
748 multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
749 let OtherPredicates = [LDSRequiresM0Init] in {
750 def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0")>;
753 let OtherPredicates = [NotLDSRequiresM0Init] in {
754 def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
755 !cast<PatFrag>(frag#"_local")>;
758 def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0"), 1>;
763 class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
764 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
765 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 gds))
768 multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
769 let OtherPredicates = [LDSRequiresM0Init] in {
770 def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0")>;
773 let OtherPredicates = [NotLDSRequiresM0Init] in {
774 def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
775 !cast<PatFrag>(frag#"_local")>;
778 def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0"), 1>;
784 defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
785 defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
786 defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
787 defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
788 defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
789 defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
790 defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
791 defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
792 defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
793 defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
794 defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
795 defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
796 defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
797 defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
798 defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
799 defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
802 defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
803 defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
804 defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
805 defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
806 defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
807 defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
808 defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
809 defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
810 defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
811 defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
812 defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
813 defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
815 defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
818 (SIds_ordered_count i32:$value, i16:$offset),
819 (DS_ORDERED_COUNT $value, (as_i16imm $offset))
822 //===----------------------------------------------------------------------===//
823 // Target-specific instruction encodings.
824 //===----------------------------------------------------------------------===//
826 //===----------------------------------------------------------------------===//
827 // Base ENC_DS for GFX6, GFX7, GFX10.
828 //===----------------------------------------------------------------------===//
830 class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
831 DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
833 let Inst{7-0} = !if(ps.has_offset0, offset0, 0);
834 let Inst{15-8} = !if(ps.has_offset1, offset1, 0);
835 let Inst{17} = !if(ps.has_gds, gds, ps.gdsValue);
836 let Inst{25-18} = op;
837 let Inst{31-26} = 0x36;
838 let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0, 0));
839 let Inst{47-40} = !if(ps.has_data0, data0, 0);
840 let Inst{55-48} = !if(ps.has_data1, data1, 0);
841 let Inst{63-56} = !if(ps.has_vdst, vdst, 0);
844 //===----------------------------------------------------------------------===//
846 //===----------------------------------------------------------------------===//
848 let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
849 multiclass DS_Real_gfx10<bits<8> op> {
850 def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
851 SIEncodingFamily.GFX10>;
853 } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
855 defm DS_ADD_F32 : DS_Real_gfx10<0x015>;
856 defm DS_ADD_RTN_F32 : DS_Real_gfx10<0x055>;
857 defm DS_ADD_SRC2_F32 : DS_Real_gfx10<0x095>;
858 defm DS_WRITE_B8_D16_HI : DS_Real_gfx10<0x0a0>;
859 defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
860 defm DS_READ_U8_D16 : DS_Real_gfx10<0x0a2>;
861 defm DS_READ_U8_D16_HI : DS_Real_gfx10<0x0a3>;
862 defm DS_READ_I8_D16 : DS_Real_gfx10<0x0a4>;
863 defm DS_READ_I8_D16_HI : DS_Real_gfx10<0x0a5>;
864 defm DS_READ_U16_D16 : DS_Real_gfx10<0x0a6>;
865 defm DS_READ_U16_D16_HI : DS_Real_gfx10<0x0a7>;
866 defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
867 defm DS_READ_ADDTID_B32 : DS_Real_gfx10<0x0b1>;
868 defm DS_PERMUTE_B32 : DS_Real_gfx10<0x0b2>;
869 defm DS_BPERMUTE_B32 : DS_Real_gfx10<0x0b3>;
871 //===----------------------------------------------------------------------===//
873 //===----------------------------------------------------------------------===//
875 let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
876 multiclass DS_Real_gfx7<bits<8> op> {
877 def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
878 SIEncodingFamily.SI>;
880 } // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
882 multiclass DS_Real_gfx7_gfx10<bits<8> op> :
883 DS_Real_gfx7<op>, DS_Real_gfx10<op>;
885 // FIXME-GFX7: Add tests when upstreaming this part.
886 defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
887 defm DS_WRAP_RTN_B32 : DS_Real_gfx7_gfx10<0x034>;
888 defm DS_CONDXCHG32_RTN_B64 : DS_Real_gfx7_gfx10<0x07e>;
889 defm DS_WRITE_B96 : DS_Real_gfx7_gfx10<0x0de>;
890 defm DS_WRITE_B128 : DS_Real_gfx7_gfx10<0x0df>;
891 defm DS_READ_B96 : DS_Real_gfx7_gfx10<0x0fe>;
892 defm DS_READ_B128 : DS_Real_gfx7_gfx10<0x0ff>;
894 //===----------------------------------------------------------------------===//
895 // GFX6, GFX7, GFX10.
896 //===----------------------------------------------------------------------===//
898 let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
899 multiclass DS_Real_gfx6_gfx7<bits<8> op> {
900 def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
901 SIEncodingFamily.SI>;
903 } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
905 multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
906 DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
908 defm DS_ADD_U32 : DS_Real_gfx6_gfx7_gfx10<0x000>;
909 defm DS_SUB_U32 : DS_Real_gfx6_gfx7_gfx10<0x001>;
910 defm DS_RSUB_U32 : DS_Real_gfx6_gfx7_gfx10<0x002>;
911 defm DS_INC_U32 : DS_Real_gfx6_gfx7_gfx10<0x003>;
912 defm DS_DEC_U32 : DS_Real_gfx6_gfx7_gfx10<0x004>;
913 defm DS_MIN_I32 : DS_Real_gfx6_gfx7_gfx10<0x005>;
914 defm DS_MAX_I32 : DS_Real_gfx6_gfx7_gfx10<0x006>;
915 defm DS_MIN_U32 : DS_Real_gfx6_gfx7_gfx10<0x007>;
916 defm DS_MAX_U32 : DS_Real_gfx6_gfx7_gfx10<0x008>;
917 defm DS_AND_B32 : DS_Real_gfx6_gfx7_gfx10<0x009>;
918 defm DS_OR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00a>;
919 defm DS_XOR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00b>;
920 defm DS_MSKOR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00c>;
921 defm DS_WRITE_B32 : DS_Real_gfx6_gfx7_gfx10<0x00d>;
922 defm DS_WRITE2_B32 : DS_Real_gfx6_gfx7_gfx10<0x00e>;
923 defm DS_WRITE2ST64_B32 : DS_Real_gfx6_gfx7_gfx10<0x00f>;
924 defm DS_CMPST_B32 : DS_Real_gfx6_gfx7_gfx10<0x010>;
925 defm DS_CMPST_F32 : DS_Real_gfx6_gfx7_gfx10<0x011>;
926 defm DS_MIN_F32 : DS_Real_gfx6_gfx7_gfx10<0x012>;
927 defm DS_MAX_F32 : DS_Real_gfx6_gfx7_gfx10<0x013>;
928 defm DS_NOP : DS_Real_gfx6_gfx7_gfx10<0x014>;
929 defm DS_GWS_INIT : DS_Real_gfx6_gfx7_gfx10<0x019>;
930 defm DS_GWS_SEMA_V : DS_Real_gfx6_gfx7_gfx10<0x01a>;
931 defm DS_GWS_SEMA_BR : DS_Real_gfx6_gfx7_gfx10<0x01b>;
932 defm DS_GWS_SEMA_P : DS_Real_gfx6_gfx7_gfx10<0x01c>;
933 defm DS_GWS_BARRIER : DS_Real_gfx6_gfx7_gfx10<0x01d>;
934 defm DS_WRITE_B8 : DS_Real_gfx6_gfx7_gfx10<0x01e>;
935 defm DS_WRITE_B16 : DS_Real_gfx6_gfx7_gfx10<0x01f>;
936 defm DS_ADD_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x020>;
937 defm DS_SUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x021>;
938 defm DS_RSUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x022>;
939 defm DS_INC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x023>;
940 defm DS_DEC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x024>;
941 defm DS_MIN_RTN_I32 : DS_Real_gfx6_gfx7_gfx10<0x025>;
942 defm DS_MAX_RTN_I32 : DS_Real_gfx6_gfx7_gfx10<0x026>;
943 defm DS_MIN_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x027>;
944 defm DS_MAX_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x028>;
945 defm DS_AND_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x029>;
946 defm DS_OR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02a>;
947 defm DS_XOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02b>;
948 defm DS_MSKOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02c>;
949 defm DS_WRXCHG_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02d>;
950 defm DS_WRXCHG2_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02e>;
951 defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
952 defm DS_CMPST_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x030>;
953 defm DS_CMPST_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x031>;
954 defm DS_MIN_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x032>;
955 defm DS_MAX_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x033>;
956 defm DS_SWIZZLE_B32 : DS_Real_gfx6_gfx7_gfx10<0x035>;
957 defm DS_READ_B32 : DS_Real_gfx6_gfx7_gfx10<0x036>;
958 defm DS_READ2_B32 : DS_Real_gfx6_gfx7_gfx10<0x037>;
959 defm DS_READ2ST64_B32 : DS_Real_gfx6_gfx7_gfx10<0x038>;
960 defm DS_READ_I8 : DS_Real_gfx6_gfx7_gfx10<0x039>;
961 defm DS_READ_U8 : DS_Real_gfx6_gfx7_gfx10<0x03a>;
962 defm DS_READ_I16 : DS_Real_gfx6_gfx7_gfx10<0x03b>;
963 defm DS_READ_U16 : DS_Real_gfx6_gfx7_gfx10<0x03c>;
964 defm DS_CONSUME : DS_Real_gfx6_gfx7_gfx10<0x03d>;
965 defm DS_APPEND : DS_Real_gfx6_gfx7_gfx10<0x03e>;
966 defm DS_ORDERED_COUNT : DS_Real_gfx6_gfx7_gfx10<0x03f>;
967 defm DS_ADD_U64 : DS_Real_gfx6_gfx7_gfx10<0x040>;
968 defm DS_SUB_U64 : DS_Real_gfx6_gfx7_gfx10<0x041>;
969 defm DS_RSUB_U64 : DS_Real_gfx6_gfx7_gfx10<0x042>;
970 defm DS_INC_U64 : DS_Real_gfx6_gfx7_gfx10<0x043>;
971 defm DS_DEC_U64 : DS_Real_gfx6_gfx7_gfx10<0x044>;
972 defm DS_MIN_I64 : DS_Real_gfx6_gfx7_gfx10<0x045>;
973 defm DS_MAX_I64 : DS_Real_gfx6_gfx7_gfx10<0x046>;
974 defm DS_MIN_U64 : DS_Real_gfx6_gfx7_gfx10<0x047>;
975 defm DS_MAX_U64 : DS_Real_gfx6_gfx7_gfx10<0x048>;
976 defm DS_AND_B64 : DS_Real_gfx6_gfx7_gfx10<0x049>;
977 defm DS_OR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04a>;
978 defm DS_XOR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04b>;
979 defm DS_MSKOR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04c>;
980 defm DS_WRITE_B64 : DS_Real_gfx6_gfx7_gfx10<0x04d>;
981 defm DS_WRITE2_B64 : DS_Real_gfx6_gfx7_gfx10<0x04e>;
982 defm DS_WRITE2ST64_B64 : DS_Real_gfx6_gfx7_gfx10<0x04f>;
983 defm DS_CMPST_B64 : DS_Real_gfx6_gfx7_gfx10<0x050>;
984 defm DS_CMPST_F64 : DS_Real_gfx6_gfx7_gfx10<0x051>;
985 defm DS_MIN_F64 : DS_Real_gfx6_gfx7_gfx10<0x052>;
986 defm DS_MAX_F64 : DS_Real_gfx6_gfx7_gfx10<0x053>;
987 defm DS_ADD_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x060>;
988 defm DS_SUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x061>;
989 defm DS_RSUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x062>;
990 defm DS_INC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x063>;
991 defm DS_DEC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x064>;
992 defm DS_MIN_RTN_I64 : DS_Real_gfx6_gfx7_gfx10<0x065>;
993 defm DS_MAX_RTN_I64 : DS_Real_gfx6_gfx7_gfx10<0x066>;
994 defm DS_MIN_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x067>;
995 defm DS_MAX_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x068>;
996 defm DS_AND_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x069>;
997 defm DS_OR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06a>;
998 defm DS_XOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06b>;
999 defm DS_MSKOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1000 defm DS_WRXCHG_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1001 defm DS_WRXCHG2_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1002 defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1003 defm DS_CMPST_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x070>;
1004 defm DS_CMPST_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x071>;
1005 defm DS_MIN_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x072>;
1006 defm DS_MAX_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x073>;
1007 defm DS_READ_B64 : DS_Real_gfx6_gfx7_gfx10<0x076>;
1008 defm DS_READ2_B64 : DS_Real_gfx6_gfx7_gfx10<0x077>;
1009 defm DS_READ2ST64_B64 : DS_Real_gfx6_gfx7_gfx10<0x078>;
1010 defm DS_ADD_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x080>;
1011 defm DS_SUB_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x081>;
1012 defm DS_RSUB_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x082>;
1013 defm DS_INC_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x083>;
1014 defm DS_DEC_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x084>;
1015 defm DS_MIN_SRC2_I32 : DS_Real_gfx6_gfx7_gfx10<0x085>;
1016 defm DS_MAX_SRC2_I32 : DS_Real_gfx6_gfx7_gfx10<0x086>;
1017 defm DS_MIN_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x087>;
1018 defm DS_MAX_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x088>;
1019 defm DS_AND_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x089>;
1020 defm DS_OR_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1021 defm DS_XOR_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1022 defm DS_WRITE_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1023 defm DS_MIN_SRC2_F32 : DS_Real_gfx6_gfx7_gfx10<0x092>;
1024 defm DS_MAX_SRC2_F32 : DS_Real_gfx6_gfx7_gfx10<0x093>;
1025 defm DS_ADD_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1026 defm DS_SUB_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1027 defm DS_RSUB_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1028 defm DS_INC_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1029 defm DS_DEC_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1030 defm DS_MIN_SRC2_I64 : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1031 defm DS_MAX_SRC2_I64 : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1032 defm DS_MIN_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1033 defm DS_MAX_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1034 defm DS_AND_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1035 defm DS_OR_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1036 defm DS_XOR_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1037 defm DS_WRITE_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1038 defm DS_MIN_SRC2_F64 : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1039 defm DS_MAX_SRC2_F64 : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1041 //===----------------------------------------------------------------------===//
1043 //===----------------------------------------------------------------------===//
1045 class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
1047 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
1048 let AssemblerPredicates = [isGFX8GFX9];
1049 let DecoderNamespace = "GFX8";
1052 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
1053 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
1054 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
1055 let Inst{24-17} = op;
1056 let Inst{31-26} = 0x36; // ds prefix
1057 let Inst{39-32} = !if(ds.has_addr, addr, !if(ds.has_gws_data0, data0, 0));
1058 let Inst{47-40} = !if(ds.has_data0, data0, 0);
1059 let Inst{55-48} = !if(ds.has_data1, data1, 0);
1060 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
1063 def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
1064 def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
1065 def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
1066 def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
1067 def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
1068 def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
1069 def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
1070 def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
1071 def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
1072 def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
1073 def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
1074 def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
1075 def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
1076 def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
1077 def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
1078 def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
1079 def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
1080 def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
1081 def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
1082 def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
1083 def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
1084 def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
1085 def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
1086 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1087 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1088 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1089 def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1090 def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1091 def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
1092 def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
1093 def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1094 def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1095 def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1096 def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1097 def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1098 def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1099 def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1100 def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1101 def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1102 def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1103 def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1104 def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1105 def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1106 def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1107 def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1108 def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1109 def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1110 def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1111 def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1112 def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1113 def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1114 def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1115 def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
1116 def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
1117 def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1118 def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
1119 def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
1120 def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
1121 def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
1122 def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1123 def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
1124 def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
1125 def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1126 def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1127 def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1128 def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1130 def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
1131 def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
1132 def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
1133 def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
1134 def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
1135 def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
1136 def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
1137 def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
1138 def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
1139 def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
1140 def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
1141 def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
1142 def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1143 def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
1144 def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1145 def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1146 def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
1147 def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
1148 def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
1149 def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
1151 def DS_WRITE_B8_D16_HI_vi : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1152 def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1154 def DS_READ_U8_D16_vi : DS_Real_vi<0x56, DS_READ_U8_D16>;
1155 def DS_READ_U8_D16_HI_vi : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1156 def DS_READ_I8_D16_vi : DS_Real_vi<0x58, DS_READ_I8_D16>;
1157 def DS_READ_I8_D16_HI_vi : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1158 def DS_READ_U16_D16_vi : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1159 def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1161 def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1162 def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1163 def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1164 def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1165 def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1166 def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1167 def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1168 def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1169 def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1170 def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1171 def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1172 def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1173 def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1174 def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1175 def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1176 def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1177 def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1178 def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1179 def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1180 def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1181 def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1182 def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1184 def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
1185 def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
1186 def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1188 def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1189 def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1190 def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1191 def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1192 def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1193 def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1194 def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1195 def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1196 def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1197 def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1198 def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1199 def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1200 def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1201 def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1202 def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1203 def DS_ADD_SRC2_F32_vi : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1204 def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1205 def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1206 def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1207 def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1208 def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1209 def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1210 def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1211 def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1212 def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1213 def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1214 def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1215 def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1216 def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1217 def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1218 def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1219 def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
1220 def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
1221 def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
1222 def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;