1 //===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are:
11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs
12 // - Available only on Evergreen family GPUs.
14 //===----------------------------------------------------------------------===//
17 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
18 "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
19 "!Subtarget->hasCaymanISA()"
22 def isEGorCayman : Predicate<
23 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
24 "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS"
27 //===----------------------------------------------------------------------===//
28 // Evergreen / Cayman store instructions
29 //===----------------------------------------------------------------------===//
31 let Predicates = [isEGorCayman] in {
33 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
34 string name, list<dag> pattern>
35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
36 "MEM_RAT_CACHELESS "#name, pattern>;
38 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
39 dag outs, string name, list<dag> pattern>
40 : EG_CF_RAT <0x56, rat_inst, rat_id, mask, outs, ins,
41 "MEM_RAT "#name, pattern>;
43 class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop>
44 : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr,
45 i32imm:$rat_id, InstFlag:$eop), (outs),
46 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr"
47 #!if(has_eop, ", $eop", ""),
48 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr,
49 R600_Reg128:$index_gpr,
52 def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 0xf,
53 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs),
54 "MSKOR $rw_gpr.XW, $index_gpr",
55 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
61 multiclass RAT_ATOMIC<bits<6> op_ret, bits<6> op_noret, string name> {
62 let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in {
63 def _RTN: CF_MEM_RAT <op_ret, 0, 0xf,
64 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
65 (outs R600_Reg128:$out_gpr),
66 name ## "_RTN" ## " $rw_gpr, $index_gpr", [] >;
67 def _NORET: CF_MEM_RAT <op_noret, 0, 0xf,
68 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
69 (outs R600_Reg128:$out_gpr),
70 name ## " $rw_gpr, $index_gpr", [] >;
74 // Swap no-ret is just store. Raw store to cached target
75 // can only store on dword, which exactly matches swap_no_ret.
76 defm RAT_ATOMIC_XCHG_INT : RAT_ATOMIC<1, 34, "ATOMIC_XCHG_INT">;
77 defm RAT_ATOMIC_CMPXCHG_INT : RAT_ATOMIC<4, 36, "ATOMIC_CMPXCHG_INT">;
78 defm RAT_ATOMIC_ADD : RAT_ATOMIC<7, 39, "ATOMIC_ADD">;
79 defm RAT_ATOMIC_SUB : RAT_ATOMIC<8, 40, "ATOMIC_SUB">;
80 defm RAT_ATOMIC_RSUB : RAT_ATOMIC<9, 41, "ATOMIC_RSUB">;
81 defm RAT_ATOMIC_MIN_INT : RAT_ATOMIC<10, 42, "ATOMIC_MIN_INT">;
82 defm RAT_ATOMIC_MIN_UINT : RAT_ATOMIC<11, 43, "ATOMIC_MIN_UINT">;
83 defm RAT_ATOMIC_MAX_INT : RAT_ATOMIC<12, 44, "ATOMIC_MAX_INT">;
84 defm RAT_ATOMIC_MAX_UINT : RAT_ATOMIC<13, 45, "ATOMIC_MAX_UINT">;
85 defm RAT_ATOMIC_AND : RAT_ATOMIC<14, 46, "ATOMIC_AND">;
86 defm RAT_ATOMIC_OR : RAT_ATOMIC<15, 47, "ATOMIC_OR">;
87 defm RAT_ATOMIC_XOR : RAT_ATOMIC<16, 48, "ATOMIC_XOR">;
88 defm RAT_ATOMIC_INC_UINT : RAT_ATOMIC<18, 50, "ATOMIC_INC_UINT">;
89 defm RAT_ATOMIC_DEC_UINT : RAT_ATOMIC<19, 51, "ATOMIC_DEC_UINT">;
91 } // End let Predicates = [isEGorCayman]
93 //===----------------------------------------------------------------------===//
94 // Evergreen Only instructions
95 //===----------------------------------------------------------------------===//
97 let Predicates = [isEG] in {
99 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
100 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
102 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
103 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
104 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
105 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
106 def MULHI_UINT24_eg : MULHI_UINT24_Common<0xb2>;
108 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
109 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
110 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
111 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
112 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
113 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
114 def : RsqPat<RECIPSQRT_IEEE_eg, f32>;
115 def SIN_eg : SIN_Common<0x8D>;
116 def COS_eg : COS_Common<0x8E>;
118 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
119 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
121 //===----------------------------------------------------------------------===//
122 // Memory read/write instructions
123 //===----------------------------------------------------------------------===//
125 let usesCustomInserter = 1 in {
128 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
129 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
130 "STORE_RAW $rw_gpr, $index_gpr, $eop",
131 [(global_store i32:$rw_gpr, i32:$index_gpr)]
135 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
136 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
137 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
138 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
142 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
143 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
144 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
145 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
148 def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>;
150 } // End usesCustomInserter = 1
152 class VTX_READ_eg <string name, dag outs>
153 : VTX_WORD0_eg, VTX_READ<name, outs, []> {
158 let FETCH_WHOLE_QUAD = 0;
160 // XXX: We can infer this field based on the SRC_GPR. This would allow us
161 // to store vertex addresses in any channel, not just X.
164 let Inst{31-0} = Word0;
168 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr",
169 (outs R600_TReg32_X:$dst_gpr)> {
171 let MEGA_FETCH_COUNT = 1;
173 let DST_SEL_Y = 7; // Masked
174 let DST_SEL_Z = 7; // Masked
175 let DST_SEL_W = 7; // Masked
176 let DATA_FORMAT = 1; // FMT_8
180 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr",
181 (outs R600_TReg32_X:$dst_gpr)> {
182 let MEGA_FETCH_COUNT = 2;
184 let DST_SEL_Y = 7; // Masked
185 let DST_SEL_Z = 7; // Masked
186 let DST_SEL_W = 7; // Masked
187 let DATA_FORMAT = 5; // FMT_16
192 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr",
193 (outs R600_TReg32_X:$dst_gpr)> {
195 let MEGA_FETCH_COUNT = 4;
197 let DST_SEL_Y = 7; // Masked
198 let DST_SEL_Z = 7; // Masked
199 let DST_SEL_W = 7; // Masked
200 let DATA_FORMAT = 0xD; // COLOR_32
202 // This is not really necessary, but there were some GPU hangs that appeared
203 // to be caused by ALU instructions in the next instruction group that wrote
204 // to the $src_gpr registers of the VTX_READ.
206 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
207 // %T2_X<def> = MOV %ZERO
208 //Adding this constraint prevents this from happening.
209 let Constraints = "$src_gpr.ptr = $dst_gpr";
213 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr",
214 (outs R600_Reg64:$dst_gpr)> {
216 let MEGA_FETCH_COUNT = 8;
221 let DATA_FORMAT = 0x1D; // COLOR_32_32
225 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",
226 (outs R600_Reg128:$dst_gpr)> {
228 let MEGA_FETCH_COUNT = 16;
233 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
235 // XXX: Need to force VTX_READ_128 instructions to write to the same register
236 // that holds its buffer address to avoid potential hangs. We can't use
237 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
238 // registers are different sizes.
241 //===----------------------------------------------------------------------===//
242 // VTX Read from parameter memory space
243 //===----------------------------------------------------------------------===//
244 def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),
245 (VTX_READ_8_eg MEMxi:$src_gpr, 3)>;
246 def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),
247 (VTX_READ_16_eg MEMxi:$src_gpr, 3)>;
248 def : Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
249 (VTX_READ_32_eg MEMxi:$src_gpr, 3)>;
250 def : Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
251 (VTX_READ_64_eg MEMxi:$src_gpr, 3)>;
252 def : Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
253 (VTX_READ_128_eg MEMxi:$src_gpr, 3)>;
255 //===----------------------------------------------------------------------===//
256 // VTX Read from constant memory space
257 //===----------------------------------------------------------------------===//
258 def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),
259 (VTX_READ_8_eg MEMxi:$src_gpr, 2)>;
260 def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),
261 (VTX_READ_16_eg MEMxi:$src_gpr, 2)>;
262 def : Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
263 (VTX_READ_32_eg MEMxi:$src_gpr, 2)>;
264 def : Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
265 (VTX_READ_64_eg MEMxi:$src_gpr, 2)>;
266 def : Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
267 (VTX_READ_128_eg MEMxi:$src_gpr, 2)>;
269 //===----------------------------------------------------------------------===//
270 // VTX Read from global memory space
271 //===----------------------------------------------------------------------===//
272 def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),
273 (VTX_READ_8_eg MEMxi:$src_gpr, 1)>;
274 def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),
275 (VTX_READ_16_eg MEMxi:$src_gpr, 1)>;
276 def : Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
277 (VTX_READ_32_eg MEMxi:$src_gpr, 1)>;
278 def : Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
279 (VTX_READ_64_eg MEMxi:$src_gpr, 1)>;
280 def : Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
281 (VTX_READ_128_eg MEMxi:$src_gpr, 1)>;
283 } // End Predicates = [isEG]
285 //===----------------------------------------------------------------------===//
286 // Evergreen / Cayman Instructions
287 //===----------------------------------------------------------------------===//
289 let Predicates = [isEGorCayman] in {
291 multiclass AtomicPat<Instruction inst_ret, Instruction inst_noret,
292 SDPatternOperator node_ret, SDPatternOperator node_noret> {
293 // FIXME: Add _RTN version. We need per WI scratch location to store the old value
294 // EXTRACT_SUBREG here is dummy, we know the node has no uses
295 def : Pat<(i32 (node_noret i32:$ptr, i32:$data)),
296 (EXTRACT_SUBREG (inst_noret
297 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>;
299 multiclass AtomicIncDecPat<Instruction inst_ret, Instruction inst_noret,
300 SDPatternOperator node_ret, SDPatternOperator node_noret, int C> {
301 // FIXME: Add _RTN version. We need per WI scratch location to store the old value
302 // EXTRACT_SUBREG here is dummy, we know the node has no uses
303 def : Pat<(i32 (node_noret i32:$ptr, C)),
304 (EXTRACT_SUBREG (inst_noret
305 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (MOV_IMM_I32 -1), sub0), $ptr), sub1)>;
308 // CMPSWAP is pattern is special
309 // EXTRACT_SUBREG here is dummy, we know the node has no uses
310 // FIXME: Add _RTN version. We need per WI scratch location to store the old value
311 def : Pat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)),
312 (EXTRACT_SUBREG (RAT_ATOMIC_CMPXCHG_INT_NORET
314 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $cmp, sub3),
318 defm AtomicSwapPat : AtomicPat <RAT_ATOMIC_XCHG_INT_RTN,
319 RAT_ATOMIC_XCHG_INT_NORET,
320 atomic_swap_global_ret,
321 atomic_swap_global_noret>;
322 defm AtomicAddPat : AtomicPat <RAT_ATOMIC_ADD_RTN, RAT_ATOMIC_ADD_NORET,
323 atomic_add_global_ret, atomic_add_global_noret>;
324 defm AtomicSubPat : AtomicPat <RAT_ATOMIC_SUB_RTN, RAT_ATOMIC_SUB_NORET,
325 atomic_sub_global_ret, atomic_sub_global_noret>;
326 defm AtomicMinPat : AtomicPat <RAT_ATOMIC_MIN_INT_RTN,
327 RAT_ATOMIC_MIN_INT_NORET,
328 atomic_min_global_ret, atomic_min_global_noret>;
329 defm AtomicUMinPat : AtomicPat <RAT_ATOMIC_MIN_UINT_RTN,
330 RAT_ATOMIC_MIN_UINT_NORET,
331 atomic_umin_global_ret, atomic_umin_global_noret>;
332 defm AtomicMaxPat : AtomicPat <RAT_ATOMIC_MAX_INT_RTN,
333 RAT_ATOMIC_MAX_INT_NORET,
334 atomic_max_global_ret, atomic_max_global_noret>;
335 defm AtomicUMaxPat : AtomicPat <RAT_ATOMIC_MAX_UINT_RTN,
336 RAT_ATOMIC_MAX_UINT_NORET,
337 atomic_umax_global_ret, atomic_umax_global_noret>;
338 defm AtomicAndPat : AtomicPat <RAT_ATOMIC_AND_RTN, RAT_ATOMIC_AND_NORET,
339 atomic_and_global_ret, atomic_and_global_noret>;
340 defm AtomicOrPat : AtomicPat <RAT_ATOMIC_OR_RTN, RAT_ATOMIC_OR_NORET,
341 atomic_or_global_ret, atomic_or_global_noret>;
342 defm AtomicXorPat : AtomicPat <RAT_ATOMIC_XOR_RTN, RAT_ATOMIC_XOR_NORET,
343 atomic_xor_global_ret, atomic_xor_global_noret>;
344 defm AtomicIncAddPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN,
345 RAT_ATOMIC_INC_UINT_NORET,
346 atomic_add_global_ret,
347 atomic_add_global_noret, 1>;
348 defm AtomicIncSubPat : AtomicIncDecPat <RAT_ATOMIC_INC_UINT_RTN,
349 RAT_ATOMIC_INC_UINT_NORET,
350 atomic_sub_global_ret,
351 atomic_sub_global_noret, -1>;
352 defm AtomicDecAddPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN,
353 RAT_ATOMIC_DEC_UINT_NORET,
354 atomic_add_global_ret,
355 atomic_add_global_noret, -1>;
356 defm AtomicDecSubPat : AtomicIncDecPat <RAT_ATOMIC_DEC_UINT_RTN,
357 RAT_ATOMIC_DEC_UINT_NORET,
358 atomic_sub_global_ret,
359 atomic_sub_global_noret, 1>;
361 // Should be predicated on FeatureFP64
362 // def FMA_64 : R600_3OP <
364 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
367 // BFE_UINT - bit_extract, an optimization for mask and shift
372 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
377 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
378 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
379 // (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
380 // (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
381 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
382 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
386 def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
387 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
391 defm : BFEPattern <BFE_UINT_eg, BFE_INT_eg, MOV_IMM_I32>;
393 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
394 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
398 def : Pat<(i32 (sext_inreg i32:$src, i1)),
399 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;
400 def : Pat<(i32 (sext_inreg i32:$src, i8)),
401 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;
402 def : Pat<(i32 (sext_inreg i32:$src, i16)),
403 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;
405 defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>;
407 def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
408 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
412 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
413 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
416 def : UMad24Pat<MULADD_UINT24_eg>;
418 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
419 def : ROTRPattern <BIT_ALIGN_INT_eg>;
420 def MULADD_eg : MULADD_Common<0x14>;
421 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
422 def FMA_eg : FMA_Common<0x7>;
423 def ASHR_eg : ASHR_Common<0x15>;
424 def LSHR_eg : LSHR_Common<0x16>;
425 def LSHL_eg : LSHL_Common<0x17>;
426 def CNDE_eg : CNDE_Common<0x19>;
427 def CNDGT_eg : CNDGT_Common<0x1A>;
428 def CNDGE_eg : CNDGE_Common<0x1B>;
429 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
430 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
431 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
432 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
434 def DOT4_eg : DOT4_Common<0xBE>;
435 defm CUBE_eg : CUBE_Common<0xC0>;
438 def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>;
439 def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>;
441 def FLT32_TO_FLT16 : R600_1OP_Helper <0xA2, "FLT32_TO_FLT16", AMDGPUfp_to_f16, VecALU>;
442 def FLT16_TO_FLT32 : R600_1OP_Helper <0xA3, "FLT16_TO_FLT32", f16_to_fp, VecALU>;
443 def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>;
444 def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>;
445 def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>;
447 let hasSideEffects = 1 in {
448 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
451 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
453 let Itinerary = AnyALU;
456 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
458 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
462 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
464 def GROUP_BARRIER : InstR600 <
465 (outs), (ins), " GROUP_BARRIER", [(int_r600_group_barrier)], AnyALU>,
467 R600ALU_Word1_OP2 <0x54> {
483 let bank_swizzle = 0;
485 let update_exec_mask = 0;
488 let Inst{31-0} = Word0;
489 let Inst{63-32} = Word1;
494 //===----------------------------------------------------------------------===//
496 //===----------------------------------------------------------------------===//
497 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
498 list<dag> pattern = []> :
500 InstR600 <outs, ins, asm, pattern, XALU>,
507 let Word1{27} = offset{0};
508 let Word1{12} = offset{1};
509 let Word1{28} = offset{2};
510 let Word1{31} = offset{3};
511 let Word0{12} = offset{4};
512 let Word0{25} = offset{5};
515 let Inst{31-0} = Word0;
516 let Inst{63-32} = Word1;
519 let HasNativeOperands = 1;
520 let UseNamedOperandTable = 1;
523 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
525 (outs R600_Reg32:$dst),
526 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
527 LAST:$last, R600_Pred:$pred_sel,
528 BANK_SWIZZLE:$bank_swizzle),
529 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
538 let usesCustomInserter = 1;
540 let DisableEncoding = "$dst";
543 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
547 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
548 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
549 LAST:$last, R600_Pred:$pred_sel,
550 BANK_SWIZZLE:$bank_swizzle),
551 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
562 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
563 R600_LDS_1A1D <lds_op, (outs), name, pattern> {
567 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
568 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
571 let usesCustomInserter = 1;
572 let DisableEncoding = "$dst";
575 class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
579 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
580 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
581 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
582 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
583 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
592 class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
593 R600_LDS_1A2D <lds_op, (outs), name, pattern> {
597 class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> :
598 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> {
601 let usesCustomInserter = 1;
602 let DisableEncoding = "$dst";
605 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
606 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
607 def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >;
608 def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >;
609 def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >;
610 def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >;
611 def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >;
612 def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >;
613 def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >;
614 def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >;
615 def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >;
616 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
617 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
619 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
620 [(truncstorei8_local i32:$src1, i32:$src0)]
622 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
623 [(truncstorei16_local i32:$src1, i32:$src0)]
625 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
626 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
628 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
629 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
631 def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND",
632 [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))]
634 def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR",
635 [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))]
637 def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR",
638 [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))]
640 def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT",
641 [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))]
643 def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT",
644 [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))]
646 def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT",
647 [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))]
649 def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT",
650 [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))]
652 def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG",
653 [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))]
655 def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST",
656 [(set i32:$dst, (atomic_cmp_swap_32_local i32:$src0, i32:$src1, i32:$src2))]
658 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
659 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
661 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
662 [(set i32:$dst, (sextloadi8_local i32:$src0))]
664 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
665 [(set i32:$dst, (az_extloadi8_local i32:$src0))]
667 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
668 [(set i32:$dst, (sextloadi16_local i32:$src0))]
670 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
671 [(set i32:$dst, (az_extloadi16_local i32:$src0))]
674 // TRUNC is used for the FLT_TO_INT instructions to work around a
675 // perceived problem where the rounding modes are applied differently
676 // depending on the instruction and the slot they are in.
678 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
679 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
681 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
682 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
683 // We should look into handling these cases separately.
684 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
686 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
689 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
691 def EG_ExportSwz : ExportSwzInst {
692 let Word1{19-16} = 0; // BURST_COUNT
693 let Word1{20} = 0; // VALID_PIXEL_MODE
695 let Word1{29-22} = inst;
696 let Word1{30} = 0; // MARK
697 let Word1{31} = 1; // BARRIER
699 defm : ExportPattern<EG_ExportSwz, 83>;
701 def EG_ExportBuf : ExportBufInst {
702 let Word1{19-16} = 0; // BURST_COUNT
703 let Word1{20} = 0; // VALID_PIXEL_MODE
705 let Word1{29-22} = inst;
706 let Word1{30} = 0; // MARK
707 let Word1{31} = 1; // BARRIER
709 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
711 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
712 "TEX $COUNT @$ADDR"> {
715 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
716 "VTX $COUNT @$ADDR"> {
719 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
720 "LOOP_START_DX10 @$ADDR"> {
724 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
728 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
729 "LOOP_BREAK @$ADDR"> {
733 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
738 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
739 "JUMP @$ADDR POP:$POP_COUNT"> {
742 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
743 "PUSH @$ADDR POP:$POP_COUNT"> {
746 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
747 "ELSE @$ADDR POP:$POP_COUNT"> {
750 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
755 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
756 "POP @$ADDR POP:$POP_COUNT"> {
759 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
763 let END_OF_PROGRAM = 1;
766 } // End Predicates = [isEGorCayman]