1 //===-- FLATInstructions.td - FLAT Instruction Defintions -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def FLATAtomic : ComplexPattern<i64, 3, "SelectFlat">;
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 class FLAT_Pseudo<string opName, dag outs, dag ins,
17 string asmOps, list<dag> pattern=[]> :
18 InstSI<outs, ins, "", pattern>,
19 SIMCInstr<opName, SIEncodingFamily.NONE> {
22 let isCodeGenOnly = 1;
24 let SubtargetPredicate = isCIVI;
27 // Internally, FLAT instruction are executed as both an LDS and a
28 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
29 // and are not considered done until both have been decremented.
33 let Uses = [EXEC, FLAT_SCR]; // M0
35 let UseNamedOperandTable = 1;
36 let hasSideEffects = 0;
37 let SchedRW = [WriteVMEM];
39 string Mnemonic = opName;
40 string AsmOperands = asmOps;
48 class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
49 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
53 let isCodeGenOnly = 0;
55 // copy relevant pseudo op flags
56 let SubtargetPredicate = ps.SubtargetPredicate;
57 let AsmMatchConverter = ps.AsmMatchConverter;
68 let Inst{16} = !if(ps.has_glc, glc, ps.glcValue);
71 let Inst{31-26} = 0x37; // Encoding.
72 let Inst{39-32} = vaddr;
73 let Inst{47-40} = !if(ps.has_data, vdata, ?);
76 let Inst{63-56} = !if(ps.has_vdst, vdst, ?);
79 class FLAT_Load_Pseudo <string opName, RegisterClass regClass> : FLAT_Pseudo<
81 (outs regClass:$vdst),
82 (ins VReg_64:$vaddr, GLC:$glc, slc:$slc, tfe:$tfe),
83 " $vdst, $vaddr$glc$slc$tfe"> {
88 class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass> : FLAT_Pseudo<
91 (ins VReg_64:$vaddr, vdataClass:$vdata, GLC:$glc, slc:$slc, tfe:$tfe),
92 " $vaddr, $vdata$glc$slc$tfe"> {
98 multiclass FLAT_Atomic_Pseudo<
100 RegisterClass vdst_rc,
102 SDPatternOperator atomic = null_frag,
103 ValueType data_vt = vt,
104 RegisterClass data_rc = vdst_rc> {
106 def "" : FLAT_Pseudo <opName,
108 (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc, tfe:$tfe),
109 " $vaddr, $vdata$slc$tfe",
111 AtomicNoRet <NAME, 0> {
117 let PseudoInstr = NAME;
120 def _RTN : FLAT_Pseudo <opName,
121 (outs vdst_rc:$vdst),
122 (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc, tfe:$tfe),
123 " $vdst, $vaddr, $vdata glc$slc$tfe",
125 (atomic (FLATAtomic i64:$vaddr, i1:$slc, i1:$tfe), data_vt:$vdata))]>,
126 AtomicNoRet <NAME, 1> {
129 let hasPostISelHook = 1;
132 let PseudoInstr = NAME # "_RTN";
136 class flat_binary_atomic_op<SDNode atomic_op> : PatFrag<
137 (ops node:$ptr, node:$value),
138 (atomic_op node:$ptr, node:$value),
139 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;}]
142 def atomic_cmp_swap_flat : flat_binary_atomic_op<AMDGPUatomic_cmp_swap>;
143 def atomic_swap_flat : flat_binary_atomic_op<atomic_swap>;
144 def atomic_add_flat : flat_binary_atomic_op<atomic_load_add>;
145 def atomic_and_flat : flat_binary_atomic_op<atomic_load_and>;
146 def atomic_max_flat : flat_binary_atomic_op<atomic_load_max>;
147 def atomic_min_flat : flat_binary_atomic_op<atomic_load_min>;
148 def atomic_or_flat : flat_binary_atomic_op<atomic_load_or>;
149 def atomic_sub_flat : flat_binary_atomic_op<atomic_load_sub>;
150 def atomic_umax_flat : flat_binary_atomic_op<atomic_load_umax>;
151 def atomic_umin_flat : flat_binary_atomic_op<atomic_load_umin>;
152 def atomic_xor_flat : flat_binary_atomic_op<atomic_load_xor>;
153 def atomic_inc_flat : flat_binary_atomic_op<SIatomic_inc>;
154 def atomic_dec_flat : flat_binary_atomic_op<SIatomic_dec>;
158 //===----------------------------------------------------------------------===//
160 //===----------------------------------------------------------------------===//
162 def FLAT_LOAD_UBYTE : FLAT_Load_Pseudo <"flat_load_ubyte", VGPR_32>;
163 def FLAT_LOAD_SBYTE : FLAT_Load_Pseudo <"flat_load_sbyte", VGPR_32>;
164 def FLAT_LOAD_USHORT : FLAT_Load_Pseudo <"flat_load_ushort", VGPR_32>;
165 def FLAT_LOAD_SSHORT : FLAT_Load_Pseudo <"flat_load_sshort", VGPR_32>;
166 def FLAT_LOAD_DWORD : FLAT_Load_Pseudo <"flat_load_dword", VGPR_32>;
167 def FLAT_LOAD_DWORDX2 : FLAT_Load_Pseudo <"flat_load_dwordx2", VReg_64>;
168 def FLAT_LOAD_DWORDX4 : FLAT_Load_Pseudo <"flat_load_dwordx4", VReg_128>;
169 def FLAT_LOAD_DWORDX3 : FLAT_Load_Pseudo <"flat_load_dwordx3", VReg_96>;
171 def FLAT_STORE_BYTE : FLAT_Store_Pseudo <"flat_store_byte", VGPR_32>;
172 def FLAT_STORE_SHORT : FLAT_Store_Pseudo <"flat_store_short", VGPR_32>;
173 def FLAT_STORE_DWORD : FLAT_Store_Pseudo <"flat_store_dword", VGPR_32>;
174 def FLAT_STORE_DWORDX2 : FLAT_Store_Pseudo <"flat_store_dwordx2", VReg_64>;
175 def FLAT_STORE_DWORDX4 : FLAT_Store_Pseudo <"flat_store_dwordx4", VReg_128>;
176 def FLAT_STORE_DWORDX3 : FLAT_Store_Pseudo <"flat_store_dwordx3", VReg_96>;
178 defm FLAT_ATOMIC_CMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap",
179 VGPR_32, i32, atomic_cmp_swap_flat,
182 defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap_x2",
183 VReg_64, i64, atomic_cmp_swap_flat,
186 defm FLAT_ATOMIC_SWAP : FLAT_Atomic_Pseudo <"flat_atomic_swap",
187 VGPR_32, i32, atomic_swap_flat>;
189 defm FLAT_ATOMIC_SWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_swap_x2",
190 VReg_64, i64, atomic_swap_flat>;
192 defm FLAT_ATOMIC_ADD : FLAT_Atomic_Pseudo <"flat_atomic_add",
193 VGPR_32, i32, atomic_add_flat>;
195 defm FLAT_ATOMIC_SUB : FLAT_Atomic_Pseudo <"flat_atomic_sub",
196 VGPR_32, i32, atomic_sub_flat>;
198 defm FLAT_ATOMIC_SMIN : FLAT_Atomic_Pseudo <"flat_atomic_smin",
199 VGPR_32, i32, atomic_min_flat>;
201 defm FLAT_ATOMIC_UMIN : FLAT_Atomic_Pseudo <"flat_atomic_umin",
202 VGPR_32, i32, atomic_umin_flat>;
204 defm FLAT_ATOMIC_SMAX : FLAT_Atomic_Pseudo <"flat_atomic_smax",
205 VGPR_32, i32, atomic_max_flat>;
207 defm FLAT_ATOMIC_UMAX : FLAT_Atomic_Pseudo <"flat_atomic_umax",
208 VGPR_32, i32, atomic_umax_flat>;
210 defm FLAT_ATOMIC_AND : FLAT_Atomic_Pseudo <"flat_atomic_and",
211 VGPR_32, i32, atomic_and_flat>;
213 defm FLAT_ATOMIC_OR : FLAT_Atomic_Pseudo <"flat_atomic_or",
214 VGPR_32, i32, atomic_or_flat>;
216 defm FLAT_ATOMIC_XOR : FLAT_Atomic_Pseudo <"flat_atomic_xor",
217 VGPR_32, i32, atomic_xor_flat>;
219 defm FLAT_ATOMIC_INC : FLAT_Atomic_Pseudo <"flat_atomic_inc",
220 VGPR_32, i32, atomic_inc_flat>;
222 defm FLAT_ATOMIC_DEC : FLAT_Atomic_Pseudo <"flat_atomic_dec",
223 VGPR_32, i32, atomic_dec_flat>;
225 defm FLAT_ATOMIC_ADD_X2 : FLAT_Atomic_Pseudo <"flat_atomic_add_x2",
226 VReg_64, i64, atomic_add_flat>;
228 defm FLAT_ATOMIC_SUB_X2 : FLAT_Atomic_Pseudo <"flat_atomic_sub_x2",
229 VReg_64, i64, atomic_sub_flat>;
231 defm FLAT_ATOMIC_SMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smin_x2",
232 VReg_64, i64, atomic_min_flat>;
234 defm FLAT_ATOMIC_UMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umin_x2",
235 VReg_64, i64, atomic_umin_flat>;
237 defm FLAT_ATOMIC_SMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smax_x2",
238 VReg_64, i64, atomic_max_flat>;
240 defm FLAT_ATOMIC_UMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umax_x2",
241 VReg_64, i64, atomic_umax_flat>;
243 defm FLAT_ATOMIC_AND_X2 : FLAT_Atomic_Pseudo <"flat_atomic_and_x2",
244 VReg_64, i64, atomic_and_flat>;
246 defm FLAT_ATOMIC_OR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_or_x2",
247 VReg_64, i64, atomic_or_flat>;
249 defm FLAT_ATOMIC_XOR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_xor_x2",
250 VReg_64, i64, atomic_xor_flat>;
252 defm FLAT_ATOMIC_INC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_inc_x2",
253 VReg_64, i64, atomic_inc_flat>;
255 defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2",
256 VReg_64, i64, atomic_dec_flat>;
258 let SubtargetPredicate = isCI in { // CI Only flat instructions : FIXME Only?
260 defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap",
261 VGPR_32, f32, null_frag, v2f32, VReg_64>;
263 defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap_x2",
264 VReg_64, f64, null_frag, v2f64, VReg_128>;
266 defm FLAT_ATOMIC_FMIN : FLAT_Atomic_Pseudo <"flat_atomic_fmin",
269 defm FLAT_ATOMIC_FMAX : FLAT_Atomic_Pseudo <"flat_atomic_fmax",
272 defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
275 defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
278 } // End SubtargetPredicate = isCI
280 //===----------------------------------------------------------------------===//
282 //===----------------------------------------------------------------------===//
284 class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr),
286 auto const AS = cast<MemSDNode>(N)->getAddressSpace();
287 return AS == AMDGPUAS::FLAT_ADDRESS ||
288 AS == AMDGPUAS::GLOBAL_ADDRESS ||
289 AS == AMDGPUAS::CONSTANT_ADDRESS;
292 class flat_st <SDPatternOperator st> : PatFrag<(ops node:$val, node:$ptr),
293 (st node:$val, node:$ptr), [{
294 auto const AS = cast<MemSDNode>(N)->getAddressSpace();
295 return AS == AMDGPUAS::FLAT_ADDRESS ||
296 AS == AMDGPUAS::GLOBAL_ADDRESS;
299 def atomic_flat_load : flat_ld <atomic_load>;
300 def flat_load : flat_ld <load>;
301 def flat_az_extloadi8 : flat_ld <az_extloadi8>;
302 def flat_sextloadi8 : flat_ld <sextloadi8>;
303 def flat_az_extloadi16 : flat_ld <az_extloadi16>;
304 def flat_sextloadi16 : flat_ld <sextloadi16>;
306 def atomic_flat_store : flat_st <atomic_store>;
307 def flat_store : flat_st <store>;
308 def flat_truncstorei8 : flat_st <truncstorei8>;
309 def flat_truncstorei16 : flat_st <truncstorei16>;
311 // Patterns for global loads with no offset.
312 class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
313 (vt (node i64:$addr)),
314 (inst $addr, 0, 0, 0)
317 class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
318 (vt (node i64:$addr)),
319 (inst $addr, 1, 0, 0)
322 class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
323 (node vt:$data, i64:$addr),
324 (inst $addr, $data, 0, 0, 0)
327 class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
328 // atomic store follows atomic binop convention so the address comes
330 (node i64:$addr, vt:$data),
331 (inst $addr, $data, 1, 0, 0)
334 class FlatAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
335 ValueType data_vt = vt> : Pat <
336 (vt (node i64:$addr, data_vt:$data)),
337 (inst $addr, $data, 0, 0)
340 let Predicates = [isCIVI] in {
342 def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;
343 def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;
344 def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i16>;
345 def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i16>;
346 def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;
347 def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;
348 def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;
349 def : FlatLoadPat <FLAT_LOAD_DWORDX2, flat_load, v2i32>;
350 def : FlatLoadPat <FLAT_LOAD_DWORDX4, flat_load, v4i32>;
352 def : FlatLoadAtomicPat <FLAT_LOAD_DWORD, atomic_flat_load, i32>;
353 def : FlatLoadAtomicPat <FLAT_LOAD_DWORDX2, atomic_flat_load, i64>;
355 def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i32>;
356 def : FlatStorePat <FLAT_STORE_SHORT, flat_truncstorei16, i32>;
357 def : FlatStorePat <FLAT_STORE_DWORD, flat_store, i32>;
358 def : FlatStorePat <FLAT_STORE_DWORDX2, flat_store, v2i32>;
359 def : FlatStorePat <FLAT_STORE_DWORDX4, flat_store, v4i32>;
361 def : FlatStoreAtomicPat <FLAT_STORE_DWORD, atomic_flat_store, i32>;
362 def : FlatStoreAtomicPat <FLAT_STORE_DWORDX2, atomic_flat_store, i64>;
364 def : FlatAtomicPat <FLAT_ATOMIC_ADD_RTN, atomic_add_global, i32>;
365 def : FlatAtomicPat <FLAT_ATOMIC_SUB_RTN, atomic_sub_global, i32>;
366 def : FlatAtomicPat <FLAT_ATOMIC_INC_RTN, atomic_inc_global, i32>;
367 def : FlatAtomicPat <FLAT_ATOMIC_DEC_RTN, atomic_dec_global, i32>;
368 def : FlatAtomicPat <FLAT_ATOMIC_AND_RTN, atomic_and_global, i32>;
369 def : FlatAtomicPat <FLAT_ATOMIC_SMAX_RTN, atomic_max_global, i32>;
370 def : FlatAtomicPat <FLAT_ATOMIC_UMAX_RTN, atomic_umax_global, i32>;
371 def : FlatAtomicPat <FLAT_ATOMIC_SMIN_RTN, atomic_min_global, i32>;
372 def : FlatAtomicPat <FLAT_ATOMIC_UMIN_RTN, atomic_umin_global, i32>;
373 def : FlatAtomicPat <FLAT_ATOMIC_OR_RTN, atomic_or_global, i32>;
374 def : FlatAtomicPat <FLAT_ATOMIC_SWAP_RTN, atomic_swap_global, i32>;
375 def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_RTN, AMDGPUatomic_cmp_swap_global, i32, v2i32>;
376 def : FlatAtomicPat <FLAT_ATOMIC_XOR_RTN, atomic_xor_global, i32>;
378 def : FlatAtomicPat <FLAT_ATOMIC_ADD_X2_RTN, atomic_add_global, i64>;
379 def : FlatAtomicPat <FLAT_ATOMIC_SUB_X2_RTN, atomic_sub_global, i64>;
380 def : FlatAtomicPat <FLAT_ATOMIC_INC_X2_RTN, atomic_inc_global, i64>;
381 def : FlatAtomicPat <FLAT_ATOMIC_DEC_X2_RTN, atomic_dec_global, i64>;
382 def : FlatAtomicPat <FLAT_ATOMIC_AND_X2_RTN, atomic_and_global, i64>;
383 def : FlatAtomicPat <FLAT_ATOMIC_SMAX_X2_RTN, atomic_max_global, i64>;
384 def : FlatAtomicPat <FLAT_ATOMIC_UMAX_X2_RTN, atomic_umax_global, i64>;
385 def : FlatAtomicPat <FLAT_ATOMIC_SMIN_X2_RTN, atomic_min_global, i64>;
386 def : FlatAtomicPat <FLAT_ATOMIC_UMIN_X2_RTN, atomic_umin_global, i64>;
387 def : FlatAtomicPat <FLAT_ATOMIC_OR_X2_RTN, atomic_or_global, i64>;
388 def : FlatAtomicPat <FLAT_ATOMIC_SWAP_X2_RTN, atomic_swap_global, i64>;
389 def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_X2_RTN, AMDGPUatomic_cmp_swap_global, i64, v2i64>;
390 def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
392 } // End Predicates = [isCIVI]
394 let Predicates = [isVI] in {
395 def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i16>;
396 def : FlatStorePat <FLAT_STORE_SHORT, flat_store, i16>;
400 //===----------------------------------------------------------------------===//
402 //===----------------------------------------------------------------------===//
404 //===----------------------------------------------------------------------===//
406 //===----------------------------------------------------------------------===//
408 class FLAT_Real_ci <bits<7> op, FLAT_Pseudo ps> :
410 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
411 let AssemblerPredicate = isCIOnly;
412 let DecoderNamespace="CI";
415 def FLAT_LOAD_UBYTE_ci : FLAT_Real_ci <0x8, FLAT_LOAD_UBYTE>;
416 def FLAT_LOAD_SBYTE_ci : FLAT_Real_ci <0x9, FLAT_LOAD_SBYTE>;
417 def FLAT_LOAD_USHORT_ci : FLAT_Real_ci <0xa, FLAT_LOAD_USHORT>;
418 def FLAT_LOAD_SSHORT_ci : FLAT_Real_ci <0xb, FLAT_LOAD_SSHORT>;
419 def FLAT_LOAD_DWORD_ci : FLAT_Real_ci <0xc, FLAT_LOAD_DWORD>;
420 def FLAT_LOAD_DWORDX2_ci : FLAT_Real_ci <0xd, FLAT_LOAD_DWORDX2>;
421 def FLAT_LOAD_DWORDX4_ci : FLAT_Real_ci <0xe, FLAT_LOAD_DWORDX4>;
422 def FLAT_LOAD_DWORDX3_ci : FLAT_Real_ci <0xf, FLAT_LOAD_DWORDX3>;
424 def FLAT_STORE_BYTE_ci : FLAT_Real_ci <0x18, FLAT_STORE_BYTE>;
425 def FLAT_STORE_SHORT_ci : FLAT_Real_ci <0x1a, FLAT_STORE_SHORT>;
426 def FLAT_STORE_DWORD_ci : FLAT_Real_ci <0x1c, FLAT_STORE_DWORD>;
427 def FLAT_STORE_DWORDX2_ci : FLAT_Real_ci <0x1d, FLAT_STORE_DWORDX2>;
428 def FLAT_STORE_DWORDX4_ci : FLAT_Real_ci <0x1e, FLAT_STORE_DWORDX4>;
429 def FLAT_STORE_DWORDX3_ci : FLAT_Real_ci <0x1f, FLAT_STORE_DWORDX3>;
431 multiclass FLAT_Real_Atomics_ci <bits<7> op, FLAT_Pseudo ps> {
432 def _ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
433 def _RTN_ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
436 defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_ci <0x30, FLAT_ATOMIC_SWAP>;
437 defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_ci <0x31, FLAT_ATOMIC_CMPSWAP>;
438 defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_ci <0x32, FLAT_ATOMIC_ADD>;
439 defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_ci <0x33, FLAT_ATOMIC_SUB>;
440 defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_ci <0x35, FLAT_ATOMIC_SMIN>;
441 defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_ci <0x36, FLAT_ATOMIC_UMIN>;
442 defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_ci <0x37, FLAT_ATOMIC_SMAX>;
443 defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_ci <0x38, FLAT_ATOMIC_UMAX>;
444 defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_ci <0x39, FLAT_ATOMIC_AND>;
445 defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_ci <0x3a, FLAT_ATOMIC_OR>;
446 defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_ci <0x3b, FLAT_ATOMIC_XOR>;
447 defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_ci <0x3c, FLAT_ATOMIC_INC>;
448 defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_ci <0x3d, FLAT_ATOMIC_DEC>;
449 defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_ci <0x50, FLAT_ATOMIC_SWAP_X2>;
450 defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_ci <0x51, FLAT_ATOMIC_CMPSWAP_X2>;
451 defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_ci <0x52, FLAT_ATOMIC_ADD_X2>;
452 defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_ci <0x53, FLAT_ATOMIC_SUB_X2>;
453 defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_ci <0x55, FLAT_ATOMIC_SMIN_X2>;
454 defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_ci <0x56, FLAT_ATOMIC_UMIN_X2>;
455 defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_ci <0x57, FLAT_ATOMIC_SMAX_X2>;
456 defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_ci <0x58, FLAT_ATOMIC_UMAX_X2>;
457 defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_ci <0x59, FLAT_ATOMIC_AND_X2>;
458 defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_ci <0x5a, FLAT_ATOMIC_OR_X2>;
459 defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_ci <0x5b, FLAT_ATOMIC_XOR_X2>;
460 defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_ci <0x5c, FLAT_ATOMIC_INC_X2>;
461 defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_ci <0x5d, FLAT_ATOMIC_DEC_X2>;
463 // CI Only flat instructions
464 defm FLAT_ATOMIC_FCMPSWAP : FLAT_Real_Atomics_ci <0x3e, FLAT_ATOMIC_FCMPSWAP>;
465 defm FLAT_ATOMIC_FMIN : FLAT_Real_Atomics_ci <0x3f, FLAT_ATOMIC_FMIN>;
466 defm FLAT_ATOMIC_FMAX : FLAT_Real_Atomics_ci <0x40, FLAT_ATOMIC_FMAX>;
467 defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Real_Atomics_ci <0x5e, FLAT_ATOMIC_FCMPSWAP_X2>;
468 defm FLAT_ATOMIC_FMIN_X2 : FLAT_Real_Atomics_ci <0x5f, FLAT_ATOMIC_FMIN_X2>;
469 defm FLAT_ATOMIC_FMAX_X2 : FLAT_Real_Atomics_ci <0x60, FLAT_ATOMIC_FMAX_X2>;
472 //===----------------------------------------------------------------------===//
474 //===----------------------------------------------------------------------===//
476 class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps> :
478 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
479 let AssemblerPredicate = isVI;
480 let DecoderNamespace="VI";
483 def FLAT_LOAD_UBYTE_vi : FLAT_Real_vi <0x10, FLAT_LOAD_UBYTE>;
484 def FLAT_LOAD_SBYTE_vi : FLAT_Real_vi <0x11, FLAT_LOAD_SBYTE>;
485 def FLAT_LOAD_USHORT_vi : FLAT_Real_vi <0x12, FLAT_LOAD_USHORT>;
486 def FLAT_LOAD_SSHORT_vi : FLAT_Real_vi <0x13, FLAT_LOAD_SSHORT>;
487 def FLAT_LOAD_DWORD_vi : FLAT_Real_vi <0x14, FLAT_LOAD_DWORD>;
488 def FLAT_LOAD_DWORDX2_vi : FLAT_Real_vi <0x15, FLAT_LOAD_DWORDX2>;
489 def FLAT_LOAD_DWORDX4_vi : FLAT_Real_vi <0x17, FLAT_LOAD_DWORDX4>;
490 def FLAT_LOAD_DWORDX3_vi : FLAT_Real_vi <0x16, FLAT_LOAD_DWORDX3>;
492 def FLAT_STORE_BYTE_vi : FLAT_Real_vi <0x18, FLAT_STORE_BYTE>;
493 def FLAT_STORE_SHORT_vi : FLAT_Real_vi <0x1a, FLAT_STORE_SHORT>;
494 def FLAT_STORE_DWORD_vi : FLAT_Real_vi <0x1c, FLAT_STORE_DWORD>;
495 def FLAT_STORE_DWORDX2_vi : FLAT_Real_vi <0x1d, FLAT_STORE_DWORDX2>;
496 def FLAT_STORE_DWORDX4_vi : FLAT_Real_vi <0x1f, FLAT_STORE_DWORDX4>;
497 def FLAT_STORE_DWORDX3_vi : FLAT_Real_vi <0x1e, FLAT_STORE_DWORDX3>;
499 multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps> {
500 def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
501 def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
504 defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
505 defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
506 defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
507 defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_vi <0x43, FLAT_ATOMIC_SUB>;
508 defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_vi <0x44, FLAT_ATOMIC_SMIN>;
509 defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_vi <0x45, FLAT_ATOMIC_UMIN>;
510 defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_vi <0x46, FLAT_ATOMIC_SMAX>;
511 defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_vi <0x47, FLAT_ATOMIC_UMAX>;
512 defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_vi <0x48, FLAT_ATOMIC_AND>;
513 defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_vi <0x49, FLAT_ATOMIC_OR>;
514 defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_vi <0x4a, FLAT_ATOMIC_XOR>;
515 defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_vi <0x4b, FLAT_ATOMIC_INC>;
516 defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_vi <0x4c, FLAT_ATOMIC_DEC>;
517 defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_vi <0x60, FLAT_ATOMIC_SWAP_X2>;
518 defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_vi <0x61, FLAT_ATOMIC_CMPSWAP_X2>;
519 defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_vi <0x62, FLAT_ATOMIC_ADD_X2>;
520 defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_vi <0x63, FLAT_ATOMIC_SUB_X2>;
521 defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_vi <0x64, FLAT_ATOMIC_SMIN_X2>;
522 defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_vi <0x65, FLAT_ATOMIC_UMIN_X2>;
523 defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_vi <0x66, FLAT_ATOMIC_SMAX_X2>;
524 defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_vi <0x67, FLAT_ATOMIC_UMAX_X2>;
525 defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_vi <0x68, FLAT_ATOMIC_AND_X2>;
526 defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_vi <0x69, FLAT_ATOMIC_OR_X2>;
527 defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_vi <0x6a, FLAT_ATOMIC_XOR_X2>;
528 defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_vi <0x6b, FLAT_ATOMIC_INC_X2>;
529 defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_vi <0x6c, FLAT_ATOMIC_DEC_X2>;