1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements hazard recognizers for scheduling on GCN processors.
12 //===----------------------------------------------------------------------===//
14 #include "GCNHazardRecognizer.h"
15 #include "AMDGPUSubtarget.h"
16 #include "SIDefines.h"
17 #include "SIInstrInfo.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/ADT/iterator_range.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/ScheduleDAG.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/ErrorHandling.h"
35 //===----------------------------------------------------------------------===//
36 // Hazard Recoginizer Implementation
37 //===----------------------------------------------------------------------===//
39 GCNHazardRecognizer::GCNHazardRecognizer(const MachineFunction &MF) :
40 CurrCycleInstr(nullptr),
42 ST(MF.getSubtarget<SISubtarget>()),
43 TII(*ST.getInstrInfo()),
44 TRI(TII.getRegisterInfo()),
45 ClauseUses(TRI.getNumRegUnits()),
46 ClauseDefs(TRI.getNumRegUnits()) {
50 void GCNHazardRecognizer::EmitInstruction(SUnit *SU) {
51 EmitInstruction(SU->getInstr());
54 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) {
58 static bool isDivFMas(unsigned Opcode) {
59 return Opcode == AMDGPU::V_DIV_FMAS_F32 || Opcode == AMDGPU::V_DIV_FMAS_F64;
62 static bool isSGetReg(unsigned Opcode) {
63 return Opcode == AMDGPU::S_GETREG_B32;
66 static bool isSSetReg(unsigned Opcode) {
67 return Opcode == AMDGPU::S_SETREG_B32 || Opcode == AMDGPU::S_SETREG_IMM32_B32;
70 static bool isRWLane(unsigned Opcode) {
71 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32;
74 static bool isRFE(unsigned Opcode) {
75 return Opcode == AMDGPU::S_RFE_B64;
78 static bool isSMovRel(unsigned Opcode) {
80 case AMDGPU::S_MOVRELS_B32:
81 case AMDGPU::S_MOVRELS_B64:
82 case AMDGPU::S_MOVRELD_B32:
83 case AMDGPU::S_MOVRELD_B64:
90 static bool isSendMsgTraceDataOrGDS(const MachineInstr &MI) {
91 switch (MI.getOpcode()) {
92 case AMDGPU::S_SENDMSG:
93 case AMDGPU::S_SENDMSGHALT:
94 case AMDGPU::S_TTRACEDATA:
102 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) {
103 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,
104 AMDGPU::OpName::simm16);
105 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_;
108 ScheduleHazardRecognizer::HazardType
109 GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
110 MachineInstr *MI = SU->getInstr();
112 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0)
115 // FIXME: Should flat be considered vmem?
116 if ((SIInstrInfo::isVMEM(*MI) ||
117 SIInstrInfo::isFLAT(*MI))
118 && checkVMEMHazards(MI) > 0)
121 if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0)
124 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0)
127 if (isDivFMas(MI->getOpcode()) && checkDivFMasHazards(MI) > 0)
130 if (isRWLane(MI->getOpcode()) && checkRWLaneHazards(MI) > 0)
133 if (isSGetReg(MI->getOpcode()) && checkGetRegHazards(MI) > 0)
136 if (isSSetReg(MI->getOpcode()) && checkSetRegHazards(MI) > 0)
139 if (isRFE(MI->getOpcode()) && checkRFEHazards(MI) > 0)
142 if (ST.hasReadM0MovRelInterpHazard() &&
143 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) &&
144 checkReadM0Hazards(MI) > 0)
147 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(*MI) &&
148 checkReadM0Hazards(MI) > 0)
151 if (MI->isInlineAsm() && checkInlineAsmHazards(MI) > 0)
154 if (checkAnyInstHazards(MI) > 0)
160 unsigned GCNHazardRecognizer::PreEmitNoops(SUnit *SU) {
161 return PreEmitNoops(SU->getInstr());
164 unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) {
165 int WaitStates = std::max(0, checkAnyInstHazards(MI));
167 if (SIInstrInfo::isSMRD(*MI))
168 return std::max(WaitStates, checkSMRDHazards(MI));
170 if (SIInstrInfo::isVALU(*MI))
171 WaitStates = std::max(WaitStates, checkVALUHazards(MI));
173 if (SIInstrInfo::isVMEM(*MI) || SIInstrInfo::isFLAT(*MI))
174 WaitStates = std::max(WaitStates, checkVMEMHazards(MI));
176 if (SIInstrInfo::isDPP(*MI))
177 WaitStates = std::max(WaitStates, checkDPPHazards(MI));
179 if (isDivFMas(MI->getOpcode()))
180 WaitStates = std::max(WaitStates, checkDivFMasHazards(MI));
182 if (isRWLane(MI->getOpcode()))
183 WaitStates = std::max(WaitStates, checkRWLaneHazards(MI));
185 if (MI->isInlineAsm())
186 return std::max(WaitStates, checkInlineAsmHazards(MI));
188 if (isSGetReg(MI->getOpcode()))
189 return std::max(WaitStates, checkGetRegHazards(MI));
191 if (isSSetReg(MI->getOpcode()))
192 return std::max(WaitStates, checkSetRegHazards(MI));
194 if (isRFE(MI->getOpcode()))
195 return std::max(WaitStates, checkRFEHazards(MI));
197 if (ST.hasReadM0MovRelInterpHazard() && (TII.isVINTRP(*MI) ||
198 isSMovRel(MI->getOpcode())))
199 return std::max(WaitStates, checkReadM0Hazards(MI));
201 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(*MI))
202 return std::max(WaitStates, checkReadM0Hazards(MI));
207 void GCNHazardRecognizer::EmitNoop() {
208 EmittedInstrs.push_front(nullptr);
211 void GCNHazardRecognizer::AdvanceCycle() {
212 // When the scheduler detects a stall, it will call AdvanceCycle() without
213 // emitting any instructions.
217 unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr);
219 // Keep track of emitted instructions
220 EmittedInstrs.push_front(CurrCycleInstr);
222 // Add a nullptr for each additional wait state after the first. Make sure
223 // not to add more than getMaxLookAhead() items to the list, since we
224 // truncate the list to that size right after this loop.
225 for (unsigned i = 1, e = std::min(NumWaitStates, getMaxLookAhead());
227 EmittedInstrs.push_front(nullptr);
230 // getMaxLookahead() is the largest number of wait states we will ever need
231 // to insert, so there is no point in keeping track of more than that many
233 EmittedInstrs.resize(getMaxLookAhead());
235 CurrCycleInstr = nullptr;
238 void GCNHazardRecognizer::RecedeCycle() {
239 llvm_unreachable("hazard recognizer does not support bottom-up scheduling.");
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
246 int GCNHazardRecognizer::getWaitStatesSince(
247 function_ref<bool(MachineInstr *)> IsHazard) {
249 for (MachineInstr *MI : EmittedInstrs) {
254 unsigned Opcode = MI->getOpcode();
255 if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF ||
256 Opcode == AMDGPU::INLINEASM)
261 return std::numeric_limits<int>::max();
264 int GCNHazardRecognizer::getWaitStatesSinceDef(
265 unsigned Reg, function_ref<bool(MachineInstr *)> IsHazardDef) {
266 const SIRegisterInfo *TRI = ST.getRegisterInfo();
268 auto IsHazardFn = [IsHazardDef, TRI, Reg] (MachineInstr *MI) {
269 return IsHazardDef(MI) && MI->modifiesRegister(Reg, TRI);
272 return getWaitStatesSince(IsHazardFn);
275 int GCNHazardRecognizer::getWaitStatesSinceSetReg(
276 function_ref<bool(MachineInstr *)> IsHazard) {
277 auto IsHazardFn = [IsHazard] (MachineInstr *MI) {
278 return isSSetReg(MI->getOpcode()) && IsHazard(MI);
281 return getWaitStatesSince(IsHazardFn);
284 //===----------------------------------------------------------------------===//
285 // No-op Hazard Detection
286 //===----------------------------------------------------------------------===//
288 static void addRegUnits(const SIRegisterInfo &TRI,
289 BitVector &BV, unsigned Reg) {
290 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI)
294 static void addRegsToSet(const SIRegisterInfo &TRI,
295 iterator_range<MachineInstr::const_mop_iterator> Ops,
297 for (const MachineOperand &Op : Ops) {
299 addRegUnits(TRI, Set, Op.getReg());
303 void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
304 // XXX: Do we need to worry about implicit operands
305 addRegsToSet(TRI, MI.defs(), ClauseDefs);
306 addRegsToSet(TRI, MI.uses(), ClauseUses);
309 int GCNHazardRecognizer::checkSoftClauseHazards(MachineInstr *MEM) {
310 // SMEM soft clause are only present on VI+, and only matter if xnack is
312 if (!ST.isXNACKEnabled())
315 bool IsSMRD = TII.isSMRD(*MEM);
319 // A soft-clause is any group of consecutive SMEM instructions. The
320 // instructions in this group may return out of order and/or may be
321 // replayed (i.e. the same instruction issued more than once).
323 // In order to handle these situations correctly we need to make sure
324 // that when a clause has more than one instruction, no instruction in the
325 // clause writes to a register that is read another instruction in the clause
326 // (including itself). If we encounter this situaion, we need to break the
327 // clause by inserting a non SMEM instruction.
329 for (MachineInstr *MI : EmittedInstrs) {
330 // When we hit a non-SMEM instruction then we have passed the start of the
331 // clause and we can stop.
335 if (IsSMRD != SIInstrInfo::isSMRD(*MI))
341 if (ClauseDefs.none())
344 // We need to make sure not to put loads and stores in the same clause if they
345 // use the same address. For now, just start a new clause whenever we see a
352 // If the set of defs and uses intersect then we cannot add this instruction
353 // to the clause, so we have a hazard.
354 return ClauseDefs.anyCommon(ClauseUses) ? 1 : 0;
357 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) {
358 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
359 int WaitStatesNeeded = 0;
361 WaitStatesNeeded = checkSoftClauseHazards(SMRD);
363 // This SMRD hazard only affects SI.
364 if (ST.getGeneration() != SISubtarget::SOUTHERN_ISLANDS)
365 return WaitStatesNeeded;
367 // A read of an SGPR by SMRD instruction requires 4 wait states when the
368 // SGPR was written by a VALU instruction.
369 int SmrdSgprWaitStates = 4;
370 auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };
371 auto IsBufferHazardDefFn = [this] (MachineInstr *MI) { return TII.isSALU(*MI); };
373 bool IsBufferSMRD = TII.isBufferSMRD(*SMRD);
375 for (const MachineOperand &Use : SMRD->uses()) {
378 int WaitStatesNeededForUse =
379 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn);
380 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
382 // This fixes what appears to be undocumented hardware behavior in SI where
383 // s_mov writing a descriptor and s_buffer_load_dword reading the descriptor
384 // needs some number of nops in between. We don't know how many we need, but
385 // let's use 4. This wasn't discovered before probably because the only
386 // case when this happens is when we expand a 64-bit pointer into a full
387 // descriptor and use s_buffer_load_dword instead of s_load_dword, which was
388 // probably never encountered in the closed-source land.
390 int WaitStatesNeededForUse =
391 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(),
392 IsBufferHazardDefFn);
393 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
397 return WaitStatesNeeded;
400 int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) {
401 if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
404 int WaitStatesNeeded = checkSoftClauseHazards(VMEM);
406 // A read of an SGPR by a VMEM instruction requires 5 wait states when the
407 // SGPR was written by a VALU Instruction.
408 const int VmemSgprWaitStates = 5;
409 auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };
411 for (const MachineOperand &Use : VMEM->uses()) {
412 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
415 int WaitStatesNeededForUse =
416 VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn);
417 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
419 return WaitStatesNeeded;
422 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) {
423 const SIRegisterInfo *TRI = ST.getRegisterInfo();
424 const SIInstrInfo *TII = ST.getInstrInfo();
426 // Check for DPP VGPR read after VALU VGPR write and EXEC write.
427 int DppVgprWaitStates = 2;
428 int DppExecWaitStates = 5;
429 int WaitStatesNeeded = 0;
430 auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
432 for (const MachineOperand &Use : DPP->uses()) {
433 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
435 int WaitStatesNeededForUse =
436 DppVgprWaitStates - getWaitStatesSinceDef(Use.getReg());
437 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
440 WaitStatesNeeded = std::max(
442 DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC, IsHazardDefFn));
444 return WaitStatesNeeded;
447 int GCNHazardRecognizer::checkDivFMasHazards(MachineInstr *DivFMas) {
448 const SIInstrInfo *TII = ST.getInstrInfo();
450 // v_div_fmas requires 4 wait states after a write to vcc from a VALU
452 const int DivFMasWaitStates = 4;
453 auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
454 int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn);
456 return DivFMasWaitStates - WaitStatesNeeded;
459 int GCNHazardRecognizer::checkGetRegHazards(MachineInstr *GetRegInstr) {
460 const SIInstrInfo *TII = ST.getInstrInfo();
461 unsigned GetRegHWReg = getHWReg(TII, *GetRegInstr);
463 const int GetRegWaitStates = 2;
464 auto IsHazardFn = [TII, GetRegHWReg] (MachineInstr *MI) {
465 return GetRegHWReg == getHWReg(TII, *MI);
467 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
469 return GetRegWaitStates - WaitStatesNeeded;
472 int GCNHazardRecognizer::checkSetRegHazards(MachineInstr *SetRegInstr) {
473 const SIInstrInfo *TII = ST.getInstrInfo();
474 unsigned HWReg = getHWReg(TII, *SetRegInstr);
476 const int SetRegWaitStates =
477 ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ? 1 : 2;
478 auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {
479 return HWReg == getHWReg(TII, *MI);
481 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
482 return SetRegWaitStates - WaitStatesNeeded;
485 int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) {
489 const SIInstrInfo *TII = ST.getInstrInfo();
490 unsigned Opcode = MI.getOpcode();
491 const MCInstrDesc &Desc = MI.getDesc();
493 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
496 VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
498 if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
499 // There is no hazard if the instruction does not use vector regs
503 // For MUBUF/MTBUF instructions this hazard only exists if the
504 // instruction is not using a register in the soffset field.
505 const MachineOperand *SOffset =
506 TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
507 // If we have no soffset operand, then assume this field has been
508 // hardcoded to zero.
509 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 &&
510 (!SOffset || !SOffset->isReg()))
514 // MIMG instructions create a hazard if they don't use a 256-bit T# and
515 // the store size is greater than 8 bytes and they have more than two bits
516 // of their dmask set.
517 // All our MIMG definitions use a 256-bit T#, so we can skip checking for them.
518 if (TII->isMIMG(MI)) {
519 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
520 assert(SRsrcIdx != -1 &&
521 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256);
525 if (TII->isFLAT(MI)) {
526 int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
527 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)
534 int GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def,
535 const MachineRegisterInfo &MRI) {
536 // Helper to check for the hazard where VMEM instructions that store more than
537 // 8 bytes can have there store data over written by the next instruction.
538 const SIRegisterInfo *TRI = ST.getRegisterInfo();
540 const int VALUWaitStates = 1;
541 int WaitStatesNeeded = 0;
543 if (!TRI->isVGPR(MRI, Def.getReg()))
544 return WaitStatesNeeded;
545 unsigned Reg = Def.getReg();
546 auto IsHazardFn = [this, Reg, TRI] (MachineInstr *MI) {
547 int DataIdx = createsVALUHazard(*MI);
548 return DataIdx >= 0 &&
549 TRI->regsOverlap(MI->getOperand(DataIdx).getReg(), Reg);
551 int WaitStatesNeededForDef =
552 VALUWaitStates - getWaitStatesSince(IsHazardFn);
553 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
555 return WaitStatesNeeded;
558 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) {
559 // This checks for the hazard where VMEM instructions that store more than
560 // 8 bytes can have there store data over written by the next instruction.
561 if (!ST.has12DWordStoreHazard())
564 const MachineRegisterInfo &MRI = MF.getRegInfo();
565 int WaitStatesNeeded = 0;
567 for (const MachineOperand &Def : VALU->defs()) {
568 WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI));
571 return WaitStatesNeeded;
574 int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) {
575 // This checks for hazards associated with inline asm statements.
576 // Since inline asms can contain just about anything, we use this
577 // to call/leverage other check*Hazard routines. Note that
578 // this function doesn't attempt to address all possible inline asm
579 // hazards (good luck), but is a collection of what has been
580 // problematic thus far.
582 // see checkVALUHazards()
583 if (!ST.has12DWordStoreHazard())
586 const MachineRegisterInfo &MRI = MF.getRegInfo();
587 int WaitStatesNeeded = 0;
589 for (unsigned I = InlineAsm::MIOp_FirstOperand, E = IA->getNumOperands();
591 const MachineOperand &Op = IA->getOperand(I);
592 if (Op.isReg() && Op.isDef()) {
593 WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
597 return WaitStatesNeeded;
600 int GCNHazardRecognizer::checkRWLaneHazards(MachineInstr *RWLane) {
601 const SIInstrInfo *TII = ST.getInstrInfo();
602 const SIRegisterInfo *TRI = ST.getRegisterInfo();
603 const MachineRegisterInfo &MRI = MF.getRegInfo();
605 const MachineOperand *LaneSelectOp =
606 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1);
608 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg()))
611 unsigned LaneSelectReg = LaneSelectOp->getReg();
612 auto IsHazardFn = [TII] (MachineInstr *MI) {
613 return TII->isVALU(*MI);
616 const int RWLaneWaitStates = 4;
617 int WaitStatesSince = getWaitStatesSinceDef(LaneSelectReg, IsHazardFn);
618 return RWLaneWaitStates - WaitStatesSince;
621 int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) {
622 if (ST.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
625 const SIInstrInfo *TII = ST.getInstrInfo();
627 const int RFEWaitStates = 1;
629 auto IsHazardFn = [TII] (MachineInstr *MI) {
630 return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;
632 int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
633 return RFEWaitStates - WaitStatesNeeded;
636 int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) {
637 if (MI->isDebugValue())
640 const SIRegisterInfo *TRI = ST.getRegisterInfo();
641 if (!ST.hasSMovFedHazard())
644 // Check for any instruction reading an SGPR after a write from
646 int MovFedWaitStates = 1;
647 int WaitStatesNeeded = 0;
649 for (const MachineOperand &Use : MI->uses()) {
650 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
652 auto IsHazardFn = [] (MachineInstr *MI) {
653 return MI->getOpcode() == AMDGPU::S_MOV_FED_B32;
655 int WaitStatesNeededForUse =
656 MovFedWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardFn);
657 WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
660 return WaitStatesNeeded;
663 int GCNHazardRecognizer::checkReadM0Hazards(MachineInstr *MI) {
664 const SIInstrInfo *TII = ST.getInstrInfo();
665 const int SMovRelWaitStates = 1;
666 auto IsHazardFn = [TII] (MachineInstr *MI) {
667 return TII->isSALU(*MI);
669 return SMovRelWaitStates - getWaitStatesSinceDef(AMDGPU::M0, IsHazardFn);