1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines hazard recognizers for scheduling on GCN processors.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
15 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
23 class MachineFunction;
29 class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
30 // This variable stores the instruction that has been emitted this cycle. It
31 // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
33 MachineInstr *CurrCycleInstr;
34 std::list<MachineInstr*> EmittedInstrs;
35 const MachineFunction &MF;
36 const SISubtarget &ST;
37 const SIInstrInfo &TII;
39 int getWaitStatesSince(function_ref<bool(MachineInstr *)> IsHazard);
40 int getWaitStatesSinceDef(unsigned Reg,
41 function_ref<bool(MachineInstr *)> IsHazardDef =
42 [](MachineInstr *) { return true; });
43 int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard);
45 int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
46 int checkSMRDHazards(MachineInstr *SMRD);
47 int checkVMEMHazards(MachineInstr* VMEM);
48 int checkDPPHazards(MachineInstr *DPP);
49 int checkDivFMasHazards(MachineInstr *DivFMas);
50 int checkGetRegHazards(MachineInstr *GetRegInstr);
51 int checkSetRegHazards(MachineInstr *SetRegInstr);
52 int createsVALUHazard(const MachineInstr &MI);
53 int checkVALUHazards(MachineInstr *VALU);
54 int checkRWLaneHazards(MachineInstr *RWLane);
55 int checkRFEHazards(MachineInstr *RFE);
56 int checkAnyInstHazards(MachineInstr *MI);
57 int checkReadM0Hazards(MachineInstr *SMovRel);
59 GCNHazardRecognizer(const MachineFunction &MF);
60 // We can only issue one instruction per cycle.
61 bool atIssueLimit() const override { return true; }
62 void EmitInstruction(SUnit *SU) override;
63 void EmitInstruction(MachineInstr *MI) override;
64 HazardType getHazardType(SUnit *SU, int Stalls) override;
65 void EmitNoop() override;
66 unsigned PreEmitNoops(SUnit *SU) override;
67 unsigned PreEmitNoops(MachineInstr *) override;
68 void AdvanceCycle() override;
69 void RecedeCycle() override;
72 } // end namespace llvm
74 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H