1 //===- GCNRegPressure.h -----------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
11 #define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
13 #include "AMDGPUSubtarget.h"
14 #include "llvm/ADT/DenseMap.h"
15 #include "llvm/CodeGen/LiveIntervals.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/SlotIndexes.h"
19 #include "llvm/MC/LaneBitmask.h"
20 #include "llvm/Support/Debug.h"
26 class MachineRegisterInfo;
29 struct GCNRegPressure {
42 bool empty() const { return getSGPRNum() == 0 && getVGPRNum() == 0; }
44 void clear() { std::fill(&Value[0], &Value[TOTAL_KINDS], 0); }
46 unsigned getSGPRNum() const { return Value[SGPR32]; }
47 unsigned getVGPRNum() const { return Value[VGPR32]; }
49 unsigned getVGPRTuplesWeight() const { return Value[VGPR_TUPLE]; }
50 unsigned getSGPRTuplesWeight() const { return Value[SGPR_TUPLE]; }
52 unsigned getOccupancy(const SISubtarget &ST) const {
53 return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
54 ST.getOccupancyWithNumVGPRs(getVGPRNum()));
57 void inc(unsigned Reg,
60 const MachineRegisterInfo &MRI);
62 bool higherOccupancy(const SISubtarget &ST, const GCNRegPressure& O) const {
63 return getOccupancy(ST) > O.getOccupancy(ST);
66 bool less(const SISubtarget &ST, const GCNRegPressure& O,
67 unsigned MaxOccupancy = std::numeric_limits<unsigned>::max()) const;
69 bool operator==(const GCNRegPressure &O) const {
70 return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
73 bool operator!=(const GCNRegPressure &O) const {
77 void print(raw_ostream &OS, const SISubtarget *ST = nullptr) const;
78 void dump() const { print(dbgs()); }
81 unsigned Value[TOTAL_KINDS];
83 static unsigned getRegKind(unsigned Reg, const MachineRegisterInfo &MRI);
85 friend GCNRegPressure max(const GCNRegPressure &P1,
86 const GCNRegPressure &P2);
89 inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
91 for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
92 Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
98 using LiveRegSet = DenseMap<unsigned, LaneBitmask>;
101 const LiveIntervals &LIS;
103 GCNRegPressure CurPressure, MaxPressure;
104 const MachineInstr *LastTrackedMI = nullptr;
105 mutable const MachineRegisterInfo *MRI = nullptr;
107 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
110 // live regs for the current state
111 const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
112 const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
114 void clearMaxPressure() { MaxPressure.clear(); }
116 // returns MaxPressure, resetting it
117 decltype(MaxPressure) moveMaxPressure() {
118 auto Res = MaxPressure;
123 decltype(LiveRegs) moveLiveRegs() {
124 return std::move(LiveRegs);
127 static void printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
128 const MachineRegisterInfo &MRI);
131 class GCNUpwardRPTracker : public GCNRPTracker {
133 GCNUpwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {}
135 // reset tracker to the point just below MI
136 // filling live regs upon this point using LIS
137 void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
139 // move to the state just above the MI
140 void recede(const MachineInstr &MI);
142 // checks whether the tracker's state after receding MI corresponds
143 // to reported by LIS
144 bool isValid() const;
147 class GCNDownwardRPTracker : public GCNRPTracker {
148 // Last position of reset or advanceBeforeNext
149 MachineBasicBlock::const_iterator NextMI;
151 MachineBasicBlock::const_iterator MBBEnd;
154 GCNDownwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {}
156 const MachineBasicBlock::const_iterator getNext() const { return NextMI; }
158 // Reset tracker to the point before the MI
159 // filling live regs upon this point using LIS.
160 // Returns false if block is empty except debug values.
161 bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
163 // Move to the state right before the next MI. Returns false if reached
165 bool advanceBeforeNext();
167 // Move to the state at the MI, advanceBeforeNext has to be called first.
168 void advanceToNext();
170 // Move to the state at the next MI. Returns false if reached end of block.
173 // Advance instructions until before End.
174 bool advance(MachineBasicBlock::const_iterator End);
176 // Reset to Begin and advance to End.
177 bool advance(MachineBasicBlock::const_iterator Begin,
178 MachineBasicBlock::const_iterator End,
179 const LiveRegSet *LiveRegsCopy = nullptr);
182 LaneBitmask getLiveLaneMask(unsigned Reg,
184 const LiveIntervals &LIS,
185 const MachineRegisterInfo &MRI);
187 GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI,
188 const LiveIntervals &LIS,
189 const MachineRegisterInfo &MRI);
191 inline GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI,
192 const LiveIntervals &LIS) {
193 return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
194 MI.getParent()->getParent()->getRegInfo());
197 inline GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI,
198 const LiveIntervals &LIS) {
199 return getLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
200 MI.getParent()->getParent()->getRegInfo());
203 template <typename Range>
204 GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI,
207 for (const auto &RM : LiveRegs)
208 Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
212 void printLivesAt(SlotIndex SI,
213 const LiveIntervals &LIS,
214 const MachineRegisterInfo &MRI);
216 } // end namespace llvm
218 #endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H