1 //===---------------------- GCNRegPressure.h -*- C++ -*--------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
15 #define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
17 #include "AMDGPUSubtarget.h"
23 struct GCNRegPressure {
36 bool empty() const { return getSGRPNum() == 0 && getVGRPNum() == 0; }
38 void clear() { std::fill(&Value[0], &Value[TOTAL_KINDS], 0); }
40 unsigned getSGRPNum() const { return Value[SGPR32]; }
41 unsigned getVGRPNum() const { return Value[VGPR32]; }
43 unsigned getVGPRTuplesWeight() const { return Value[VGPR_TUPLE]; }
44 unsigned getSGPRTuplesWeight() const { return Value[SGPR_TUPLE]; }
46 unsigned getOccupancy(const SISubtarget &ST) const {
47 return std::min(ST.getOccupancyWithNumSGPRs(getSGRPNum()),
48 ST.getOccupancyWithNumVGPRs(getVGRPNum()));
51 void inc(unsigned Reg,
54 const MachineRegisterInfo &MRI);
56 bool higherOccupancy(const SISubtarget &ST, const GCNRegPressure& O) const {
57 return getOccupancy(ST) > O.getOccupancy(ST);
60 bool less(const SISubtarget &ST, const GCNRegPressure& O,
61 unsigned MaxOccupancy = std::numeric_limits<unsigned>::max()) const;
63 bool operator==(const GCNRegPressure &O) const {
64 return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
67 bool operator!=(const GCNRegPressure &O) const {
71 void print(raw_ostream &OS, const SISubtarget *ST=nullptr) const;
72 void dump() const { print(dbgs()); }
75 unsigned Value[TOTAL_KINDS];
77 static unsigned getRegKind(unsigned Reg, const MachineRegisterInfo &MRI);
79 friend GCNRegPressure max(const GCNRegPressure &P1,
80 const GCNRegPressure &P2);
83 inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
85 for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
86 Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
92 typedef DenseMap<unsigned, LaneBitmask> LiveRegSet;
96 GCNRegPressure CurPressure, MaxPressure;
97 const MachineInstr *LastTrackedMI = nullptr;
98 mutable const MachineRegisterInfo *MRI = nullptr;
101 // live regs for the current state
102 const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
103 const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
105 // returns MaxPressure, resetting it
106 decltype(MaxPressure) moveMaxPressure() {
107 auto Res = MaxPressure;
111 decltype(LiveRegs) moveLiveRegs() {
112 return std::move(LiveRegs);
116 class GCNUpwardRPTracker : public GCNRPTracker {
117 const LiveIntervals &LIS;
118 LaneBitmask getDefRegMask(const MachineOperand &MO) const;
119 LaneBitmask getUsedRegMask(const MachineOperand &MO) const;
121 GCNUpwardRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
122 // reset tracker to the point just below MI
123 // filling live regs upon this point using LIS
124 void reset(const MachineInstr &MI);
126 // move to the state just above the MI
127 void recede(const MachineInstr &MI);
129 // checks whether the tracker's state after receding MI corresponds
130 // to reported by LIS
131 bool isValid() const;
134 LaneBitmask getLiveLaneMask(unsigned Reg,
136 const LiveIntervals &LIS,
137 const MachineRegisterInfo &MRI);
139 GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI,
140 const LiveIntervals &LIS,
141 const MachineRegisterInfo &MRI);
143 inline GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI,
144 const LiveIntervals &LIS) {
145 return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
146 MI.getParent()->getParent()->getRegInfo());
149 inline GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI,
150 const LiveIntervals &LIS) {
151 return getLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
152 MI.getParent()->getParent()->getRegInfo());
155 template <typename Range>
156 GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI,
159 for (const auto &RM : LiveRegs)
160 Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
164 void printLivesAt(SlotIndex SI,
165 const LiveIntervals &LIS,
166 const MachineRegisterInfo &MRI);
168 } // End namespace llvm
170 #endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H