1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "SIDefines.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
28 using namespace llvm::AMDGPU;
30 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
31 StringRef Annot, const MCSubtargetInfo &STI) {
33 printInstruction(MI, STI, OS);
34 printAnnotation(OS, Annot);
37 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
38 const MCSubtargetInfo &STI,
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
43 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
45 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
48 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
49 const MCSubtargetInfo &STI,
51 // It's possible to end up with a 32-bit literal used with a 16-bit operand
52 // with ignored high bits. Print as 32-bit anyway in that case.
53 int64_t Imm = MI->getOperand(OpNo).getImm();
54 if (isInt<16>(Imm) || isUInt<16>(Imm))
55 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
57 printU32ImmOperand(MI, OpNo, STI, O);
60 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
62 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
65 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
67 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
70 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
72 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
75 void AMDGPUInstPrinter::printS16ImmDecOperand(const MCInst *MI, unsigned OpNo,
77 O << formatDec(static_cast<int16_t>(MI->getOperand(OpNo).getImm()));
80 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
81 const MCSubtargetInfo &STI,
83 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
86 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
87 raw_ostream &O, StringRef BitName) {
88 if (MI->getOperand(OpNo).getImm()) {
93 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
95 printNamedBit(MI, OpNo, O, "offen");
98 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
100 printNamedBit(MI, OpNo, O, "idxen");
103 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
105 printNamedBit(MI, OpNo, O, "addr64");
108 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
110 if (MI->getOperand(OpNo).getImm()) {
112 printU16ImmDecOperand(MI, OpNo, O);
116 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
117 const MCSubtargetInfo &STI,
119 uint16_t Imm = MI->getOperand(OpNo).getImm();
121 O << ((OpNo == 0)? "offset:" : " offset:");
122 printU16ImmDecOperand(MI, OpNo, O);
126 void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo,
127 const MCSubtargetInfo &STI,
129 uint16_t Imm = MI->getOperand(OpNo).getImm();
131 O << ((OpNo == 0)? "offset:" : " offset:");
132 printS16ImmDecOperand(MI, OpNo, O);
136 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
137 const MCSubtargetInfo &STI,
139 if (MI->getOperand(OpNo).getImm()) {
141 printU8ImmDecOperand(MI, OpNo, O);
145 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
146 const MCSubtargetInfo &STI,
148 if (MI->getOperand(OpNo).getImm()) {
150 printU8ImmDecOperand(MI, OpNo, O);
154 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
155 const MCSubtargetInfo &STI,
157 printU32ImmOperand(MI, OpNo, STI, O);
160 void AMDGPUInstPrinter::printSMRDOffset20(const MCInst *MI, unsigned OpNo,
161 const MCSubtargetInfo &STI,
163 printU32ImmOperand(MI, OpNo, STI, O);
166 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
167 const MCSubtargetInfo &STI,
169 printU32ImmOperand(MI, OpNo, STI, O);
172 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
173 const MCSubtargetInfo &STI, raw_ostream &O) {
174 printNamedBit(MI, OpNo, O, "gds");
177 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
178 const MCSubtargetInfo &STI, raw_ostream &O) {
179 printNamedBit(MI, OpNo, O, "glc");
182 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
183 const MCSubtargetInfo &STI, raw_ostream &O) {
184 printNamedBit(MI, OpNo, O, "slc");
187 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
188 const MCSubtargetInfo &STI, raw_ostream &O) {
189 printNamedBit(MI, OpNo, O, "tfe");
192 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
193 const MCSubtargetInfo &STI, raw_ostream &O) {
194 if (MI->getOperand(OpNo).getImm()) {
196 printU16ImmOperand(MI, OpNo, STI, O);
200 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
201 const MCSubtargetInfo &STI, raw_ostream &O) {
202 printNamedBit(MI, OpNo, O, "unorm");
205 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
206 const MCSubtargetInfo &STI, raw_ostream &O) {
207 printNamedBit(MI, OpNo, O, "da");
210 void AMDGPUInstPrinter::printR128(const MCInst *MI, unsigned OpNo,
211 const MCSubtargetInfo &STI, raw_ostream &O) {
212 printNamedBit(MI, OpNo, O, "r128");
215 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
216 const MCSubtargetInfo &STI, raw_ostream &O) {
217 printNamedBit(MI, OpNo, O, "lwe");
220 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
221 const MCSubtargetInfo &STI,
223 if (MI->getOperand(OpNo).getImm())
227 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
228 const MCSubtargetInfo &STI,
230 if (MI->getOperand(OpNo).getImm())
234 void AMDGPUInstPrinter::printDFMT(const MCInst *MI, unsigned OpNo,
235 const MCSubtargetInfo &STI,
237 if (MI->getOperand(OpNo).getImm()) {
239 printU8ImmDecOperand(MI, OpNo, O);
243 void AMDGPUInstPrinter::printNFMT(const MCInst *MI, unsigned OpNo,
244 const MCSubtargetInfo &STI,
246 if (MI->getOperand(OpNo).getImm()) {
248 printU8ImmDecOperand(MI, OpNo, O);
252 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
253 const MCRegisterInfo &MRI) {
267 case AMDGPU::FLAT_SCR:
288 case AMDGPU::EXEC_LO:
291 case AMDGPU::EXEC_HI:
294 case AMDGPU::FLAT_SCR_LO:
295 O << "flat_scratch_lo";
297 case AMDGPU::FLAT_SCR_HI:
298 O << "flat_scratch_hi";
302 case AMDGPU::SCRATCH_WAVE_OFFSET_REG:
303 case AMDGPU::PRIVATE_RSRC_REG:
304 llvm_unreachable("pseudo-register should not ever be emitted");
309 // The low 8 bits of the encoding value is the register index, for both VGPRs
311 unsigned RegIdx = MRI.getEncodingValue(RegNo) & ((1 << 8) - 1);
314 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(RegNo)) {
317 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(RegNo)) {
320 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo)) {
323 } else if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo)) {
326 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(RegNo)) {
329 } else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(RegNo)) {
332 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(RegNo)) {
335 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(RegNo)) {
338 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(RegNo)) {
341 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(RegNo)) {
344 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(RegNo)) {
347 } else if (MRI.getRegClass(AMDGPU::TTMP_64RegClassID).contains(RegNo)) {
350 // Trap temps start at offset 112. TODO: Get this from tablegen.
352 } else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(RegNo)) {
355 // Trap temps start at offset 112. TODO: Get this from tablegen.
358 O << getRegisterName(RegNo);
367 O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
370 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
371 const MCSubtargetInfo &STI, raw_ostream &O) {
372 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
374 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
376 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
381 printOperand(MI, OpNo, STI, O);
384 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
385 const MCSubtargetInfo &STI,
387 int16_t SImm = static_cast<int16_t>(Imm);
388 if (SImm >= -16 && SImm <= 64) {
395 else if (Imm == 0xBC00)
397 else if (Imm == 0x3800)
399 else if (Imm == 0xB800)
401 else if (Imm == 0x4000)
403 else if (Imm == 0xC000)
405 else if (Imm == 0x4400)
407 else if (Imm == 0xC400)
409 else if (Imm == 0x3118) {
410 assert(STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]);
413 O << formatHex(static_cast<uint64_t>(Imm));
416 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
417 const MCSubtargetInfo &STI,
419 uint16_t Lo16 = static_cast<uint16_t>(Imm);
420 printImmediate16(Lo16, STI, O);
423 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
424 const MCSubtargetInfo &STI,
426 int32_t SImm = static_cast<int32_t>(Imm);
427 if (SImm >= -16 && SImm <= 64) {
432 if (Imm == FloatToBits(0.0f))
434 else if (Imm == FloatToBits(1.0f))
436 else if (Imm == FloatToBits(-1.0f))
438 else if (Imm == FloatToBits(0.5f))
440 else if (Imm == FloatToBits(-0.5f))
442 else if (Imm == FloatToBits(2.0f))
444 else if (Imm == FloatToBits(-2.0f))
446 else if (Imm == FloatToBits(4.0f))
448 else if (Imm == FloatToBits(-4.0f))
450 else if (Imm == 0x3e22f983 &&
451 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
454 O << formatHex(static_cast<uint64_t>(Imm));
457 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
458 const MCSubtargetInfo &STI,
460 int64_t SImm = static_cast<int64_t>(Imm);
461 if (SImm >= -16 && SImm <= 64) {
466 if (Imm == DoubleToBits(0.0))
468 else if (Imm == DoubleToBits(1.0))
470 else if (Imm == DoubleToBits(-1.0))
472 else if (Imm == DoubleToBits(0.5))
474 else if (Imm == DoubleToBits(-0.5))
476 else if (Imm == DoubleToBits(2.0))
478 else if (Imm == DoubleToBits(-2.0))
480 else if (Imm == DoubleToBits(4.0))
482 else if (Imm == DoubleToBits(-4.0))
484 else if (Imm == 0x3fc45f306dc9c882 &&
485 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
488 assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
490 // In rare situations, we will have a 32-bit literal in a 64-bit
491 // operand. This is technically allowed for the encoding of s_mov_b64.
492 O << formatHex(static_cast<uint64_t>(Imm));
496 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
497 const MCSubtargetInfo &STI,
499 if (OpNo >= MI->getNumOperands()) {
500 O << "/*Missing OP" << OpNo << "*/";
504 const MCOperand &Op = MI->getOperand(OpNo);
506 switch (Op.getReg()) {
507 // This is the default predicate state, so we don't need to print it.
508 case AMDGPU::PRED_SEL_OFF:
512 printRegOperand(Op.getReg(), O, MRI);
515 } else if (Op.isImm()) {
516 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
517 switch (Desc.OpInfo[OpNo].OperandType) {
518 case AMDGPU::OPERAND_REG_IMM_INT32:
519 case AMDGPU::OPERAND_REG_IMM_FP32:
520 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
521 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
522 case MCOI::OPERAND_IMMEDIATE:
523 printImmediate32(Op.getImm(), STI, O);
525 case AMDGPU::OPERAND_REG_IMM_INT64:
526 case AMDGPU::OPERAND_REG_IMM_FP64:
527 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
528 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
529 printImmediate64(Op.getImm(), STI, O);
531 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
532 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
533 case AMDGPU::OPERAND_REG_IMM_INT16:
534 case AMDGPU::OPERAND_REG_IMM_FP16:
535 printImmediate16(Op.getImm(), STI, O);
537 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
538 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
539 printImmediateV216(Op.getImm(), STI, O);
541 case MCOI::OPERAND_UNKNOWN:
542 case MCOI::OPERAND_PCREL:
543 O << formatDec(Op.getImm());
545 case MCOI::OPERAND_REGISTER:
546 // FIXME: This should be removed and handled somewhere else. Seems to come
547 // from a disassembler bug.
548 O << "/*invalid immediate*/";
551 // We hit this for the immediate instruction bits that don't yet have a
553 llvm_unreachable("unexpected immediate operand type");
555 } else if (Op.isFPImm()) {
556 // We special case 0.0 because otherwise it will be printed as an integer.
557 if (Op.getFPImm() == 0.0)
560 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
561 int RCID = Desc.OpInfo[OpNo].RegClass;
562 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
564 printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
565 else if (RCBits == 64)
566 printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
568 llvm_unreachable("Invalid register class size");
570 } else if (Op.isExpr()) {
571 const MCExpr *Exp = Op.getExpr();
578 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
580 const MCSubtargetInfo &STI,
582 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
584 // Use 'neg(...)' instead of '-' to avoid ambiguity.
585 // This is important for integer literals because
586 // -1 is not the same value as neg(1).
587 bool NegMnemo = false;
589 if (InputModifiers & SISrcMods::NEG) {
590 if (OpNo + 1 < MI->getNumOperands() &&
591 (InputModifiers & SISrcMods::ABS) == 0) {
592 const MCOperand &Op = MI->getOperand(OpNo + 1);
593 NegMnemo = Op.isImm() || Op.isFPImm();
602 if (InputModifiers & SISrcMods::ABS)
604 printOperand(MI, OpNo + 1, STI, O);
605 if (InputModifiers & SISrcMods::ABS)
613 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
615 const MCSubtargetInfo &STI,
617 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
618 if (InputModifiers & SISrcMods::SEXT)
620 printOperand(MI, OpNo + 1, STI, O);
621 if (InputModifiers & SISrcMods::SEXT)
625 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
626 const MCSubtargetInfo &STI,
628 unsigned Imm = MI->getOperand(OpNo).getImm();
631 O << formatDec(Imm & 0x3) << ',';
632 O << formatDec((Imm & 0xc) >> 2) << ',';
633 O << formatDec((Imm & 0x30) >> 4) << ',';
634 O << formatDec((Imm & 0xc0) >> 6) << ']';
635 } else if ((Imm >= 0x101) && (Imm <= 0x10f)) {
637 printU4ImmDecOperand(MI, OpNo, O);
638 } else if ((Imm >= 0x111) && (Imm <= 0x11f)) {
640 printU4ImmDecOperand(MI, OpNo, O);
641 } else if ((Imm >= 0x121) && (Imm <= 0x12f)) {
643 printU4ImmDecOperand(MI, OpNo, O);
644 } else if (Imm == 0x130) {
646 } else if (Imm == 0x134) {
648 } else if (Imm == 0x138) {
650 } else if (Imm == 0x13c) {
652 } else if (Imm == 0x140) {
654 } else if (Imm == 0x141) {
655 O << " row_half_mirror";
656 } else if (Imm == 0x142) {
657 O << " row_bcast:15";
658 } else if (Imm == 0x143) {
659 O << " row_bcast:31";
661 llvm_unreachable("Invalid dpp_ctrl value");
665 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
666 const MCSubtargetInfo &STI,
669 printU4ImmOperand(MI, OpNo, STI, O);
672 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
673 const MCSubtargetInfo &STI,
676 printU4ImmOperand(MI, OpNo, STI, O);
679 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
680 const MCSubtargetInfo &STI,
682 unsigned Imm = MI->getOperand(OpNo).getImm();
684 O << " bound_ctrl:0"; // XXX - this syntax is used in sp3
688 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
690 using namespace llvm::AMDGPU::SDWA;
692 unsigned Imm = MI->getOperand(OpNo).getImm();
694 case SdwaSel::BYTE_0: O << "BYTE_0"; break;
695 case SdwaSel::BYTE_1: O << "BYTE_1"; break;
696 case SdwaSel::BYTE_2: O << "BYTE_2"; break;
697 case SdwaSel::BYTE_3: O << "BYTE_3"; break;
698 case SdwaSel::WORD_0: O << "WORD_0"; break;
699 case SdwaSel::WORD_1: O << "WORD_1"; break;
700 case SdwaSel::DWORD: O << "DWORD"; break;
701 default: llvm_unreachable("Invalid SDWA data select operand");
705 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
706 const MCSubtargetInfo &STI,
709 printSDWASel(MI, OpNo, O);
712 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
713 const MCSubtargetInfo &STI,
716 printSDWASel(MI, OpNo, O);
719 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
720 const MCSubtargetInfo &STI,
723 printSDWASel(MI, OpNo, O);
726 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
727 const MCSubtargetInfo &STI,
729 using namespace llvm::AMDGPU::SDWA;
732 unsigned Imm = MI->getOperand(OpNo).getImm();
734 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
735 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
736 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
737 default: llvm_unreachable("Invalid SDWA dest_unused operand");
741 template <unsigned N>
742 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
743 const MCSubtargetInfo &STI,
745 unsigned Opc = MI->getOpcode();
746 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
747 unsigned En = MI->getOperand(EnIdx).getImm();
749 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
751 // If compr is set, print as src0, src0, src1, src1
752 if (MI->getOperand(ComprIdx).getImm()) {
753 if (N == 1 || N == 2)
760 printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
765 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
766 const MCSubtargetInfo &STI,
768 printExpSrcN<0>(MI, OpNo, STI, O);
771 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
772 const MCSubtargetInfo &STI,
774 printExpSrcN<1>(MI, OpNo, STI, O);
777 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
778 const MCSubtargetInfo &STI,
780 printExpSrcN<2>(MI, OpNo, STI, O);
783 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
784 const MCSubtargetInfo &STI,
786 printExpSrcN<3>(MI, OpNo, STI, O);
789 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
790 const MCSubtargetInfo &STI,
792 // This is really a 6 bit field.
793 uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
801 else if (Tgt >= 12 && Tgt <= 15)
802 O << " pos" << Tgt - 12;
803 else if (Tgt >= 32 && Tgt <= 63)
804 O << " param" << Tgt - 32;
806 // Reserved values 10, 11
807 O << " invalid_target_" << Tgt;
811 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod) {
812 int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
814 for (int I = 0; I < NumOps; ++I) {
815 if (!!(Ops[I] & Mod) != DefaultValue)
822 static void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
824 unsigned Opc = MI->getOpcode();
828 for (int OpName : { AMDGPU::OpName::src0_modifiers,
829 AMDGPU::OpName::src1_modifiers,
830 AMDGPU::OpName::src2_modifiers }) {
831 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
835 Ops[NumOps++] = MI->getOperand(Idx).getImm();
838 if (allOpsDefaultValue(Ops, NumOps, Mod))
842 for (int I = 0; I < NumOps; ++I) {
846 O << !!(Ops[I] & Mod);
852 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
853 const MCSubtargetInfo &STI,
855 printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
858 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
859 const MCSubtargetInfo &STI,
861 printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
864 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
865 const MCSubtargetInfo &STI,
867 printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
870 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
871 const MCSubtargetInfo &STI,
873 printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
876 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
877 const MCSubtargetInfo &STI,
879 unsigned Imm = MI->getOperand(OpNum).getImm();
891 O << "invalid_param_" << Imm;
895 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
896 const MCSubtargetInfo &STI,
898 unsigned Attr = MI->getOperand(OpNum).getImm();
902 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
903 const MCSubtargetInfo &STI,
905 unsigned Chan = MI->getOperand(OpNum).getImm();
906 O << '.' << "xyzw"[Chan & 0x3];
909 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
910 const MCSubtargetInfo &STI,
912 unsigned Val = MI->getOperand(OpNo).getImm();
918 if (Val & VGPRIndexMode::DST_ENABLE)
921 if (Val & VGPRIndexMode::SRC0_ENABLE)
924 if (Val & VGPRIndexMode::SRC1_ENABLE)
927 if (Val & VGPRIndexMode::SRC2_ENABLE)
931 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
932 const MCSubtargetInfo &STI,
934 printOperand(MI, OpNo, STI, O);
936 printOperand(MI, OpNo + 1, STI, O);
939 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
940 raw_ostream &O, StringRef Asm,
942 const MCOperand &Op = MI->getOperand(OpNo);
944 if (Op.getImm() == 1) {
951 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
952 raw_ostream &O, char Asm) {
953 const MCOperand &Op = MI->getOperand(OpNo);
955 if (Op.getImm() == 1)
959 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
960 const MCSubtargetInfo &STI, raw_ostream &O) {
961 printIfSet(MI, OpNo, O, '|');
964 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
965 const MCSubtargetInfo &STI, raw_ostream &O) {
966 printIfSet(MI, OpNo, O, "_SAT");
969 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
970 const MCSubtargetInfo &STI,
972 if (MI->getOperand(OpNo).getImm())
976 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
977 const MCSubtargetInfo &STI,
979 int Imm = MI->getOperand(OpNo).getImm();
980 if (Imm == SIOutMods::MUL2)
982 else if (Imm == SIOutMods::MUL4)
984 else if (Imm == SIOutMods::DIV2)
988 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
989 const MCSubtargetInfo &STI,
991 const MCOperand &Op = MI->getOperand(OpNo);
992 assert(Op.isImm() || Op.isExpr());
994 int64_t Imm = Op.getImm();
995 O << Imm << '(' << BitsToFloat(Imm) << ')';
998 Op.getExpr()->print(O << '@', &MAI);
1002 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
1003 const MCSubtargetInfo &STI, raw_ostream &O) {
1004 printIfSet(MI, OpNo, O, "*", " ");
1007 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
1008 const MCSubtargetInfo &STI, raw_ostream &O) {
1009 printIfSet(MI, OpNo, O, '-');
1012 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
1013 const MCSubtargetInfo &STI, raw_ostream &O) {
1014 switch (MI->getOperand(OpNo).getImm()) {
1028 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
1029 const MCSubtargetInfo &STI, raw_ostream &O) {
1030 printIfSet(MI, OpNo, O, '+');
1033 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
1034 const MCSubtargetInfo &STI,
1036 printIfSet(MI, OpNo, O, "ExecMask,");
1039 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
1040 const MCSubtargetInfo &STI,
1042 printIfSet(MI, OpNo, O, "Pred,");
1045 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
1046 const MCSubtargetInfo &STI, raw_ostream &O) {
1047 const MCOperand &Op = MI->getOperand(OpNo);
1048 if (Op.getImm() == 0) {
1053 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
1055 const char * chans = "XYZW";
1056 int sel = MI->getOperand(OpNo).getImm();
1065 O << cb << '[' << sel << ']';
1066 } else if (sel >= 448) {
1069 } else if (sel >= 0){
1074 O << '.' << chans[chan];
1077 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
1078 const MCSubtargetInfo &STI,
1080 int BankSwizzle = MI->getOperand(OpNo).getImm();
1081 switch (BankSwizzle) {
1083 O << "BS:VEC_021/SCL_122";
1086 O << "BS:VEC_120/SCL_212";
1089 O << "BS:VEC_102/SCL_221";
1102 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
1103 const MCSubtargetInfo &STI, raw_ostream &O) {
1104 unsigned Sel = MI->getOperand(OpNo).getImm();
1132 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
1133 const MCSubtargetInfo &STI, raw_ostream &O) {
1134 unsigned CT = MI->getOperand(OpNo).getImm();
1147 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1148 const MCSubtargetInfo &STI, raw_ostream &O) {
1149 int KCacheMode = MI->getOperand(OpNo).getImm();
1150 if (KCacheMode > 0) {
1151 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1152 O << "CB" << KCacheBank << ':';
1153 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1154 int LineSize = (KCacheMode == 1) ? 16 : 32;
1155 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1159 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1160 const MCSubtargetInfo &STI,
1162 using namespace llvm::AMDGPU::SendMsg;
1164 const unsigned SImm16 = MI->getOperand(OpNo).getImm();
1165 const unsigned Id = SImm16 & ID_MASK_;
1167 if (Id == ID_INTERRUPT) {
1168 if ((SImm16 & ~ID_MASK_) != 0) // Unused/unknown bits must be 0.
1170 O << "sendmsg(" << IdSymbolic[Id] << ')';
1173 if (Id == ID_GS || Id == ID_GS_DONE) {
1174 if ((SImm16 & ~(ID_MASK_|OP_GS_MASK_|STREAM_ID_MASK_)) != 0) // Unused/unknown bits must be 0.
1176 const unsigned OpGs = (SImm16 & OP_GS_MASK_) >> OP_SHIFT_;
1177 const unsigned StreamId = (SImm16 & STREAM_ID_MASK_) >> STREAM_ID_SHIFT_;
1178 if (OpGs == OP_GS_NOP && Id != ID_GS_DONE) // NOP to be used for GS_DONE only.
1180 if (OpGs == OP_GS_NOP && StreamId != 0) // NOP does not use/define stream id bits.
1182 O << "sendmsg(" << IdSymbolic[Id] << ", " << OpGsSymbolic[OpGs];
1183 if (OpGs != OP_GS_NOP) { O << ", " << StreamId; }
1187 if (Id == ID_SYSMSG) {
1188 if ((SImm16 & ~(ID_MASK_|OP_SYS_MASK_)) != 0) // Unused/unknown bits must be 0.
1190 const unsigned OpSys = (SImm16 & OP_SYS_MASK_) >> OP_SHIFT_;
1191 if (! (OP_SYS_FIRST_ <= OpSys && OpSys < OP_SYS_LAST_)) // Unused/unknown.
1193 O << "sendmsg(" << IdSymbolic[Id] << ", " << OpSysSymbolic[OpSys] << ')';
1197 O << SImm16; // Unknown simm16 code.
1200 static void printSwizzleBitmask(const uint16_t AndMask,
1201 const uint16_t OrMask,
1202 const uint16_t XorMask,
1204 using namespace llvm::AMDGPU::Swizzle;
1206 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1207 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1211 for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1212 uint16_t p0 = Probe0 & Mask;
1213 uint16_t p1 = Probe1 & Mask;
1233 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1234 const MCSubtargetInfo &STI,
1236 using namespace llvm::AMDGPU::Swizzle;
1238 uint16_t Imm = MI->getOperand(OpNo).getImm();
1245 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1247 O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1248 for (auto i = 0; i < LANE_NUM; ++i) {
1250 O << formatDec(Imm & LANE_MASK);
1255 } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1257 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1258 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1259 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1261 if (AndMask == BITMASK_MAX &&
1263 countPopulation(XorMask) == 1) {
1265 O << "swizzle(" << IdSymbolic[ID_SWAP];
1267 O << formatDec(XorMask);
1270 } else if (AndMask == BITMASK_MAX &&
1271 OrMask == 0 && XorMask > 0 &&
1272 isPowerOf2_64(XorMask + 1)) {
1274 O << "swizzle(" << IdSymbolic[ID_REVERSE];
1276 O << formatDec(XorMask + 1);
1281 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1282 if (GroupSize > 1 &&
1283 isPowerOf2_64(GroupSize) &&
1284 OrMask < GroupSize &&
1287 O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1289 O << formatDec(GroupSize);
1291 O << formatDec(OrMask);
1295 O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1297 printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1302 printU16ImmDecOperand(MI, OpNo, O);
1306 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1307 const MCSubtargetInfo &STI,
1309 AMDGPU::IsaInfo::IsaVersion ISA =
1310 AMDGPU::IsaInfo::getIsaVersion(STI.getFeatureBits());
1312 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1313 unsigned Vmcnt, Expcnt, Lgkmcnt;
1314 decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1316 bool NeedSpace = false;
1318 if (Vmcnt != getVmcntBitMask(ISA)) {
1319 O << "vmcnt(" << Vmcnt << ')';
1323 if (Expcnt != getExpcntBitMask(ISA)) {
1326 O << "expcnt(" << Expcnt << ')';
1330 if (Lgkmcnt != getLgkmcntBitMask(ISA)) {
1333 O << "lgkmcnt(" << Lgkmcnt << ')';
1337 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1338 const MCSubtargetInfo &STI, raw_ostream &O) {
1339 using namespace llvm::AMDGPU::Hwreg;
1341 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1342 const unsigned Id = (SImm16 & ID_MASK_) >> ID_SHIFT_;
1343 const unsigned Offset = (SImm16 & OFFSET_MASK_) >> OFFSET_SHIFT_;
1344 const unsigned Width = ((SImm16 & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
1347 if (ID_SYMBOLIC_FIRST_ <= Id && Id < ID_SYMBOLIC_LAST_) {
1348 O << IdSymbolic[Id];
1352 if (Width != WIDTH_M1_DEFAULT_ + 1 || Offset != OFFSET_DEFAULT_) {
1353 O << ", " << Offset << ", " << Width;
1358 #include "AMDGPUGenAsmWriter.inc"