1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "SIDefines.h"
13 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14 #include "Utils/AMDGPUAsmUtils.h"
15 #include "Utils/AMDGPUBaseInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
28 using namespace llvm::AMDGPU;
30 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
31 StringRef Annot, const MCSubtargetInfo &STI) {
33 printInstruction(MI, STI, OS);
34 printAnnotation(OS, Annot);
37 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
38 const MCSubtargetInfo &STI,
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
43 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
45 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
48 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
49 const MCSubtargetInfo &STI,
51 // It's possible to end up with a 32-bit literal used with a 16-bit operand
52 // with ignored high bits. Print as 32-bit anyway in that case.
53 int64_t Imm = MI->getOperand(OpNo).getImm();
54 if (isInt<16>(Imm) || isUInt<16>(Imm))
55 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
57 printU32ImmOperand(MI, OpNo, STI, O);
60 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
62 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
65 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
67 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
70 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
72 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
75 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
76 const MCSubtargetInfo &STI,
78 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
81 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
82 raw_ostream &O, StringRef BitName) {
83 if (MI->getOperand(OpNo).getImm()) {
88 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
90 printNamedBit(MI, OpNo, O, "offen");
93 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
95 printNamedBit(MI, OpNo, O, "idxen");
98 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
100 printNamedBit(MI, OpNo, O, "addr64");
103 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
105 if (MI->getOperand(OpNo).getImm()) {
107 printU16ImmDecOperand(MI, OpNo, O);
111 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
112 const MCSubtargetInfo &STI,
114 uint16_t Imm = MI->getOperand(OpNo).getImm();
117 printU16ImmDecOperand(MI, OpNo, O);
121 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
122 const MCSubtargetInfo &STI,
124 if (MI->getOperand(OpNo).getImm()) {
126 printU8ImmDecOperand(MI, OpNo, O);
130 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
131 const MCSubtargetInfo &STI,
133 if (MI->getOperand(OpNo).getImm()) {
135 printU8ImmDecOperand(MI, OpNo, O);
139 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
140 const MCSubtargetInfo &STI,
142 printU32ImmOperand(MI, OpNo, STI, O);
145 void AMDGPUInstPrinter::printSMRDOffset20(const MCInst *MI, unsigned OpNo,
146 const MCSubtargetInfo &STI,
148 printU32ImmOperand(MI, OpNo, STI, O);
151 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
152 const MCSubtargetInfo &STI,
154 printU32ImmOperand(MI, OpNo, STI, O);
157 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
158 const MCSubtargetInfo &STI, raw_ostream &O) {
159 printNamedBit(MI, OpNo, O, "gds");
162 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
163 const MCSubtargetInfo &STI, raw_ostream &O) {
164 printNamedBit(MI, OpNo, O, "glc");
167 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
168 const MCSubtargetInfo &STI, raw_ostream &O) {
169 printNamedBit(MI, OpNo, O, "slc");
172 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
173 const MCSubtargetInfo &STI, raw_ostream &O) {
174 printNamedBit(MI, OpNo, O, "tfe");
177 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
178 const MCSubtargetInfo &STI, raw_ostream &O) {
179 if (MI->getOperand(OpNo).getImm()) {
181 printU16ImmOperand(MI, OpNo, STI, O);
185 void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
186 const MCSubtargetInfo &STI, raw_ostream &O) {
187 printNamedBit(MI, OpNo, O, "unorm");
190 void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
191 const MCSubtargetInfo &STI, raw_ostream &O) {
192 printNamedBit(MI, OpNo, O, "da");
195 void AMDGPUInstPrinter::printR128(const MCInst *MI, unsigned OpNo,
196 const MCSubtargetInfo &STI, raw_ostream &O) {
197 printNamedBit(MI, OpNo, O, "r128");
200 void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
201 const MCSubtargetInfo &STI, raw_ostream &O) {
202 printNamedBit(MI, OpNo, O, "lwe");
205 void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
206 const MCSubtargetInfo &STI,
208 if (MI->getOperand(OpNo).getImm())
212 void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
213 const MCSubtargetInfo &STI,
215 if (MI->getOperand(OpNo).getImm())
219 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
220 const MCRegisterInfo &MRI) {
234 case AMDGPU::FLAT_SCR:
255 case AMDGPU::EXEC_LO:
258 case AMDGPU::EXEC_HI:
261 case AMDGPU::FLAT_SCR_LO:
262 O << "flat_scratch_lo";
264 case AMDGPU::FLAT_SCR_HI:
265 O << "flat_scratch_hi";
271 // The low 8 bits of the encoding value is the register index, for both VGPRs
273 unsigned RegIdx = MRI.getEncodingValue(RegNo) & ((1 << 8) - 1);
276 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(RegNo)) {
279 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(RegNo)) {
282 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo)) {
285 } else if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo)) {
288 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(RegNo)) {
291 } else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(RegNo)) {
294 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(RegNo)) {
297 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(RegNo)) {
300 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(RegNo)) {
303 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(RegNo)) {
306 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(RegNo)) {
309 } else if (MRI.getRegClass(AMDGPU::TTMP_64RegClassID).contains(RegNo)) {
312 // Trap temps start at offset 112. TODO: Get this from tablegen.
314 } else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(RegNo)) {
317 // Trap temps start at offset 112. TODO: Get this from tablegen.
320 O << getRegisterName(RegNo);
329 O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
332 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
333 const MCSubtargetInfo &STI, raw_ostream &O) {
334 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
336 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
338 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
343 printOperand(MI, OpNo, STI, O);
346 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
347 const MCSubtargetInfo &STI,
349 int16_t SImm = static_cast<int16_t>(Imm);
350 if (SImm >= -16 && SImm <= 64) {
357 else if (Imm == 0xBC00)
359 else if (Imm == 0x3800)
361 else if (Imm == 0xB800)
363 else if (Imm == 0x4000)
365 else if (Imm == 0xC000)
367 else if (Imm == 0x4400)
369 else if (Imm == 0xC400)
371 else if (Imm == 0x3118) {
372 assert(STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]);
375 O << formatHex(static_cast<uint64_t>(Imm));
378 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
379 const MCSubtargetInfo &STI,
381 int32_t SImm = static_cast<int32_t>(Imm);
382 if (SImm >= -16 && SImm <= 64) {
387 if (Imm == FloatToBits(0.0f))
389 else if (Imm == FloatToBits(1.0f))
391 else if (Imm == FloatToBits(-1.0f))
393 else if (Imm == FloatToBits(0.5f))
395 else if (Imm == FloatToBits(-0.5f))
397 else if (Imm == FloatToBits(2.0f))
399 else if (Imm == FloatToBits(-2.0f))
401 else if (Imm == FloatToBits(4.0f))
403 else if (Imm == FloatToBits(-4.0f))
405 else if (Imm == 0x3e22f983 &&
406 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
409 O << formatHex(static_cast<uint64_t>(Imm));
412 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
413 const MCSubtargetInfo &STI,
415 int64_t SImm = static_cast<int64_t>(Imm);
416 if (SImm >= -16 && SImm <= 64) {
421 if (Imm == DoubleToBits(0.0))
423 else if (Imm == DoubleToBits(1.0))
425 else if (Imm == DoubleToBits(-1.0))
427 else if (Imm == DoubleToBits(0.5))
429 else if (Imm == DoubleToBits(-0.5))
431 else if (Imm == DoubleToBits(2.0))
433 else if (Imm == DoubleToBits(-2.0))
435 else if (Imm == DoubleToBits(4.0))
437 else if (Imm == DoubleToBits(-4.0))
439 else if (Imm == 0x3fc45f306dc9c882 &&
440 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
443 assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
445 // In rare situations, we will have a 32-bit literal in a 64-bit
446 // operand. This is technically allowed for the encoding of s_mov_b64.
447 O << formatHex(static_cast<uint64_t>(Imm));
451 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
452 const MCSubtargetInfo &STI,
454 if (OpNo >= MI->getNumOperands()) {
455 O << "/*Missing OP" << OpNo << "*/";
459 const MCOperand &Op = MI->getOperand(OpNo);
461 switch (Op.getReg()) {
462 // This is the default predicate state, so we don't need to print it.
463 case AMDGPU::PRED_SEL_OFF:
467 printRegOperand(Op.getReg(), O, MRI);
470 } else if (Op.isImm()) {
471 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
472 switch (Desc.OpInfo[OpNo].OperandType) {
473 case AMDGPU::OPERAND_REG_IMM_INT32:
474 case AMDGPU::OPERAND_REG_IMM_FP32:
475 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
476 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
477 case MCOI::OPERAND_IMMEDIATE:
478 printImmediate32(Op.getImm(), STI, O);
480 case AMDGPU::OPERAND_REG_IMM_INT64:
481 case AMDGPU::OPERAND_REG_IMM_FP64:
482 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
483 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
484 printImmediate64(Op.getImm(), STI, O);
486 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
487 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
488 case AMDGPU::OPERAND_REG_IMM_INT16:
489 case AMDGPU::OPERAND_REG_IMM_FP16:
490 printImmediate16(Op.getImm(), STI, O);
492 case MCOI::OPERAND_UNKNOWN:
493 case MCOI::OPERAND_PCREL:
494 O << formatDec(Op.getImm());
496 case MCOI::OPERAND_REGISTER:
497 // FIXME: This should be removed and handled somewhere else. Seems to come
498 // from a disassembler bug.
499 O << "/*invalid immediate*/";
502 // We hit this for the immediate instruction bits that don't yet have a
504 llvm_unreachable("unexpected immediate operand type");
506 } else if (Op.isFPImm()) {
507 // We special case 0.0 because otherwise it will be printed as an integer.
508 if (Op.getFPImm() == 0.0)
511 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
512 int RCID = Desc.OpInfo[OpNo].RegClass;
513 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
515 printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
516 else if (RCBits == 64)
517 printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
519 llvm_unreachable("Invalid register class size");
521 } else if (Op.isExpr()) {
522 const MCExpr *Exp = Op.getExpr();
529 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
531 const MCSubtargetInfo &STI,
533 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
534 if (InputModifiers & SISrcMods::NEG)
536 if (InputModifiers & SISrcMods::ABS)
538 printOperand(MI, OpNo + 1, STI, O);
539 if (InputModifiers & SISrcMods::ABS)
543 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
545 const MCSubtargetInfo &STI,
547 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
548 if (InputModifiers & SISrcMods::SEXT)
550 printOperand(MI, OpNo + 1, STI, O);
551 if (InputModifiers & SISrcMods::SEXT)
555 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
556 const MCSubtargetInfo &STI,
558 unsigned Imm = MI->getOperand(OpNo).getImm();
561 O << formatDec(Imm & 0x3) << ',';
562 O << formatDec((Imm & 0xc) >> 2) << ',';
563 O << formatDec((Imm & 0x30) >> 4) << ',';
564 O << formatDec((Imm & 0xc0) >> 6) << ']';
565 } else if ((Imm >= 0x101) && (Imm <= 0x10f)) {
567 printU4ImmDecOperand(MI, OpNo, O);
568 } else if ((Imm >= 0x111) && (Imm <= 0x11f)) {
570 printU4ImmDecOperand(MI, OpNo, O);
571 } else if ((Imm >= 0x121) && (Imm <= 0x12f)) {
573 printU4ImmDecOperand(MI, OpNo, O);
574 } else if (Imm == 0x130) {
576 } else if (Imm == 0x134) {
578 } else if (Imm == 0x138) {
580 } else if (Imm == 0x13c) {
582 } else if (Imm == 0x140) {
584 } else if (Imm == 0x141) {
585 O << " row_half_mirror";
586 } else if (Imm == 0x142) {
587 O << " row_bcast:15";
588 } else if (Imm == 0x143) {
589 O << " row_bcast:31";
591 llvm_unreachable("Invalid dpp_ctrl value");
595 void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo,
596 const MCSubtargetInfo &STI,
599 printU4ImmOperand(MI, OpNo, STI, O);
602 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
603 const MCSubtargetInfo &STI,
606 printU4ImmOperand(MI, OpNo, STI, O);
609 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
610 const MCSubtargetInfo &STI,
612 unsigned Imm = MI->getOperand(OpNo).getImm();
614 O << " bound_ctrl:0"; // XXX - this syntax is used in sp3
618 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
620 using namespace llvm::AMDGPU::SDWA;
622 unsigned Imm = MI->getOperand(OpNo).getImm();
624 case SdwaSel::BYTE_0: O << "BYTE_0"; break;
625 case SdwaSel::BYTE_1: O << "BYTE_1"; break;
626 case SdwaSel::BYTE_2: O << "BYTE_2"; break;
627 case SdwaSel::BYTE_3: O << "BYTE_3"; break;
628 case SdwaSel::WORD_0: O << "WORD_0"; break;
629 case SdwaSel::WORD_1: O << "WORD_1"; break;
630 case SdwaSel::DWORD: O << "DWORD"; break;
631 default: llvm_unreachable("Invalid SDWA data select operand");
635 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
636 const MCSubtargetInfo &STI,
639 printSDWASel(MI, OpNo, O);
642 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
643 const MCSubtargetInfo &STI,
646 printSDWASel(MI, OpNo, O);
649 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
650 const MCSubtargetInfo &STI,
653 printSDWASel(MI, OpNo, O);
656 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
657 const MCSubtargetInfo &STI,
659 using namespace llvm::AMDGPU::SDWA;
662 unsigned Imm = MI->getOperand(OpNo).getImm();
664 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
665 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
666 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
667 default: llvm_unreachable("Invalid SDWA dest_unused operand");
671 template <unsigned N>
672 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
673 const MCSubtargetInfo &STI,
675 int EnIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::en);
676 unsigned En = MI->getOperand(EnIdx).getImm();
678 // FIXME: What do we do with compr? The meaning of en changes depending on if
682 printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
687 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
688 const MCSubtargetInfo &STI,
690 printExpSrcN<0>(MI, OpNo, STI, O);
693 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
694 const MCSubtargetInfo &STI,
696 printExpSrcN<1>(MI, OpNo, STI, O);
699 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
700 const MCSubtargetInfo &STI,
702 printExpSrcN<2>(MI, OpNo, STI, O);
705 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
706 const MCSubtargetInfo &STI,
708 printExpSrcN<3>(MI, OpNo, STI, O);
711 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
712 const MCSubtargetInfo &STI,
714 // This is really a 6 bit field.
715 uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
723 else if (Tgt >= 12 && Tgt <= 15)
724 O << " pos" << Tgt - 12;
725 else if (Tgt >= 32 && Tgt <= 63)
726 O << " param" << Tgt - 32;
728 // Reserved values 10, 11
729 O << " invalid_target_" << Tgt;
733 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
734 const MCSubtargetInfo &STI,
736 unsigned Imm = MI->getOperand(OpNum).getImm();
748 O << "invalid_param_" << Imm;
752 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
753 const MCSubtargetInfo &STI,
755 unsigned Attr = MI->getOperand(OpNum).getImm();
759 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
760 const MCSubtargetInfo &STI,
762 unsigned Chan = MI->getOperand(OpNum).getImm();
763 O << '.' << "xyzw"[Chan & 0x3];
766 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
767 const MCSubtargetInfo &STI,
769 unsigned Val = MI->getOperand(OpNo).getImm();
775 if (Val & VGPRIndexMode::DST_ENABLE)
778 if (Val & VGPRIndexMode::SRC0_ENABLE)
781 if (Val & VGPRIndexMode::SRC1_ENABLE)
784 if (Val & VGPRIndexMode::SRC2_ENABLE)
788 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
789 const MCSubtargetInfo &STI,
791 printOperand(MI, OpNo, STI, O);
793 printOperand(MI, OpNo + 1, STI, O);
796 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
797 raw_ostream &O, StringRef Asm,
799 const MCOperand &Op = MI->getOperand(OpNo);
801 if (Op.getImm() == 1) {
808 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
809 raw_ostream &O, char Asm) {
810 const MCOperand &Op = MI->getOperand(OpNo);
812 if (Op.getImm() == 1)
816 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
817 const MCSubtargetInfo &STI, raw_ostream &O) {
818 printIfSet(MI, OpNo, O, '|');
821 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
822 const MCSubtargetInfo &STI, raw_ostream &O) {
823 printIfSet(MI, OpNo, O, "_SAT");
826 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
827 const MCSubtargetInfo &STI,
829 if (MI->getOperand(OpNo).getImm())
833 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
834 const MCSubtargetInfo &STI,
836 int Imm = MI->getOperand(OpNo).getImm();
837 if (Imm == SIOutMods::MUL2)
839 else if (Imm == SIOutMods::MUL4)
841 else if (Imm == SIOutMods::DIV2)
845 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
846 const MCSubtargetInfo &STI,
848 const MCOperand &Op = MI->getOperand(OpNo);
849 assert(Op.isImm() || Op.isExpr());
851 int64_t Imm = Op.getImm();
852 O << Imm << '(' << BitsToFloat(Imm) << ')';
855 Op.getExpr()->print(O << '@', &MAI);
859 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
860 const MCSubtargetInfo &STI, raw_ostream &O) {
861 printIfSet(MI, OpNo, O, "*", " ");
864 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
865 const MCSubtargetInfo &STI, raw_ostream &O) {
866 printIfSet(MI, OpNo, O, '-');
869 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
870 const MCSubtargetInfo &STI, raw_ostream &O) {
871 switch (MI->getOperand(OpNo).getImm()) {
885 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
886 const MCSubtargetInfo &STI, raw_ostream &O) {
887 printIfSet(MI, OpNo, O, '+');
890 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
891 const MCSubtargetInfo &STI,
893 printIfSet(MI, OpNo, O, "ExecMask,");
896 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
897 const MCSubtargetInfo &STI,
899 printIfSet(MI, OpNo, O, "Pred,");
902 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
903 const MCSubtargetInfo &STI, raw_ostream &O) {
904 const MCOperand &Op = MI->getOperand(OpNo);
905 if (Op.getImm() == 0) {
910 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
912 const char * chans = "XYZW";
913 int sel = MI->getOperand(OpNo).getImm();
922 O << cb << '[' << sel << ']';
923 } else if (sel >= 448) {
926 } else if (sel >= 0){
931 O << '.' << chans[chan];
934 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
935 const MCSubtargetInfo &STI,
937 int BankSwizzle = MI->getOperand(OpNo).getImm();
938 switch (BankSwizzle) {
940 O << "BS:VEC_021/SCL_122";
943 O << "BS:VEC_120/SCL_212";
946 O << "BS:VEC_102/SCL_221";
959 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
960 const MCSubtargetInfo &STI, raw_ostream &O) {
961 unsigned Sel = MI->getOperand(OpNo).getImm();
989 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
990 const MCSubtargetInfo &STI, raw_ostream &O) {
991 unsigned CT = MI->getOperand(OpNo).getImm();
1004 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
1005 const MCSubtargetInfo &STI, raw_ostream &O) {
1006 int KCacheMode = MI->getOperand(OpNo).getImm();
1007 if (KCacheMode > 0) {
1008 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
1009 O << "CB" << KCacheBank << ':';
1010 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
1011 int LineSize = (KCacheMode == 1) ? 16 : 32;
1012 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
1016 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1017 const MCSubtargetInfo &STI,
1019 using namespace llvm::AMDGPU::SendMsg;
1021 const unsigned SImm16 = MI->getOperand(OpNo).getImm();
1022 const unsigned Id = SImm16 & ID_MASK_;
1024 if (Id == ID_INTERRUPT) {
1025 if ((SImm16 & ~ID_MASK_) != 0) // Unused/unknown bits must be 0.
1027 O << "sendmsg(" << IdSymbolic[Id] << ')';
1030 if (Id == ID_GS || Id == ID_GS_DONE) {
1031 if ((SImm16 & ~(ID_MASK_|OP_GS_MASK_|STREAM_ID_MASK_)) != 0) // Unused/unknown bits must be 0.
1033 const unsigned OpGs = (SImm16 & OP_GS_MASK_) >> OP_SHIFT_;
1034 const unsigned StreamId = (SImm16 & STREAM_ID_MASK_) >> STREAM_ID_SHIFT_;
1035 if (OpGs == OP_GS_NOP && Id != ID_GS_DONE) // NOP to be used for GS_DONE only.
1037 if (OpGs == OP_GS_NOP && StreamId != 0) // NOP does not use/define stream id bits.
1039 O << "sendmsg(" << IdSymbolic[Id] << ", " << OpGsSymbolic[OpGs];
1040 if (OpGs != OP_GS_NOP) { O << ", " << StreamId; }
1044 if (Id == ID_SYSMSG) {
1045 if ((SImm16 & ~(ID_MASK_|OP_SYS_MASK_)) != 0) // Unused/unknown bits must be 0.
1047 const unsigned OpSys = (SImm16 & OP_SYS_MASK_) >> OP_SHIFT_;
1048 if (! (OP_SYS_FIRST_ <= OpSys && OpSys < OP_SYS_LAST_)) // Unused/unknown.
1050 O << "sendmsg(" << IdSymbolic[Id] << ", " << OpSysSymbolic[OpSys] << ')';
1054 O << SImm16; // Unknown simm16 code.
1057 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
1058 const MCSubtargetInfo &STI,
1060 IsaVersion IV = getIsaVersion(STI.getFeatureBits());
1062 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1063 unsigned Vmcnt, Expcnt, Lgkmcnt;
1064 decodeWaitcnt(IV, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1066 bool NeedSpace = false;
1068 if (Vmcnt != getVmcntBitMask(IV)) {
1069 O << "vmcnt(" << Vmcnt << ')';
1073 if (Expcnt != getExpcntBitMask(IV)) {
1076 O << "expcnt(" << Expcnt << ')';
1080 if (Lgkmcnt != getLgkmcntBitMask(IV)) {
1083 O << "lgkmcnt(" << Lgkmcnt << ')';
1087 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1088 const MCSubtargetInfo &STI, raw_ostream &O) {
1089 using namespace llvm::AMDGPU::Hwreg;
1091 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1092 const unsigned Id = (SImm16 & ID_MASK_) >> ID_SHIFT_;
1093 const unsigned Offset = (SImm16 & OFFSET_MASK_) >> OFFSET_SHIFT_;
1094 const unsigned Width = ((SImm16 & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
1097 if (ID_SYMBOLIC_FIRST_ <= Id && Id < ID_SYMBOLIC_LAST_) {
1098 O << IdSymbolic[Id];
1102 if (Width != WIDTH_M1_DEFAULT_ + 1 || Offset != OFFSET_DEFAULT_) {
1103 O << ", " << Offset << ", " << Width;
1108 #include "AMDGPUGenAsmWriter.inc"