contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

   1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief This file provides AMDGPU specific target descriptions.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AMDGPUMCTargetDesc.h"
  16 #include "AMDGPUELFStreamer.h"
  17 #include "AMDGPUMCAsmInfo.h"
  18 #include "AMDGPUTargetStreamer.h"
  19 #include "InstPrinter/AMDGPUInstPrinter.h"
  20 #include "SIDefines.h"
  21 #include "llvm/MC/MCAsmBackend.h"
  22 #include "llvm/MC/MCCodeEmitter.h"
  23 #include "llvm/MC/MCContext.h"
  24 #include "llvm/MC/MCInstrInfo.h"
  25 #include "llvm/MC/MCRegisterInfo.h"
  26 #include "llvm/MC/MCStreamer.h"
  27 #include "llvm/MC/MCSubtargetInfo.h"
  28 #include "llvm/MC/MachineLocation.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/TargetRegistry.h"
  31
  32 using namespace llvm;
  33
  34 #define GET_INSTRINFO_MC_DESC
  35 #include "AMDGPUGenInstrInfo.inc"
  36
  37 #define GET_SUBTARGETINFO_MC_DESC
  38 #include "AMDGPUGenSubtargetInfo.inc"
  39
  40 #define GET_REGINFO_MC_DESC
  41 #include "AMDGPUGenRegisterInfo.inc"
  42
  43 static MCInstrInfo *createAMDGPUMCInstrInfo() {
  44   MCInstrInfo *X = new MCInstrInfo();
  45   InitAMDGPUMCInstrInfo(X);
  46   return X;
  47 }
  48
  49 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
  50   MCRegisterInfo *X = new MCRegisterInfo();
  51   InitAMDGPUMCRegisterInfo(X, 0);
  52   return X;
  53 }
  54
  55 static MCSubtargetInfo *
  56 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
  57   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
  58 }
  59
  60 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
  61                                                 unsigned SyntaxVariant,
  62                                                 const MCAsmInfo &MAI,
  63                                                 const MCInstrInfo &MII,
  64                                                 const MCRegisterInfo &MRI) {
  65   return T.getArch() == Triple::r600 ? new R600InstPrinter(MAI, MII, MRI) :
  66                                        new AMDGPUInstPrinter(MAI, MII, MRI);
  67 }
  68
  69 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
  70                                                       formatted_raw_ostream &OS,
  71                                                       MCInstPrinter *InstPrint,
  72                                                       bool isVerboseAsm) {
  73   return new AMDGPUTargetAsmStreamer(S, OS);
  74 }
  75
  76 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
  77                                                    MCStreamer &S,
  78                                                    const MCSubtargetInfo &STI) {
  79   return new AMDGPUTargetELFStreamer(S);
  80 }
  81
  82 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
  83                                     std::unique_ptr<MCAsmBackend> &&MAB,
  84                                     raw_pwrite_stream &OS,
  85                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
  86                                     bool RelaxAll) {
  87   return createAMDGPUELFStreamer(T, Context, std::move(MAB), OS,
  88                                  std::move(Emitter), RelaxAll);
  89 }
  90
  91 extern "C" void LLVMInitializeAMDGPUTargetMC() {
  92   for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
  93     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
  94
  95     TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
  96     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
  97     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
  98     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
  99     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
 100     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
 101   }
 102
 103   // R600 specific registration
 104   TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
 105                                         createR600MCCodeEmitter);
 106
 107   // GCN specific registration
 108   TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
 109                                         createSIMCCodeEmitter);
 110
 111   TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
 112                                             createAMDGPUAsmTargetStreamer);
 113   TargetRegistry::RegisterObjectTargetStreamer(
 114       getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
 115 }