contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

   1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// This file provides AMDGPU specific target descriptions.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AMDGPUMCTargetDesc.h"
  16 #include "AMDGPUELFStreamer.h"
  17 #include "AMDGPUMCAsmInfo.h"
  18 #include "AMDGPUTargetStreamer.h"
  19 #include "InstPrinter/AMDGPUInstPrinter.h"
  20 #include "SIDefines.h"
  21 #include "llvm/MC/MCAsmBackend.h"
  22 #include "llvm/MC/MCCodeEmitter.h"
  23 #include "llvm/MC/MCContext.h"
  24 #include "llvm/MC/MCInstrInfo.h"
  25 #include "llvm/MC/MCObjectWriter.h"
  26 #include "llvm/MC/MCRegisterInfo.h"
  27 #include "llvm/MC/MCStreamer.h"
  28 #include "llvm/MC/MCSubtargetInfo.h"
  29 #include "llvm/MC/MachineLocation.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32
  33 using namespace llvm;
  34
  35 #define GET_INSTRINFO_MC_DESC
  36 #include "AMDGPUGenInstrInfo.inc"
  37
  38 #define GET_SUBTARGETINFO_MC_DESC
  39 #include "AMDGPUGenSubtargetInfo.inc"
  40
  41 #define NoSchedModel NoSchedModelR600
  42 #define GET_SUBTARGETINFO_MC_DESC
  43 #include "R600GenSubtargetInfo.inc"
  44 #undef NoSchedModelR600
  45
  46 #define GET_REGINFO_MC_DESC
  47 #include "AMDGPUGenRegisterInfo.inc"
  48
  49 #define GET_REGINFO_MC_DESC
  50 #include "R600GenRegisterInfo.inc"
  51
  52 static MCInstrInfo *createAMDGPUMCInstrInfo() {
  53   MCInstrInfo *X = new MCInstrInfo();
  54   InitAMDGPUMCInstrInfo(X);
  55   return X;
  56 }
  57
  58 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
  59   MCRegisterInfo *X = new MCRegisterInfo();
  60   if (TT.getArch() == Triple::r600)
  61     InitR600MCRegisterInfo(X, 0);
  62   else
  63     InitAMDGPUMCRegisterInfo(X, 0);
  64   return X;
  65 }
  66
  67 static MCSubtargetInfo *
  68 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
  69   if (TT.getArch() == Triple::r600)
  70     return createR600MCSubtargetInfoImpl(TT, CPU, FS);
  71   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
  72 }
  73
  74 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
  75                                                 unsigned SyntaxVariant,
  76                                                 const MCAsmInfo &MAI,
  77                                                 const MCInstrInfo &MII,
  78                                                 const MCRegisterInfo &MRI) {
  79   if (T.getArch() == Triple::r600)
  80     return new R600InstPrinter(MAI, MII, MRI);
  81   else
  82     return new AMDGPUInstPrinter(MAI, MII, MRI);
  83 }
  84
  85 static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
  86                                                       formatted_raw_ostream &OS,
  87                                                       MCInstPrinter *InstPrint,
  88                                                       bool isVerboseAsm) {
  89   return new AMDGPUTargetAsmStreamer(S, OS);
  90 }
  91
  92 static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
  93                                                    MCStreamer &S,
  94                                                    const MCSubtargetInfo &STI) {
  95   return new AMDGPUTargetELFStreamer(S, STI);
  96 }
  97
  98 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
  99                                     std::unique_ptr<MCAsmBackend> &&MAB,
 100                                     std::unique_ptr<MCObjectWriter> &&OW,
 101                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
 102                                     bool RelaxAll) {
 103   return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
 104                                  std::move(Emitter), RelaxAll);
 105 }
 106
 107 extern "C" void LLVMInitializeAMDGPUTargetMC() {
 108
 109   TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo);
 110   TargetRegistry::RegisterMCInstrInfo(getTheAMDGPUTarget(), createR600MCInstrInfo);
 111   for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
 112     RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
 113
 114     TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
 115     TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
 116     TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
 117     TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
 118     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
 119   }
 120
 121   // R600 specific registration
 122   TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
 123                                         createR600MCCodeEmitter);
 124   TargetRegistry::RegisterObjectTargetStreamer(
 125       getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
 126
 127   // GCN specific registration
 128   TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
 129                                         createSIMCCodeEmitter);
 130
 131   TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
 132                                             createAMDGPUAsmTargetStreamer);
 133   TargetRegistry::RegisterObjectTargetStreamer(
 134       getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
 135 }