contrib/llvm/lib/Target/AMDGPU/MIMGInstructions.td

   1 //===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 class MIMG_Mask <string op, int channels> {
  11   string Op = op;
  12   int Channels = channels;
  13 }
  14
  15 class mimg <bits<7> si, bits<7> vi = si> {
  16   field bits<7> SI = si;
  17   field bits<7> VI = vi;
  18 }
  19
  20 class MIMG_Helper <dag outs, dag ins, string asm,
  21                    string dns=""> : MIMG<outs, ins, asm,[]> {
  22   let mayLoad = 1;
  23   let mayStore = 0;
  24   let hasPostISelHook = 1;
  25   let DecoderNamespace = dns;
  26   let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
  27   let AsmMatchConverter = "cvtMIMG";
  28   let usesCustomInserter = 1;
  29 }
  30
  31 class MIMG_NoSampler_Helper <bits<7> op, string asm,
  32                              RegisterClass dst_rc,
  33                              RegisterClass addr_rc,
  34                              string dns=""> : MIMG_Helper <
  35   (outs dst_rc:$vdata),
  36   (ins addr_rc:$vaddr, SReg_256:$srsrc,
  37        dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
  38        r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
  39   asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da",
  40   dns>, MIMGe<op> {
  41   let ssamp = 0;
  42 }
  43
  44 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
  45                                       RegisterClass dst_rc,
  46                                       int channels> {
  47   def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
  48                                    !if(!eq(channels, 1), "AMDGPU", "")>,
  49             MIMG_Mask<asm#"_V1", channels>;
  50   def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
  51             MIMG_Mask<asm#"_V2", channels>;
  52   def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
  53             MIMG_Mask<asm#"_V4", channels>;
  54 }
  55
  56 multiclass MIMG_NoSampler <bits<7> op, string asm> {
  57   defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
  58   defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
  59   defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
  60   defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
  61 }
  62
  63 class MIMG_Store_Helper <bits<7> op, string asm,
  64                          RegisterClass data_rc,
  65                          RegisterClass addr_rc> : MIMG_Helper <
  66   (outs),
  67   (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
  68        dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
  69        r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
  70   asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
  71      >, MIMGe<op> {
  72   let ssamp = 0;
  73   let mayLoad = 1; // TableGen requires this for matching with the intrinsics
  74   let mayStore = 1;
  75   let hasSideEffects = 1;
  76   let hasPostISelHook = 0;
  77   let DisableWQM = 1;
  78 }
  79
  80 multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm,
  81                                   RegisterClass data_rc,
  82                                   int channels> {
  83   def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32>,
  84             MIMG_Mask<asm#"_V1", channels>;
  85   def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>,
  86             MIMG_Mask<asm#"_V2", channels>;
  87   def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>,
  88             MIMG_Mask<asm#"_V4", channels>;
  89 }
  90
  91 multiclass MIMG_Store <bits<7> op, string asm> {
  92   defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>;
  93   defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 2>;
  94   defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 3>;
  95   defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 4>;
  96 }
  97
  98 class MIMG_Atomic_Helper <string asm, RegisterClass data_rc,
  99                           RegisterClass addr_rc> : MIMG_Helper <
 100     (outs data_rc:$vdst),
 101     (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
 102          dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
 103          r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
 104     asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
 105   > {
 106   let mayStore = 1;
 107   let hasSideEffects = 1;
 108   let hasPostISelHook = 0;
 109   let DisableWQM = 1;
 110   let Constraints = "$vdst = $vdata";
 111   let AsmMatchConverter = "cvtMIMGAtomic";
 112 }
 113
 114 class MIMG_Atomic_Real_si<mimg op, string name, string asm,
 115   RegisterClass data_rc, RegisterClass addr_rc> :
 116   MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
 117   SIMCInstr<name, SIEncodingFamily.SI>,
 118   MIMGe<op.SI> {
 119   let isCodeGenOnly = 0;
 120   let AssemblerPredicates = [isSICI];
 121   let DecoderNamespace = "SICI";
 122   let DisableDecoder = DisableSIDecoder;
 123 }
 124
 125 class MIMG_Atomic_Real_vi<mimg op, string name, string asm,
 126   RegisterClass data_rc, RegisterClass addr_rc> :
 127   MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
 128   SIMCInstr<name, SIEncodingFamily.VI>,
 129   MIMGe<op.VI> {
 130   let isCodeGenOnly = 0;
 131   let AssemblerPredicates = [isVI];
 132   let DecoderNamespace = "VI";
 133   let DisableDecoder = DisableVIDecoder;
 134 }
 135
 136 multiclass MIMG_Atomic_Helper_m <mimg op, string name, string asm,
 137                                  RegisterClass data_rc, RegisterClass addr_rc> {
 138   let isPseudo = 1, isCodeGenOnly = 1 in {
 139     def "" : MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
 140              SIMCInstr<name, SIEncodingFamily.NONE>;
 141   }
 142
 143   let ssamp = 0 in {
 144     def _si : MIMG_Atomic_Real_si<op, name, asm, data_rc, addr_rc>;
 145
 146     def _vi : MIMG_Atomic_Real_vi<op, name, asm, data_rc, addr_rc>;
 147   }
 148 }
 149
 150 multiclass MIMG_Atomic <mimg op, string asm, RegisterClass data_rc = VGPR_32> {
 151   defm _V1 : MIMG_Atomic_Helper_m <op, asm # "_V1", asm, data_rc, VGPR_32>;
 152   defm _V2 : MIMG_Atomic_Helper_m <op, asm # "_V2", asm, data_rc, VReg_64>;
 153   defm _V4 : MIMG_Atomic_Helper_m <op, asm # "_V3", asm, data_rc, VReg_128>;
 154 }
 155
 156 class MIMG_Sampler_Helper <bits<7> op, string asm,
 157                            RegisterClass dst_rc,
 158                            RegisterClass src_rc,
 159                            bit wqm,
 160                            string dns=""> : MIMG_Helper <
 161   (outs dst_rc:$vdata),
 162   (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
 163        dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
 164        r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
 165   asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da",
 166   dns>, MIMGe<op> {
 167   let WQM = wqm;
 168 }
 169
 170 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
 171                                     RegisterClass dst_rc,
 172                                     int channels, bit wqm> {
 173   def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm,
 174                                  !if(!eq(channels, 1), "AMDGPU", "")>,
 175             MIMG_Mask<asm#"_V1", channels>;
 176   def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
 177             MIMG_Mask<asm#"_V2", channels>;
 178   def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
 179             MIMG_Mask<asm#"_V4", channels>;
 180   def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
 181             MIMG_Mask<asm#"_V8", channels>;
 182   def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
 183             MIMG_Mask<asm#"_V16", channels>;
 184 }
 185
 186 multiclass MIMG_Sampler <bits<7> op, string asm, bit wqm=0> {
 187   defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;
 188   defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>;
 189   defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>;
 190   defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, wqm>;
 191 }
 192
 193 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op, asm, 1>;
 194
 195 class MIMG_Gather_Helper <bits<7> op, string asm,
 196                           RegisterClass dst_rc,
 197                           RegisterClass src_rc, bit wqm> : MIMG <
 198   (outs dst_rc:$vdata),
 199   (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
 200        dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
 201        r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
 202   asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da",
 203   []>, MIMGe<op> {
 204   let mayLoad = 1;
 205   let mayStore = 0;
 206
 207   // DMASK was repurposed for GATHER4. 4 components are always
 208   // returned and DMASK works like a swizzle - it selects
 209   // the component to fetch. The only useful DMASK values are
 210   // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
 211   // (red,red,red,red) etc.) The ISA document doesn't mention
 212   // this.
 213   // Therefore, disable all code which updates DMASK by setting this:
 214   let Gather4 = 1;
 215   let hasPostISelHook = 0;
 216   let WQM = wqm;
 217
 218   let isAsmParserOnly = 1; // TBD: fix it later
 219 }
 220
 221 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
 222                                     RegisterClass dst_rc,
 223                                     int channels, bit wqm> {
 224   def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
 225             MIMG_Mask<asm#"_V1", channels>;
 226   def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
 227             MIMG_Mask<asm#"_V2", channels>;
 228   def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
 229             MIMG_Mask<asm#"_V4", channels>;
 230   def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
 231             MIMG_Mask<asm#"_V8", channels>;
 232   def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
 233             MIMG_Mask<asm#"_V16", channels>;
 234 }
 235
 236 multiclass MIMG_Gather <bits<7> op, string asm, bit wqm=0> {
 237   defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>;
 238   defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>;
 239   defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>;
 240   defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, wqm>;
 241 }
 242
 243 multiclass MIMG_Gather_WQM <bits<7> op, string asm> : MIMG_Gather<op, asm, 1>;
 244
 245 //===----------------------------------------------------------------------===//
 246 // MIMG Instructions
 247 //===----------------------------------------------------------------------===//
 248 let SubtargetPredicate = isGCN in {
 249 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
 250 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
 251 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
 252 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
 253 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
 254 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
 255 defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">;
 256 defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">;
 257 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
 258 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
 259 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
 260 defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">;
 261 defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", VReg_64>;
 262 defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">;
 263 defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">;
 264 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI
 265 defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">;
 266 defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">;
 267 defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">;
 268 defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">;
 269 defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">;
 270 defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">;
 271 defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">;
 272 defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">;
 273 defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">;
 274 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; -- not on VI
 275 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI
 276 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI
 277 defm IMAGE_SAMPLE           : MIMG_Sampler_WQM <0x00000020, "image_sample">;
 278 defm IMAGE_SAMPLE_CL        : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">;
 279 defm IMAGE_SAMPLE_D         : MIMG_Sampler <0x00000022, "image_sample_d">;
 280 defm IMAGE_SAMPLE_D_CL      : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
 281 defm IMAGE_SAMPLE_L         : MIMG_Sampler <0x00000024, "image_sample_l">;
 282 defm IMAGE_SAMPLE_B         : MIMG_Sampler_WQM <0x00000025, "image_sample_b">;
 283 defm IMAGE_SAMPLE_B_CL      : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">;
 284 defm IMAGE_SAMPLE_LZ        : MIMG_Sampler <0x00000027, "image_sample_lz">;
 285 defm IMAGE_SAMPLE_C         : MIMG_Sampler_WQM <0x00000028, "image_sample_c">;
 286 defm IMAGE_SAMPLE_C_CL      : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">;
 287 defm IMAGE_SAMPLE_C_D       : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
 288 defm IMAGE_SAMPLE_C_D_CL    : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
 289 defm IMAGE_SAMPLE_C_L       : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
 290 defm IMAGE_SAMPLE_C_B       : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">;
 291 defm IMAGE_SAMPLE_C_B_CL    : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">;
 292 defm IMAGE_SAMPLE_C_LZ      : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
 293 defm IMAGE_SAMPLE_O         : MIMG_Sampler_WQM <0x00000030, "image_sample_o">;
 294 defm IMAGE_SAMPLE_CL_O      : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">;
 295 defm IMAGE_SAMPLE_D_O       : MIMG_Sampler <0x00000032, "image_sample_d_o">;
 296 defm IMAGE_SAMPLE_D_CL_O    : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
 297 defm IMAGE_SAMPLE_L_O       : MIMG_Sampler <0x00000034, "image_sample_l_o">;
 298 defm IMAGE_SAMPLE_B_O       : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">;
 299 defm IMAGE_SAMPLE_B_CL_O    : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">;
 300 defm IMAGE_SAMPLE_LZ_O      : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
 301 defm IMAGE_SAMPLE_C_O       : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">;
 302 defm IMAGE_SAMPLE_C_CL_O    : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">;
 303 defm IMAGE_SAMPLE_C_D_O     : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
 304 defm IMAGE_SAMPLE_C_D_CL_O  : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
 305 defm IMAGE_SAMPLE_C_L_O     : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
 306 defm IMAGE_SAMPLE_C_B_O     : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">;
 307 defm IMAGE_SAMPLE_C_B_CL_O  : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">;
 308 defm IMAGE_SAMPLE_C_LZ_O    : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
 309 defm IMAGE_GATHER4          : MIMG_Gather_WQM <0x00000040, "image_gather4">;
 310 defm IMAGE_GATHER4_CL       : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">;
 311 defm IMAGE_GATHER4_L        : MIMG_Gather <0x00000044, "image_gather4_l">;
 312 defm IMAGE_GATHER4_B        : MIMG_Gather_WQM <0x00000045, "image_gather4_b">;
 313 defm IMAGE_GATHER4_B_CL     : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">;
 314 defm IMAGE_GATHER4_LZ       : MIMG_Gather <0x00000047, "image_gather4_lz">;
 315 defm IMAGE_GATHER4_C        : MIMG_Gather_WQM <0x00000048, "image_gather4_c">;
 316 defm IMAGE_GATHER4_C_CL     : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">;
 317 defm IMAGE_GATHER4_C_L      : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
 318 defm IMAGE_GATHER4_C_B      : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">;
 319 defm IMAGE_GATHER4_C_B_CL   : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">;
 320 defm IMAGE_GATHER4_C_LZ     : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
 321 defm IMAGE_GATHER4_O        : MIMG_Gather_WQM <0x00000050, "image_gather4_o">;
 322 defm IMAGE_GATHER4_CL_O     : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">;
 323 defm IMAGE_GATHER4_L_O      : MIMG_Gather <0x00000054, "image_gather4_l_o">;
 324 defm IMAGE_GATHER4_B_O      : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">;
 325 defm IMAGE_GATHER4_B_CL_O   : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
 326 defm IMAGE_GATHER4_LZ_O     : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
 327 defm IMAGE_GATHER4_C_O      : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">;
 328 defm IMAGE_GATHER4_C_CL_O   : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">;
 329 defm IMAGE_GATHER4_C_L_O    : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
 330 defm IMAGE_GATHER4_C_B_O    : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">;
 331 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">;
 332 defm IMAGE_GATHER4_C_LZ_O   : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
 333 defm IMAGE_GET_LOD          : MIMG_Sampler_WQM <0x00000060, "image_get_lod">;
 334 defm IMAGE_SAMPLE_CD        : MIMG_Sampler <0x00000068, "image_sample_cd">;
 335 defm IMAGE_SAMPLE_CD_CL     : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
 336 defm IMAGE_SAMPLE_C_CD      : MIMG_Sampler <0x0000006a, "image_sample_c_cd">;
 337 defm IMAGE_SAMPLE_C_CD_CL   : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">;
 338 defm IMAGE_SAMPLE_CD_O      : MIMG_Sampler <0x0000006c, "image_sample_cd_o">;
 339 defm IMAGE_SAMPLE_CD_CL_O   : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">;
 340 defm IMAGE_SAMPLE_C_CD_O    : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">;
 341 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">;
 342 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
 343 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
 344 }
 345
 346 /********** ======================= **********/
 347 /********** Image sampling patterns **********/
 348 /********** ======================= **********/
 349
 350 // Image + sampler
 351 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
 352   (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
 353         i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
 354   (opcode $addr, $rsrc, $sampler,
 355           (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
 356           (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
 357 >;
 358
 359 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
 360   def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
 361   def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
 362   def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
 363   def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
 364   def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
 365 }
 366
 367 // Image + sampler for amdgcn
 368 // TODO:
 369 // 1. Handle half data type like v4f16, and add D16 bit support;
 370 // 2. Handle v4i32 rsrc type (Register Class for the instruction to be SReg_128).
 371 // 3. Add A16 support when we pass address of half type.
 372 multiclass AMDGCNSamplePattern<SDPatternOperator name, MIMG opcode, ValueType dt, ValueType vt>  {
 373   def : Pat<
 374     (dt (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i1:$unorm, i1:$glc,
 375         i1:$slc, i1:$lwe, i1:$da)),
 376     (opcode $addr, $rsrc, $sampler,
 377           (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
 378           0, 0, (as_i1imm $lwe), (as_i1imm $da))
 379     >;
 380 }
 381
 382 multiclass AMDGCNSampleDataPatterns<SDPatternOperator name, string opcode, ValueType dt> {
 383   defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V1), dt, f32>;
 384   defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V2), dt, v2f32>;
 385   defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V4), dt, v4f32>;
 386   defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V8), dt, v8f32>;
 387   defm : AMDGCNSamplePattern<name, !cast<MIMG>(opcode # _V16), dt, v16f32>;
 388 }
 389
 390 // TODO: support v3f32.
 391 multiclass AMDGCNSamplePatterns<SDPatternOperator name, string opcode> {
 392   defm : AMDGCNSampleDataPatterns<name, !cast<string>(opcode # _V1), f32>;
 393   defm : AMDGCNSampleDataPatterns<name, !cast<string>(opcode # _V2), v2f32>;
 394   defm : AMDGCNSampleDataPatterns<name, !cast<string>(opcode # _V4), v4f32>;
 395 }
 396
 397 // Image only
 398 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
 399   (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm,
 400         imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe),
 401   (opcode $addr, $rsrc,
 402           (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
 403           (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
 404 >;
 405
 406 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
 407   def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
 408   def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
 409   def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
 410 }
 411
 412 multiclass ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType dt, ValueType vt> {
 413   def : Pat <
 414     (dt (name vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc, i1:$lwe,
 415                 i1:$da)),
 416     (opcode $addr, $rsrc,
 417           (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
 418           0, 0, (as_i1imm $lwe), (as_i1imm $da))
 419   >;
 420 }
 421
 422 multiclass ImageLoadDataPatterns<SDPatternOperator name, string opcode, ValueType dt> {
 423   defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V1), dt, i32>;
 424   defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V2), dt, v2i32>;
 425   defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4), dt, v4i32>;
 426 }
 427
 428 // TODO: support v3f32.
 429 multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> {
 430   defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V1), f32>;
 431   defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V2), v2f32>;
 432   defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V4), v4f32>;
 433 }
 434
 435 multiclass ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType dt, ValueType vt> {
 436   def : Pat <
 437     (name dt:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc,
 438           i1:$lwe, i1:$da),
 439     (opcode $data, $addr, $rsrc,
 440           (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
 441           0, 0, (as_i1imm $lwe), (as_i1imm $da))
 442   >;
 443 }
 444
 445 multiclass ImageStoreDataPatterns<SDPatternOperator name, string opcode, ValueType dt> {
 446   defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V1), dt, i32>;
 447   defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V2), dt, v2i32>;
 448   defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V4), dt, v4i32>;
 449 }
 450
 451 // TODO: support v3f32.
 452 multiclass ImageStorePatterns<SDPatternOperator name, string opcode> {
 453   defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V1), f32>;
 454   defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V2), v2f32>;
 455   defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V4), v4f32>;
 456 }
 457
 458 class ImageAtomicPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
 459   (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc),
 460   (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da))
 461 >;
 462
 463 multiclass ImageAtomicPatterns<SDPatternOperator name, string opcode> {
 464   def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V1), i32>;
 465   def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V2), v2i32>;
 466   def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V4), v4i32>;
 467 }
 468
 469 class ImageAtomicCmpSwapPattern<MIMG opcode, ValueType vt> : Pat <
 470   (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc,
 471                                    imm:$r128, imm:$da, imm:$slc),
 472   (EXTRACT_SUBREG
 473     (opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1),
 474             $addr, $rsrc, 3, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)),
 475     sub0)
 476 >;
 477
 478 // ======= amdgcn Image Intrinsics ==============
 479
 480 // Image load
 481 defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">;
 482 defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">;
 483 defm : ImageLoadPatterns<int_amdgcn_image_getresinfo, "IMAGE_GET_RESINFO">;
 484
 485 // Image store
 486 defm : ImageStorePatterns<int_amdgcn_image_store, "IMAGE_STORE">;
 487 defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">;
 488
 489 // Basic sample
 490 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample,           "IMAGE_SAMPLE">;
 491 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl,        "IMAGE_SAMPLE_CL">;
 492 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d,         "IMAGE_SAMPLE_D">;
 493 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl,      "IMAGE_SAMPLE_D_CL">;
 494 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l,         "IMAGE_SAMPLE_L">;
 495 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b,         "IMAGE_SAMPLE_B">;
 496 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl,      "IMAGE_SAMPLE_B_CL">;
 497 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz,        "IMAGE_SAMPLE_LZ">;
 498 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd,        "IMAGE_SAMPLE_CD">;
 499 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl,     "IMAGE_SAMPLE_CD_CL">;
 500
 501 // Sample with comparison
 502 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c,         "IMAGE_SAMPLE_C">;
 503 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl,      "IMAGE_SAMPLE_C_CL">;
 504 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d,       "IMAGE_SAMPLE_C_D">;
 505 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl,    "IMAGE_SAMPLE_C_D_CL">;
 506 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l,       "IMAGE_SAMPLE_C_L">;
 507 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b,       "IMAGE_SAMPLE_C_B">;
 508 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl,    "IMAGE_SAMPLE_C_B_CL">;
 509 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz,      "IMAGE_SAMPLE_C_LZ">;
 510 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd,      "IMAGE_SAMPLE_C_CD">;
 511 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl,   "IMAGE_SAMPLE_C_CD_CL">;
 512
 513 // Sample with offsets
 514 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_o,         "IMAGE_SAMPLE_O">;
 515 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cl_o,      "IMAGE_SAMPLE_CL_O">;
 516 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_o,       "IMAGE_SAMPLE_D_O">;
 517 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_d_cl_o,    "IMAGE_SAMPLE_D_CL_O">;
 518 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_l_o,       "IMAGE_SAMPLE_L_O">;
 519 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_o,       "IMAGE_SAMPLE_B_O">;
 520 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_b_cl_o,    "IMAGE_SAMPLE_B_CL_O">;
 521 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_lz_o,      "IMAGE_SAMPLE_LZ_O">;
 522 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_o,      "IMAGE_SAMPLE_CD_O">;
 523 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_cd_cl_o,   "IMAGE_SAMPLE_CD_CL_O">;
 524
 525 // Sample with comparison and offsets
 526 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_o,       "IMAGE_SAMPLE_C_O">;
 527 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cl_o,    "IMAGE_SAMPLE_C_CL_O">;
 528 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_o,     "IMAGE_SAMPLE_C_D_O">;
 529 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_d_cl_o,  "IMAGE_SAMPLE_C_D_CL_O">;
 530 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_l_o,     "IMAGE_SAMPLE_C_L_O">;
 531 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_o,     "IMAGE_SAMPLE_C_B_O">;
 532 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_b_cl_o,  "IMAGE_SAMPLE_C_B_CL_O">;
 533 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_lz_o,    "IMAGE_SAMPLE_C_LZ_O">;
 534 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_o,    "IMAGE_SAMPLE_C_CD_O">;
 535 defm : AMDGCNSamplePatterns<int_amdgcn_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
 536
 537 // Gather opcodes
 538 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4,           "IMAGE_GATHER4">;
 539 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_cl,        "IMAGE_GATHER4_CL">;
 540 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_l,         "IMAGE_GATHER4_L">;
 541 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_b,         "IMAGE_GATHER4_B">;
 542 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_b_cl,      "IMAGE_GATHER4_B_CL">;
 543 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_lz,        "IMAGE_GATHER4_LZ">;
 544
 545 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c,         "IMAGE_GATHER4_C">;
 546 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_cl,      "IMAGE_GATHER4_C_CL">;
 547 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_l,       "IMAGE_GATHER4_C_L">;
 548 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_b,       "IMAGE_GATHER4_C_B">;
 549 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_b_cl,    "IMAGE_GATHER4_C_B_CL">;
 550 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_lz,      "IMAGE_GATHER4_C_LZ">;
 551
 552 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_o,         "IMAGE_GATHER4_O">;
 553 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_cl_o,      "IMAGE_GATHER4_CL_O">;
 554 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_l_o,       "IMAGE_GATHER4_L_O">;
 555 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_b_o,       "IMAGE_GATHER4_B_O">;
 556 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_b_cl_o,    "IMAGE_GATHER4_B_CL_O">;
 557 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_lz_o,      "IMAGE_GATHER4_LZ_O">;
 558
 559 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_o,       "IMAGE_GATHER4_C_O">;
 560 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_cl_o,    "IMAGE_GATHER4_C_CL_O">;
 561 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_l_o,     "IMAGE_GATHER4_C_L_O">;
 562 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_b_o,     "IMAGE_GATHER4_C_B_O">;
 563 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_b_cl_o,  "IMAGE_GATHER4_C_B_CL_O">;
 564 defm : AMDGCNSamplePatterns<int_amdgcn_image_gather4_c_lz_o,    "IMAGE_GATHER4_C_LZ_O">;
 565
 566 defm : AMDGCNSamplePatterns<int_amdgcn_image_getlod, "IMAGE_GET_LOD">;
 567
 568 // Image atomics
 569 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_swap, "IMAGE_ATOMIC_SWAP">;
 570 def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V1, i32>;
 571 def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V2, v2i32>;
 572 def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V4, v4i32>;
 573 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_add, "IMAGE_ATOMIC_ADD">;
 574 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_sub, "IMAGE_ATOMIC_SUB">;
 575 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smin, "IMAGE_ATOMIC_SMIN">;
 576 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umin, "IMAGE_ATOMIC_UMIN">;
 577 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smax, "IMAGE_ATOMIC_SMAX">;
 578 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umax, "IMAGE_ATOMIC_UMAX">;
 579 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_and, "IMAGE_ATOMIC_AND">;
 580 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_or, "IMAGE_ATOMIC_OR">;
 581 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_xor, "IMAGE_ATOMIC_XOR">;
 582 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_inc, "IMAGE_ATOMIC_INC">;
 583 defm : ImageAtomicPatterns<int_amdgcn_image_atomic_dec, "IMAGE_ATOMIC_DEC">;
 584
 585 /* SIsample for simple 1D texture lookup */
 586 def : Pat <
 587   (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
 588   (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
 589 >;
 590
 591 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
 592     (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
 593     (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
 594 >;
 595
 596 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
 597     (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT),
 598     (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0)
 599 >;
 600
 601 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
 602     (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY),
 603     (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
 604 >;
 605
 606 class SampleShadowPattern<SDNode name, MIMG opcode,
 607                           ValueType vt> : Pat <
 608     (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW),
 609     (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
 610 >;
 611
 612 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
 613                                ValueType vt> : Pat <
 614     (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
 615     (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
 616 >;
 617
 618 /* SIsample* for texture lookups consuming more address parameters */
 619 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
 620                           MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
 621 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
 622   def : SamplePattern <SIsample, sample, addr_type>;
 623   def : SampleRectPattern <SIsample, sample, addr_type>;
 624   def : SampleArrayPattern <SIsample, sample, addr_type>;
 625   def : SampleShadowPattern <SIsample, sample_c, addr_type>;
 626   def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
 627
 628   def : SamplePattern <SIsamplel, sample_l, addr_type>;
 629   def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
 630   def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
 631   def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
 632
 633   def : SamplePattern <SIsampleb, sample_b, addr_type>;
 634   def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
 635   def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
 636   def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
 637
 638   def : SamplePattern <SIsampled, sample_d, addr_type>;
 639   def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
 640   def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
 641   def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
 642 }
 643
 644 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
 645                       IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
 646                       IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
 647                       IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
 648                       v2i32>;
 649 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
 650                       IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
 651                       IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
 652                       IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
 653                       v4i32>;
 654 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
 655                       IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
 656                       IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
 657                       IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
 658                       v8i32>;
 659 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
 660                       IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
 661                       IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
 662                       IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
 663                       v16i32>;