contrib/llvm/lib/Target/AMDGPU/Processors.td

   1 //===-- Processors.td - R600 Processor definitions ------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
  11 : Processor<Name, itin, Features>;
  12
  13 //===----------------------------------------------------------------------===//
  14 // R600
  15 //===----------------------------------------------------------------------===//
  16 def : Proc<"r600",       R600_VLIW5_Itin,
  17     [FeatureR600, FeatureVertexCache, FeatureWavefrontSize64]>;
  18
  19 def : Proc<"r630",       R600_VLIW5_Itin,
  20     [FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;
  21
  22 def : Proc<"rs880",      R600_VLIW5_Itin,
  23     [FeatureR600, FeatureWavefrontSize16]>;
  24
  25 def : Proc<"rv670",      R600_VLIW5_Itin,
  26     [FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // R700
  30 //===----------------------------------------------------------------------===//
  31
  32 def : Proc<"rv710",      R600_VLIW5_Itin,
  33     [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
  34
  35 def : Proc<"rv730",      R600_VLIW5_Itin,
  36     [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
  37
  38 def : Proc<"rv770",      R600_VLIW5_Itin,
  39     [FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
  40
  41 //===----------------------------------------------------------------------===//
  42 // Evergreen
  43 //===----------------------------------------------------------------------===//
  44
  45 def : Proc<"cedar",      R600_VLIW5_Itin,
  46     [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32,
  47      FeatureCFALUBug]>;
  48
  49 def : Proc<"redwood",    R600_VLIW5_Itin,
  50     [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64,
  51      FeatureCFALUBug]>;
  52
  53 def : Proc<"sumo",       R600_VLIW5_Itin,
  54     [FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]>;
  55
  56 def : Proc<"juniper",    R600_VLIW5_Itin,
  57     [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
  58
  59 def : Proc<"cypress",    R600_VLIW5_Itin,
  60     [FeatureEvergreen, FeatureFP64, FeatureVertexCache,
  61      FeatureWavefrontSize64]>;
  62
  63 //===----------------------------------------------------------------------===//
  64 // Northern Islands
  65 //===----------------------------------------------------------------------===//
  66
  67 def : Proc<"barts",      R600_VLIW5_Itin,
  68     [FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
  69
  70 def : Proc<"turks",      R600_VLIW5_Itin,
  71     [FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
  72
  73 def : Proc<"caicos",     R600_VLIW5_Itin,
  74     [FeatureNorthernIslands, FeatureCFALUBug]>;
  75
  76 def : Proc<"cayman",     R600_VLIW4_Itin,
  77     [FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
  78
  79 //===----------------------------------------------------------------------===//
  80 // Southern Islands
  81 //===----------------------------------------------------------------------===//
  82
  83 def : ProcessorModel<"gfx600",     SIFullSpeedModel,
  84   [FeatureISAVersion6_0_0]>;
  85
  86 def : ProcessorModel<"SI",         SIFullSpeedModel,
  87   [FeatureISAVersion6_0_0]
  88 >;
  89
  90 def : ProcessorModel<"tahiti",     SIFullSpeedModel,
  91   [FeatureISAVersion6_0_0]
  92 >;
  93
  94 def : ProcessorModel<"gfx601",     SIQuarterSpeedModel,
  95   [FeatureISAVersion6_0_1]
  96 >;
  97
  98 def : ProcessorModel<"pitcairn",   SIQuarterSpeedModel,
  99   [FeatureISAVersion6_0_1]>;
 100
 101 def : ProcessorModel<"verde",      SIQuarterSpeedModel,
 102   [FeatureISAVersion6_0_1]>;
 103
 104 def : ProcessorModel<"oland",      SIQuarterSpeedModel,
 105   [FeatureISAVersion6_0_1]>;
 106
 107 def : ProcessorModel<"hainan",     SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;
 108
 109 //===----------------------------------------------------------------------===//
 110 // Sea Islands
 111 //===----------------------------------------------------------------------===//
 112
 113 def : ProcessorModel<"gfx700",     SIQuarterSpeedModel,
 114   [FeatureISAVersion7_0_0]
 115 >;
 116
 117 def : ProcessorModel<"bonaire",    SIQuarterSpeedModel,
 118   [FeatureISAVersion7_0_0]
 119 >;
 120
 121 def : ProcessorModel<"kaveri",     SIQuarterSpeedModel,
 122   [FeatureISAVersion7_0_0]
 123 >;
 124
 125 def : ProcessorModel<"gfx701",     SIFullSpeedModel,
 126   [FeatureISAVersion7_0_1]
 127 >;
 128
 129 def : ProcessorModel<"hawaii",     SIFullSpeedModel,
 130   [FeatureISAVersion7_0_1]
 131 >;
 132
 133 def : ProcessorModel<"gfx702",     SIQuarterSpeedModel,
 134   [FeatureISAVersion7_0_2]
 135 >;
 136
 137 def : ProcessorModel<"gfx703",     SIQuarterSpeedModel,
 138   [FeatureISAVersion7_0_3]
 139 >;
 140
 141 def : ProcessorModel<"kabini",     SIQuarterSpeedModel,
 142   [FeatureISAVersion7_0_3]
 143 >;
 144
 145 def : ProcessorModel<"mullins",    SIQuarterSpeedModel,
 146   [FeatureISAVersion7_0_3]>;
 147
 148 //===----------------------------------------------------------------------===//
 149 // Volcanic Islands
 150 //===----------------------------------------------------------------------===//
 151
 152 def : ProcessorModel<"tonga",   SIQuarterSpeedModel,
 153   [FeatureISAVersion8_0_2]
 154 >;
 155
 156 def : ProcessorModel<"iceland", SIQuarterSpeedModel,
 157   [FeatureISAVersion8_0_0]
 158 >;
 159
 160 def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
 161   [FeatureISAVersion8_0_1]
 162 >;
 163
 164 def : ProcessorModel<"fiji",    SIQuarterSpeedModel,
 165   [FeatureISAVersion8_0_3]
 166 >;
 167
 168 def : ProcessorModel<"stoney",  SIQuarterSpeedModel,
 169   [FeatureISAVersion8_1_0]
 170 >;
 171
 172 def : ProcessorModel<"polaris10", SIQuarterSpeedModel,
 173   [FeatureISAVersion8_0_3]
 174 >;
 175
 176 def : ProcessorModel<"polaris11", SIQuarterSpeedModel,
 177   [FeatureISAVersion8_0_3]
 178 >;
 179
 180 def : ProcessorModel<"gfx800", SIQuarterSpeedModel,
 181   [FeatureISAVersion8_0_0]
 182 >;
 183
 184 def : ProcessorModel<"gfx801", SIQuarterSpeedModel,
 185   [FeatureISAVersion8_0_1]
 186 >;
 187
 188 def : ProcessorModel<"gfx802", SIQuarterSpeedModel,
 189   [FeatureISAVersion8_0_2]
 190 >;
 191
 192 def : ProcessorModel<"gfx803", SIQuarterSpeedModel,
 193   [FeatureISAVersion8_0_3]
 194 >;
 195
 196 def : ProcessorModel<"gfx804", SIQuarterSpeedModel,
 197   [FeatureISAVersion8_0_4]
 198 >;
 199
 200 def : ProcessorModel<"gfx810", SIQuarterSpeedModel,
 201   [FeatureISAVersion8_1_0]
 202 >;
 203
 204 //===----------------------------------------------------------------------===//
 205 // GFX9
 206 //===----------------------------------------------------------------------===//
 207
 208 def : ProcessorModel<"gfx900", SIQuarterSpeedModel,
 209   [FeatureISAVersion9_0_0]
 210 >;
 211
 212 def : ProcessorModel<"gfx901", SIQuarterSpeedModel,
 213   [FeatureISAVersion9_0_1]
 214 >;
 215
 216 def : ProcessorModel<"gfx902", SIQuarterSpeedModel,
 217   [FeatureISAVersion9_0_2]
 218 >;
 219
 220 def : ProcessorModel<"gfx903", SIQuarterSpeedModel,
 221   [FeatureISAVersion9_0_3]
 222 >;
 223