1 //===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
12 /// group to work correctly. This pass expands these individual instructions
13 /// into several instructions that will completely fill the instruction group.
15 //===----------------------------------------------------------------------===//
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "R600RegisterInfo.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
34 const R600InstrInfo *TII;
36 void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
40 R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID),
43 bool runOnMachineFunction(MachineFunction &MF) override;
45 StringRef getPassName() const override {
46 return "R600 Expand special instructions pass";
50 } // End anonymous namespace
52 char R600ExpandSpecialInstrsPass::ID = 0;
54 FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
55 return new R600ExpandSpecialInstrsPass();
58 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
59 const MachineInstr *OldMI, unsigned Op) {
60 int OpIdx = TII->getOperandIdx(*OldMI, Op);
62 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
63 TII->setImmOperand(*NewMI, Op, Val);
67 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
68 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
69 TII = ST.getInstrInfo();
71 const R600RegisterInfo &TRI = TII->getRegisterInfo();
73 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
75 MachineBasicBlock &MBB = *BB;
76 MachineBasicBlock::iterator I = MBB.begin();
77 while (I != MBB.end()) {
78 MachineInstr &MI = *I;
81 // Expand LDS_*_RET instructions
82 if (TII->isLDSRetInstr(MI.getOpcode())) {
83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
85 MachineOperand &DstOp = MI.getOperand(DstIdx);
86 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
87 DstOp.getReg(), AMDGPU::OQAP);
88 DstOp.setReg(AMDGPU::OQAP);
89 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
90 AMDGPU::OpName::pred_sel);
91 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
92 AMDGPU::OpName::pred_sel);
93 // Copy the pred_sel bit
94 Mov->getOperand(MovPredSelIdx).setReg(
95 MI.getOperand(LDSPredSelIdx).getReg());
98 switch (MI.getOpcode()) {
100 // Expand PRED_X to one of the PRED_SET instructions.
101 case AMDGPU::PRED_X: {
102 uint64_t Flags = MI.getOperand(3).getImm();
103 // The native opcode used by PRED_X is stored as an immediate in the
105 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
106 MI.getOperand(2).getImm(), // opcode
107 MI.getOperand(0).getReg(), // dst
108 MI.getOperand(1).getReg(), // src0
109 AMDGPU::ZERO); // src1
110 TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
111 if (Flags & MO_FLAG_PUSH) {
112 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1);
114 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1);
116 MI.eraseFromParent();
119 case AMDGPU::DOT_4: {
121 const R600RegisterInfo &TRI = TII->getRegisterInfo();
123 unsigned DstReg = MI.getOperand(0).getReg();
124 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
126 for (unsigned Chan = 0; Chan < 4; ++Chan) {
127 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
129 AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
131 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
133 BMI->bundleWithPred();
136 TII->addFlag(*BMI, 0, MO_FLAG_MASK);
139 TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
140 unsigned Opcode = BMI->getOpcode();
141 // While not strictly necessary from hw point of view, we force
142 // all src operands of a dot4 inst to belong to the same slot.
143 unsigned Src0 = BMI->getOperand(
144 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
146 unsigned Src1 = BMI->getOperand(
147 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
151 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
152 (TRI.getEncodingValue(Src1) & 0xff) < 127)
153 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
155 MI.eraseFromParent();
160 bool IsReduction = TII->isReductionOp(MI.getOpcode());
161 bool IsVector = TII->isVector(MI);
162 bool IsCube = TII->isCubeOp(MI.getOpcode());
163 if (!IsReduction && !IsVector && !IsCube) {
167 // Expand the instruction
169 // Reduction instructions:
170 // T0_X = DP4 T1_XYZW, T2_XYZW
172 // TO_X = DP4 T1_X, T2_X
173 // TO_Y (write masked) = DP4 T1_Y, T2_Y
174 // TO_Z (write masked) = DP4 T1_Z, T2_Z
175 // TO_W (write masked) = DP4 T1_W, T2_W
177 // Vector instructions:
178 // T0_X = MULLO_INT T1_X, T2_X
180 // T0_X = MULLO_INT T1_X, T2_X
181 // T0_Y (write masked) = MULLO_INT T1_X, T2_X
182 // T0_Z (write masked) = MULLO_INT T1_X, T2_X
183 // T0_W (write masked) = MULLO_INT T1_X, T2_X
185 // Cube instructions:
186 // T0_XYZW = CUBE T1_XYZW
188 // TO_X = CUBE T1_Z, T1_Y
189 // T0_Y = CUBE T1_Z, T1_X
190 // T0_Z = CUBE T1_X, T1_Z
191 // T0_W = CUBE T1_Y, T1_Z
192 for (unsigned Chan = 0; Chan < 4; Chan++) {
193 unsigned DstReg = MI.getOperand(
194 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
195 unsigned Src0 = MI.getOperand(
196 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
199 // Determine the correct source registers
201 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
203 Src1 = MI.getOperand(Src1Idx).getReg();
207 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
208 Src0 = TRI.getSubReg(Src0, SubRegIndex);
209 Src1 = TRI.getSubReg(Src1, SubRegIndex);
211 static const int CubeSrcSwz[] = {2, 2, 0, 1};
212 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
213 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
214 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
215 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
218 // Determine the correct destination registers;
222 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
223 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
225 // Mask the write if the original instruction does not write to
226 // the current Channel.
227 Mask = (Chan != TRI.getHWRegChan(DstReg));
228 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
229 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
232 // Set the IsLast bit
233 NotLast = (Chan != 3 );
235 // Add the new instruction
236 unsigned Opcode = MI.getOpcode();
238 case AMDGPU::CUBE_r600_pseudo:
239 Opcode = AMDGPU::CUBE_r600_real;
241 case AMDGPU::CUBE_eg_pseudo:
242 Opcode = AMDGPU::CUBE_eg_real;
248 MachineInstr *NewMI =
249 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
252 NewMI->bundleWithPred();
254 TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
257 TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
259 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::clamp);
260 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::literal);
261 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_abs);
262 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_abs);
263 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg);
264 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg);
266 MI.eraseFromParent();