1 //===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
12 /// group to work correctly. This pass expands these individual instructions
13 /// into several instructions that will completely fill the instruction group.
15 //===----------------------------------------------------------------------===//
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/Pass.h"
35 #define DEBUG_TYPE "r600-expand-special-instrs"
39 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
41 const R600InstrInfo *TII = nullptr;
43 void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
49 R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID) {}
51 bool runOnMachineFunction(MachineFunction &MF) override;
53 StringRef getPassName() const override {
54 return "R600 Expand special instructions pass";
58 } // end anonymous namespace
60 INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
61 "R600 Expand Special Instrs", false, false)
62 INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
63 "R600ExpandSpecialInstrs", false, false)
65 char R600ExpandSpecialInstrsPass::ID = 0;
67 char &llvm::R600ExpandSpecialInstrsPassID = R600ExpandSpecialInstrsPass::ID;
69 FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
70 return new R600ExpandSpecialInstrsPass();
73 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
74 const MachineInstr *OldMI, unsigned Op) {
75 int OpIdx = TII->getOperandIdx(*OldMI, Op);
77 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
78 TII->setImmOperand(*NewMI, Op, Val);
82 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
83 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
84 TII = ST.getInstrInfo();
86 const R600RegisterInfo &TRI = TII->getRegisterInfo();
88 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
90 MachineBasicBlock &MBB = *BB;
91 MachineBasicBlock::iterator I = MBB.begin();
92 while (I != MBB.end()) {
93 MachineInstr &MI = *I;
96 // Expand LDS_*_RET instructions
97 if (TII->isLDSRetInstr(MI.getOpcode())) {
98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
100 MachineOperand &DstOp = MI.getOperand(DstIdx);
101 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
102 DstOp.getReg(), AMDGPU::OQAP);
103 DstOp.setReg(AMDGPU::OQAP);
104 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
105 AMDGPU::OpName::pred_sel);
106 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
107 AMDGPU::OpName::pred_sel);
108 // Copy the pred_sel bit
109 Mov->getOperand(MovPredSelIdx).setReg(
110 MI.getOperand(LDSPredSelIdx).getReg());
113 switch (MI.getOpcode()) {
115 // Expand PRED_X to one of the PRED_SET instructions.
116 case AMDGPU::PRED_X: {
117 uint64_t Flags = MI.getOperand(3).getImm();
118 // The native opcode used by PRED_X is stored as an immediate in the
120 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
121 MI.getOperand(2).getImm(), // opcode
122 MI.getOperand(0).getReg(), // dst
123 MI.getOperand(1).getReg(), // src0
124 AMDGPU::ZERO); // src1
125 TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
126 if (Flags & MO_FLAG_PUSH) {
127 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1);
129 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1);
131 MI.eraseFromParent();
134 case AMDGPU::DOT_4: {
135 const R600RegisterInfo &TRI = TII->getRegisterInfo();
137 unsigned DstReg = MI.getOperand(0).getReg();
138 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
140 for (unsigned Chan = 0; Chan < 4; ++Chan) {
141 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
143 AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
145 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
147 BMI->bundleWithPred();
150 TII->addFlag(*BMI, 0, MO_FLAG_MASK);
153 TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
154 unsigned Opcode = BMI->getOpcode();
155 // While not strictly necessary from hw point of view, we force
156 // all src operands of a dot4 inst to belong to the same slot.
157 unsigned Src0 = BMI->getOperand(
158 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
160 unsigned Src1 = BMI->getOperand(
161 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
165 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
166 (TRI.getEncodingValue(Src1) & 0xff) < 127)
167 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
169 MI.eraseFromParent();
174 bool IsReduction = TII->isReductionOp(MI.getOpcode());
175 bool IsVector = TII->isVector(MI);
176 bool IsCube = TII->isCubeOp(MI.getOpcode());
177 if (!IsReduction && !IsVector && !IsCube) {
181 // Expand the instruction
183 // Reduction instructions:
184 // T0_X = DP4 T1_XYZW, T2_XYZW
186 // TO_X = DP4 T1_X, T2_X
187 // TO_Y (write masked) = DP4 T1_Y, T2_Y
188 // TO_Z (write masked) = DP4 T1_Z, T2_Z
189 // TO_W (write masked) = DP4 T1_W, T2_W
191 // Vector instructions:
192 // T0_X = MULLO_INT T1_X, T2_X
194 // T0_X = MULLO_INT T1_X, T2_X
195 // T0_Y (write masked) = MULLO_INT T1_X, T2_X
196 // T0_Z (write masked) = MULLO_INT T1_X, T2_X
197 // T0_W (write masked) = MULLO_INT T1_X, T2_X
199 // Cube instructions:
200 // T0_XYZW = CUBE T1_XYZW
202 // TO_X = CUBE T1_Z, T1_Y
203 // T0_Y = CUBE T1_Z, T1_X
204 // T0_Z = CUBE T1_X, T1_Z
205 // T0_W = CUBE T1_Y, T1_Z
206 for (unsigned Chan = 0; Chan < 4; Chan++) {
207 unsigned DstReg = MI.getOperand(
208 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
209 unsigned Src0 = MI.getOperand(
210 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
213 // Determine the correct source registers
215 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
217 Src1 = MI.getOperand(Src1Idx).getReg();
221 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
222 Src0 = TRI.getSubReg(Src0, SubRegIndex);
223 Src1 = TRI.getSubReg(Src1, SubRegIndex);
225 static const int CubeSrcSwz[] = {2, 2, 0, 1};
226 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
227 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
228 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
229 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
232 // Determine the correct destination registers;
236 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
237 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
239 // Mask the write if the original instruction does not write to
240 // the current Channel.
241 Mask = (Chan != TRI.getHWRegChan(DstReg));
242 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
243 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
246 // Set the IsLast bit
247 NotLast = (Chan != 3 );
249 // Add the new instruction
250 unsigned Opcode = MI.getOpcode();
252 case AMDGPU::CUBE_r600_pseudo:
253 Opcode = AMDGPU::CUBE_r600_real;
255 case AMDGPU::CUBE_eg_pseudo:
256 Opcode = AMDGPU::CUBE_eg_real;
262 MachineInstr *NewMI =
263 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
266 NewMI->bundleWithPred();
268 TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
271 TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
273 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::clamp);
274 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::literal);
275 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_abs);
276 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_abs);
277 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg);
278 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg);
280 MI.eraseFromParent();