1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
25 class R600TargetLowering final : public AMDGPUTargetLowering {
27 R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
29 const R600Subtarget *getSubtarget() const;
32 EmitInstrWithCustomInserter(MachineInstr &MI,
33 MachineBasicBlock *BB) const override;
34 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
35 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
36 void ReplaceNodeResults(SDNode * N,
37 SmallVectorImpl<SDValue> &Results,
38 SelectionDAG &DAG) const override;
39 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
41 const SmallVectorImpl<ISD::InputArg> &Ins,
42 const SDLoc &DL, SelectionDAG &DAG,
43 SmallVectorImpl<SDValue> &InVals) const override;
44 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
45 EVT VT) const override;
47 bool canMergeStoresTo(unsigned AS, EVT MemVT,
48 const SelectionDAG &DAG) const override;
50 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
52 bool *IsFast) const override;
56 /// Each OpenCL kernel has nine implicit parameters that are stored in the
57 /// first nine dwords of a Vertex Buffer. These implicit parameters are
58 /// lowered to load instructions which retrieve the values from the Vertex
60 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
61 unsigned DwordOffset) const;
63 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
64 MachineRegisterInfo & MRI, unsigned dword_offset) const;
65 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
66 const SDLoc &DL) const;
67 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
69 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
70 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
71 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
72 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
73 SelectionDAG &DAG) const override;
74 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
76 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
77 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
78 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
79 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
88 unsigned mainop, unsigned ovf) const;
90 SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
91 SelectionDAG &DAG) const;
92 void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
93 unsigned &Channel, unsigned &PtrIncr) const;
94 bool isZero(SDValue Op) const;
95 bool isHWTrueValue(SDValue Op) const;
96 bool isHWFalseValue(SDValue Op) const;
98 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
99 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
100 SelectionDAG &DAG) const;
102 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
105 } // End namespace llvm;