1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
25 class R600TargetLowering final : public AMDGPUTargetLowering {
27 R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
29 const R600Subtarget *getSubtarget() const;
32 EmitInstrWithCustomInserter(MachineInstr &MI,
33 MachineBasicBlock *BB) const override;
34 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
35 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
36 void ReplaceNodeResults(SDNode * N,
37 SmallVectorImpl<SDValue> &Results,
38 SelectionDAG &DAG) const override;
39 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
41 const SmallVectorImpl<ISD::InputArg> &Ins,
42 const SDLoc &DL, SelectionDAG &DAG,
43 SmallVectorImpl<SDValue> &InVals) const override;
44 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
45 EVT VT) const override;
47 bool canMergeStoresTo(unsigned AS, EVT MemVT) const override;
49 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
51 bool *IsFast) const override;
55 /// Each OpenCL kernel has nine implicit parameters that are stored in the
56 /// first nine dwords of a Vertex Buffer. These implicit parameters are
57 /// lowered to load instructions which retrieve the values from the Vertex
59 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
60 unsigned DwordOffset) const;
62 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
63 MachineRegisterInfo & MRI, unsigned dword_offset) const;
64 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
65 const SDLoc &DL) const;
66 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
68 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
69 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
70 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
71 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
72 SelectionDAG &DAG) const override;
73 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
75 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
76 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
77 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
78 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
80 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
87 unsigned mainop, unsigned ovf) const;
89 SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
90 SelectionDAG &DAG) const;
91 void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
92 unsigned &Channel, unsigned &PtrIncr) const;
93 bool isZero(SDValue Op) const;
94 bool isHWTrueValue(SDValue Op) const;
95 bool isHWFalseValue(SDValue Op) const;
97 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
98 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
99 SelectionDAG &DAG) const;
101 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
104 } // End namespace llvm;