1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
18 #include "R600RegisterInfo.h"
19 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "R600GenInstrInfo.inc"
26 namespace R600InstrFlags {
28 REGISTER_STORE = UINT64_C(1) << 62,
29 REGISTER_LOAD = UINT64_C(1) << 63
33 class AMDGPUTargetMachine;
35 class MachineFunction;
37 class MachineInstrBuilder;
40 class R600InstrInfo final : public R600GenInstrInfo {
42 const R600RegisterInfo RI;
43 const R600Subtarget &ST;
45 std::vector<std::pair<int, unsigned>>
46 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
47 unsigned &ConstCount) const;
49 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
50 MachineBasicBlock::iterator I,
51 unsigned ValueReg, unsigned Address,
53 unsigned AddrChan) const;
55 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
56 MachineBasicBlock::iterator I,
57 unsigned ValueReg, unsigned Address,
59 unsigned AddrChan) const;
62 ALU_VEC_012_SCL_210 = 0,
70 explicit R600InstrInfo(const R600Subtarget &);
72 const R600RegisterInfo &getRegisterInfo() const {
76 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
77 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
78 bool KillSrc) const override;
79 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MBBI) const override;
82 bool isReductionOp(unsigned opcode) const;
83 bool isCubeOp(unsigned opcode) const;
85 /// \returns true if this \p Opcode represents an ALU instruction.
86 bool isALUInstr(unsigned Opcode) const;
87 bool hasInstrModifiers(unsigned Opcode) const;
88 bool isLDSInstr(unsigned Opcode) const;
89 bool isLDSRetInstr(unsigned Opcode) const;
91 /// \returns true if this \p Opcode represents an ALU instruction or an
92 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
93 bool canBeConsideredALU(const MachineInstr &MI) const;
95 bool isTransOnly(unsigned Opcode) const;
96 bool isTransOnly(const MachineInstr &MI) const;
97 bool isVectorOnly(unsigned Opcode) const;
98 bool isVectorOnly(const MachineInstr &MI) const;
99 bool isExport(unsigned Opcode) const;
101 bool usesVertexCache(unsigned Opcode) const;
102 bool usesVertexCache(const MachineInstr &MI) const;
103 bool usesTextureCache(unsigned Opcode) const;
104 bool usesTextureCache(const MachineInstr &MI) const;
106 bool mustBeLastInClause(unsigned Opcode) const;
107 bool usesAddressRegister(MachineInstr &MI) const;
108 bool definesAddressRegister(MachineInstr &MI) const;
109 bool readsLDSSrcReg(const MachineInstr &MI) const;
111 /// \returns The operand Index for the Sel operand given an index to one
112 /// of the instruction's src operands.
113 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
115 /// \returns a pair for each src of an ALU instructions.
116 /// The first member of a pair is the register id.
117 /// If register is ALU_CONST, second member is SEL.
118 /// If register is ALU_LITERAL, second member is IMM.
119 /// Otherwise, second member value is undefined.
120 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
121 getSrcs(MachineInstr &MI) const;
123 unsigned isLegalUpTo(
124 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
125 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
126 const std::vector<std::pair<int, unsigned> > &TransSrcs,
127 R600InstrInfo::BankSwizzle TransSwz) const;
129 bool FindSwizzleForVectorSlot(
130 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
131 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
132 const std::vector<std::pair<int, unsigned> > &TransSrcs,
133 R600InstrInfo::BankSwizzle TransSwz) const;
135 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
136 /// returns true and the first (in lexical order) BankSwizzle affectation
137 /// starting from the one already provided in the Instruction Group MIs that
138 /// fits Read Port limitations in BS if available. Otherwise returns false
139 /// and undefined content in BS.
140 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
141 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
142 /// apply to the last instruction.
143 /// PV holds GPR to PV registers in the Instruction Group MIs.
144 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
145 const DenseMap<unsigned, unsigned> &PV,
146 std::vector<BankSwizzle> &BS,
147 bool isLastAluTrans) const;
149 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
150 /// from KCache bank on R700+. This function check if MI set in input meet
152 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
153 /// Same but using const index set instead of MI set.
154 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
156 /// Vector instructions are instructions that must fill all
157 /// instruction slots within an instruction group.
158 bool isVector(const MachineInstr &MI) const;
160 bool isMov(unsigned Opcode) const;
163 CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
165 bool reverseBranchCondition(
166 SmallVectorImpl<MachineOperand> &Cond) const override;
168 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
169 MachineBasicBlock *&FBB,
170 SmallVectorImpl<MachineOperand> &Cond,
171 bool AllowModify) const override;
173 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
174 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
176 int *BytesAdded = nullptr) const override;
178 unsigned removeBranch(MachineBasicBlock &MBB,
179 int *BytesRemvoed = nullptr) const override;
181 bool isPredicated(const MachineInstr &MI) const override;
183 bool isPredicable(const MachineInstr &MI) const override;
185 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
186 BranchProbability Probability) const override;
188 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
189 unsigned ExtraPredCycles,
190 BranchProbability Probability) const override ;
192 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
193 unsigned NumTCycles, unsigned ExtraTCycles,
194 MachineBasicBlock &FMBB,
195 unsigned NumFCycles, unsigned ExtraFCycles,
196 BranchProbability Probability) const override;
198 bool DefinesPredicate(MachineInstr &MI,
199 std::vector<MachineOperand> &Pred) const override;
201 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
202 MachineBasicBlock &FMBB) const override;
204 bool PredicateInstruction(MachineInstr &MI,
205 ArrayRef<MachineOperand> Pred) const override;
207 unsigned int getPredicationCost(const MachineInstr &) const override;
209 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
210 const MachineInstr &MI,
211 unsigned *PredCost = nullptr) const override;
213 bool expandPostRAPseudo(MachineInstr &MI) const override;
215 /// Reserve the registers that may be accesed using indirect addressing.
216 void reserveIndirectRegisters(BitVector &Reserved,
217 const MachineFunction &MF,
218 const R600RegisterInfo &TRI) const;
220 /// Calculate the "Indirect Address" for the given \p RegIndex and
223 /// We model indirect addressing using a virtual address space that can be
224 /// accesed with loads and stores. The "Indirect Address" is the memory
225 /// address in this virtual address space that maps to the given \p RegIndex
227 unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
230 /// \returns The register class to be used for loading and storing values
231 /// from an "Indirect Address" .
232 const TargetRegisterClass *getIndirectAddrRegClass() const;
234 /// \returns the smallest register index that will be accessed by an indirect
235 /// read or write or -1 if indirect addressing is not used by this program.
236 int getIndirectIndexBegin(const MachineFunction &MF) const;
238 /// \returns the largest register index that will be accessed by an indirect
239 /// read or write or -1 if indirect addressing is not used by this program.
240 int getIndirectIndexEnd(const MachineFunction &MF) const;
242 /// Build instruction(s) for an indirect register write.
244 /// \returns The instruction that performs the indirect register write
245 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
246 MachineBasicBlock::iterator I,
247 unsigned ValueReg, unsigned Address,
248 unsigned OffsetReg) const;
250 /// Build instruction(s) for an indirect register read.
252 /// \returns The instruction that performs the indirect register read
253 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
254 MachineBasicBlock::iterator I,
255 unsigned ValueReg, unsigned Address,
256 unsigned OffsetReg) const;
258 unsigned getMaxAlusPerClause() const;
260 /// buildDefaultInstruction - This function returns a MachineInstr with all
261 /// the instruction modifiers initialized to their default values. You can
262 /// use this function to avoid manually specifying each instruction modifier
263 /// operand when building a new instruction.
265 /// \returns a MachineInstr with all the instruction modifiers initialized
266 /// to their default values.
267 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator I,
272 unsigned Src1Reg = 0) const;
274 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
277 unsigned DstReg) const;
279 MachineInstr *buildMovImm(MachineBasicBlock &BB,
280 MachineBasicBlock::iterator I,
284 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
285 MachineBasicBlock::iterator I,
286 unsigned DstReg, unsigned SrcReg) const;
288 /// Get the index of Op in the MachineInstr.
290 /// \returns -1 if the Instruction does not contain the specified \p Op.
291 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
293 /// Get the index of \p Op for the given Opcode.
295 /// \returns -1 if the Instruction does not contain the specified \p Op.
296 int getOperandIdx(unsigned Opcode, unsigned Op) const;
298 /// Helper function for setting instruction flag values.
299 void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
301 ///Add one of the MO_FLAG* flags to the specified \p Operand.
302 void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
304 ///Determine if the specified \p Flag is set on this \p Operand.
305 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
307 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
308 /// \param Flag The flag being set.
310 /// \returns the operand containing the flags for this instruction.
311 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
312 unsigned Flag = 0) const;
314 /// Clear the specified flag on the instruction.
315 void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
317 // Helper functions that check the opcode for status information
318 bool isRegisterStore(const MachineInstr &MI) const {
319 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
322 bool isRegisterLoad(const MachineInstr &MI) const {
323 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
326 unsigned getAddressSpaceForPseudoSourceKind(
327 unsigned Kind) const override;
332 int getLDSNoRetOp(uint16_t Opcode);
334 } //End namespace AMDGPU
336 } // End llvm namespace