1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
18 #include "AMDGPUInstrInfo.h"
19 #include "R600RegisterInfo.h"
22 class AMDGPUTargetMachine;
24 class MachineFunction;
26 class MachineInstrBuilder;
29 class R600InstrInfo final : public AMDGPUInstrInfo {
31 const R600RegisterInfo RI;
32 const R600Subtarget &ST;
34 std::vector<std::pair<int, unsigned>>
35 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
36 unsigned &ConstCount) const;
38 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
39 MachineBasicBlock::iterator I,
40 unsigned ValueReg, unsigned Address,
42 unsigned AddrChan) const;
44 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
45 MachineBasicBlock::iterator I,
46 unsigned ValueReg, unsigned Address,
48 unsigned AddrChan) const;
51 ALU_VEC_012_SCL_210 = 0,
59 explicit R600InstrInfo(const R600Subtarget &);
61 const R600RegisterInfo &getRegisterInfo() const {
65 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
66 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
67 bool KillSrc) const override;
68 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator MBBI) const override;
71 bool isReductionOp(unsigned opcode) const;
72 bool isCubeOp(unsigned opcode) const;
74 /// \returns true if this \p Opcode represents an ALU instruction.
75 bool isALUInstr(unsigned Opcode) const;
76 bool hasInstrModifiers(unsigned Opcode) const;
77 bool isLDSInstr(unsigned Opcode) const;
78 bool isLDSRetInstr(unsigned Opcode) const;
80 /// \returns true if this \p Opcode represents an ALU instruction or an
81 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
82 bool canBeConsideredALU(const MachineInstr &MI) const;
84 bool isTransOnly(unsigned Opcode) const;
85 bool isTransOnly(const MachineInstr &MI) const;
86 bool isVectorOnly(unsigned Opcode) const;
87 bool isVectorOnly(const MachineInstr &MI) const;
88 bool isExport(unsigned Opcode) const;
90 bool usesVertexCache(unsigned Opcode) const;
91 bool usesVertexCache(const MachineInstr &MI) const;
92 bool usesTextureCache(unsigned Opcode) const;
93 bool usesTextureCache(const MachineInstr &MI) const;
95 bool mustBeLastInClause(unsigned Opcode) const;
96 bool usesAddressRegister(MachineInstr &MI) const;
97 bool definesAddressRegister(MachineInstr &MI) const;
98 bool readsLDSSrcReg(const MachineInstr &MI) const;
100 /// \returns The operand Index for the Sel operand given an index to one
101 /// of the instruction's src operands.
102 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
104 /// \returns a pair for each src of an ALU instructions.
105 /// The first member of a pair is the register id.
106 /// If register is ALU_CONST, second member is SEL.
107 /// If register is ALU_LITERAL, second member is IMM.
108 /// Otherwise, second member value is undefined.
109 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
110 getSrcs(MachineInstr &MI) const;
112 unsigned isLegalUpTo(
113 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
114 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
115 const std::vector<std::pair<int, unsigned> > &TransSrcs,
116 R600InstrInfo::BankSwizzle TransSwz) const;
118 bool FindSwizzleForVectorSlot(
119 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
120 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
121 const std::vector<std::pair<int, unsigned> > &TransSrcs,
122 R600InstrInfo::BankSwizzle TransSwz) const;
124 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
125 /// returns true and the first (in lexical order) BankSwizzle affectation
126 /// starting from the one already provided in the Instruction Group MIs that
127 /// fits Read Port limitations in BS if available. Otherwise returns false
128 /// and undefined content in BS.
129 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
130 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
131 /// apply to the last instruction.
132 /// PV holds GPR to PV registers in the Instruction Group MIs.
133 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
134 const DenseMap<unsigned, unsigned> &PV,
135 std::vector<BankSwizzle> &BS,
136 bool isLastAluTrans) const;
138 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
139 /// from KCache bank on R700+. This function check if MI set in input meet
141 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
142 /// Same but using const index set instead of MI set.
143 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
145 /// \brief Vector instructions are instructions that must fill all
146 /// instruction slots within an instruction group.
147 bool isVector(const MachineInstr &MI) const;
149 bool isMov(unsigned Opcode) const;
152 CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
154 bool ReverseBranchCondition(
155 SmallVectorImpl<MachineOperand> &Cond) const override;
157 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
158 MachineBasicBlock *&FBB,
159 SmallVectorImpl<MachineOperand> &Cond,
160 bool AllowModify) const override;
162 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
163 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
164 const DebugLoc &DL) const override;
166 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
168 bool isPredicated(const MachineInstr &MI) const override;
170 bool isPredicable(MachineInstr &MI) const override;
172 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
173 BranchProbability Probability) const override;
175 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
176 unsigned ExtraPredCycles,
177 BranchProbability Probability) const override ;
179 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
180 unsigned NumTCycles, unsigned ExtraTCycles,
181 MachineBasicBlock &FMBB,
182 unsigned NumFCycles, unsigned ExtraFCycles,
183 BranchProbability Probability) const override;
185 bool DefinesPredicate(MachineInstr &MI,
186 std::vector<MachineOperand> &Pred) const override;
188 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
189 MachineBasicBlock &FMBB) const override;
191 bool PredicateInstruction(MachineInstr &MI,
192 ArrayRef<MachineOperand> Pred) const override;
194 unsigned int getPredicationCost(const MachineInstr &) const override;
196 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
197 const MachineInstr &MI,
198 unsigned *PredCost = nullptr) const override;
200 bool expandPostRAPseudo(MachineInstr &MI) const override;
202 /// \brief Reserve the registers that may be accesed using indirect addressing.
203 void reserveIndirectRegisters(BitVector &Reserved,
204 const MachineFunction &MF) const;
206 /// Calculate the "Indirect Address" for the given \p RegIndex and
209 /// We model indirect addressing using a virtual address space that can be
210 /// accesed with loads and stores. The "Indirect Address" is the memory
211 /// address in this virtual address space that maps to the given \p RegIndex
213 unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
216 /// \returns The register class to be used for loading and storing values
217 /// from an "Indirect Address" .
218 const TargetRegisterClass *getIndirectAddrRegClass() const;
220 /// \returns the smallest register index that will be accessed by an indirect
221 /// read or write or -1 if indirect addressing is not used by this program.
222 int getIndirectIndexBegin(const MachineFunction &MF) const;
224 /// \returns the largest register index that will be accessed by an indirect
225 /// read or write or -1 if indirect addressing is not used by this program.
226 int getIndirectIndexEnd(const MachineFunction &MF) const;
228 /// \brief Build instruction(s) for an indirect register write.
230 /// \returns The instruction that performs the indirect register write
231 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
232 MachineBasicBlock::iterator I,
233 unsigned ValueReg, unsigned Address,
234 unsigned OffsetReg) const;
236 /// \brief Build instruction(s) for an indirect register read.
238 /// \returns The instruction that performs the indirect register read
239 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
240 MachineBasicBlock::iterator I,
241 unsigned ValueReg, unsigned Address,
242 unsigned OffsetReg) const;
244 unsigned getMaxAlusPerClause() const;
246 /// buildDefaultInstruction - This function returns a MachineInstr with all
247 /// the instruction modifiers initialized to their default values. You can
248 /// use this function to avoid manually specifying each instruction modifier
249 /// operand when building a new instruction.
251 /// \returns a MachineInstr with all the instruction modifiers initialized
252 /// to their default values.
253 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
254 MachineBasicBlock::iterator I,
258 unsigned Src1Reg = 0) const;
260 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
263 unsigned DstReg) const;
265 MachineInstr *buildMovImm(MachineBasicBlock &BB,
266 MachineBasicBlock::iterator I,
270 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
271 MachineBasicBlock::iterator I,
272 unsigned DstReg, unsigned SrcReg) const;
274 /// \brief Get the index of Op in the MachineInstr.
276 /// \returns -1 if the Instruction does not contain the specified \p Op.
277 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
279 /// \brief Get the index of \p Op for the given Opcode.
281 /// \returns -1 if the Instruction does not contain the specified \p Op.
282 int getOperandIdx(unsigned Opcode, unsigned Op) const;
284 /// \brief Helper function for setting instruction flag values.
285 void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
287 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
288 void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
290 ///\brief Determine if the specified \p Flag is set on this \p Operand.
291 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
293 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
294 /// \param Flag The flag being set.
296 /// \returns the operand containing the flags for this instruction.
297 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
298 unsigned Flag = 0) const;
300 /// \brief Clear the specified flag on the instruction.
301 void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
303 // Helper functions that check the opcode for status information
304 bool isRegisterStore(const MachineInstr &MI) const;
305 bool isRegisterLoad(const MachineInstr &MI) const;
310 int getLDSNoRetOp(uint16_t Opcode);
312 } //End namespace AMDGPU
314 } // End llvm namespace