1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are available on R600 family
13 //===----------------------------------------------------------------------===//
15 include "R600Intrinsics.td"
16 include "R600InstrFormats.td"
18 // FIXME: Should not be arbitrarily split from other R600 inst classes.
19 class R600WrapperInst <dag outs, dag ins, string asm = "", list<dag> pattern = []> :
20 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
21 let SubtargetPredicate = isR600toCayman;
25 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> :
26 InstR600 <outs, ins, asm, pattern, NullALU> {
28 let Namespace = "AMDGPU";
31 def MEMxi : Operand<iPTR> {
32 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
33 let PrintMethod = "printMemOperand";
36 def MEMrr : Operand<iPTR> {
37 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
40 // Operands for non-registers
42 class InstFlag<string PM = "printOperand", int Default = 0>
43 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
47 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
48 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))>;
49 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
50 let PrintMethod = "printBankSwizzle";
53 def LITERAL : InstFlag<"printLiteral">;
55 def WRITE : InstFlag <"printWrite", 1>;
56 def OMOD : InstFlag <"printOMOD">;
57 def REL : InstFlag <"printRel">;
58 def CLAMP : InstFlag <"printClamp">;
59 def NEG : InstFlag <"printNeg">;
60 def ABS : InstFlag <"printAbs">;
61 def UEM : InstFlag <"printUpdateExecMask">;
62 def UP : InstFlag <"printUpdatePred">;
64 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
65 // Once we start using the packetizer in this backend we should have this
67 def LAST : InstFlag<"printLast", 1>;
68 def RSel : Operand<i32> {
69 let PrintMethod = "printRSel";
71 def CT: Operand<i32> {
72 let PrintMethod = "printCT";
75 def FRAMEri : Operand<iPTR> {
76 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
79 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
80 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
81 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
82 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
83 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
86 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
90 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
92 // Class for instructions with only one source register.
93 // If you add new ins to this instruction, make sure they are listed before
94 // $literal, because the backend currently assumes that the last operand is
95 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
96 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
97 // and R600InstrInfo::getOperandIdx().
98 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
99 InstrItinClass itin = AnyALU> :
100 InstR600 <(outs R600_Reg32:$dst),
101 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
102 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
103 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
104 BANK_SWIZZLE:$bank_swizzle),
105 !strconcat(" ", opName,
106 "$clamp $last $dst$write$dst_rel$omod, "
107 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
108 "$pred_sel $bank_swizzle"),
112 R600ALU_Word1_OP2 <inst> {
118 let update_exec_mask = 0;
120 let HasNativeOperands = 1;
123 let DisableEncoding = "$literal";
124 let UseNamedOperandTable = 1;
126 let Inst{31-0} = Word0;
127 let Inst{63-32} = Word1;
130 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
131 InstrItinClass itin = AnyALU> :
132 R600_1OP <inst, opName,
133 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
136 // If you add or change the operands for R600_2OP instructions, you must
137 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
138 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
139 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
140 InstrItinClass itin = AnyALU> :
141 InstR600 <(outs R600_Reg32:$dst),
142 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
143 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
144 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
145 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
146 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
147 BANK_SWIZZLE:$bank_swizzle),
148 !strconcat(" ", opName,
149 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
150 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
151 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
152 "$pred_sel $bank_swizzle"),
156 R600ALU_Word1_OP2 <inst> {
158 let HasNativeOperands = 1;
161 let DisableEncoding = "$literal";
162 let UseNamedOperandTable = 1;
164 let Inst{31-0} = Word0;
165 let Inst{63-32} = Word1;
168 class R600_2OP_Helper <bits<11> inst, string opName,
169 SDPatternOperator node = null_frag,
170 InstrItinClass itin = AnyALU> :
171 R600_2OP <inst, opName,
172 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
173 R600_Reg32:$src1))], itin
176 // If you add our change the operands for R600_3OP instructions, you must
177 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
178 // R600InstrInfo::buildDefaultInstruction(), and
179 // R600InstrInfo::getOperandIdx().
180 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
181 InstrItinClass itin = AnyALU> :
182 InstR600 <(outs R600_Reg32:$dst),
183 (ins REL:$dst_rel, CLAMP:$clamp,
184 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
185 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
186 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
187 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
188 BANK_SWIZZLE:$bank_swizzle),
189 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
190 "$src0_neg$src0$src0_rel, "
191 "$src1_neg$src1$src1_rel, "
192 "$src2_neg$src2$src2_rel, "
198 R600ALU_Word1_OP3<inst>{
200 let HasNativeOperands = 1;
201 let DisableEncoding = "$literal";
203 let UseNamedOperandTable = 1;
206 let Inst{31-0} = Word0;
207 let Inst{63-32} = Word1;
210 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
211 InstrItinClass itin = VecALU> :
212 InstR600 <(outs R600_Reg32:$dst),
220 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
222 def TEX_SHADOW : PatLeaf<
224 [{uint32_t TType = (uint32_t)N->getZExtValue();
225 return (TType >= 6 && TType <= 8) || TType == 13;
229 def TEX_RECT : PatLeaf<
231 [{uint32_t TType = (uint32_t)N->getZExtValue();
236 def TEX_ARRAY : PatLeaf<
238 [{uint32_t TType = (uint32_t)N->getZExtValue();
239 return TType == 9 || TType == 10 || TType == 16;
243 def TEX_SHADOW_ARRAY : PatLeaf<
245 [{uint32_t TType = (uint32_t)N->getZExtValue();
246 return TType == 11 || TType == 12 || TType == 17;
250 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
251 dag outs, dag ins, string asm, list<dag> pattern> :
252 InstR600ISA <outs, ins, asm, pattern>,
253 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
256 let rat_inst = ratinst;
258 // XXX: Have a separate instruction for non-indexed writes.
264 let comp_mask = mask;
267 let cf_inst = cfinst;
271 let Inst{31-0} = Word0;
272 let Inst{63-32} = Word1;
277 class VTX_READ <string name, dag outs, list<dag> pattern>
278 : InstR600ISA <outs, (ins MEMxi:$src_gpr, i8imm:$buffer_id), !strconcat(" ", name, ", #$buffer_id"), pattern>,
283 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
284 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
285 // however, based on my testing if USE_CONST_FIELDS is set, then all
286 // these fields need to be set to 0.
287 let USE_CONST_FIELDS = 0;
288 let NUM_FORMAT_ALL = 1;
289 let FORMAT_COMP_ALL = 0;
290 let SRF_MODE_ALL = 0;
292 let Inst{63-32} = Word1;
293 // LLVM can only encode 64-bit instructions, so these fields are manually
294 // encoded in R600CodeEmitter
297 // bits<2> ENDIAN_SWAP = 0;
298 // bits<1> CONST_BUF_NO_STRIDE = 0;
299 // bits<1> MEGA_FETCH = 0;
300 // bits<1> ALT_CONST = 0;
301 // bits<2> BUFFER_INDEX_MODE = 0;
303 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
304 // is done in R600CodeEmitter
306 // Inst{79-64} = OFFSET;
307 // Inst{81-80} = ENDIAN_SWAP;
308 // Inst{82} = CONST_BUF_NO_STRIDE;
309 // Inst{83} = MEGA_FETCH;
310 // Inst{84} = ALT_CONST;
311 // Inst{86-85} = BUFFER_INDEX_MODE;
312 // Inst{95-86} = 0; Reserved
314 // VTX_WORD3 (Padding)
321 class LoadParamFrag <PatFrag load_type> : PatFrag <
322 (ops node:$ptr), (load_type node:$ptr),
323 [{ return isConstantLoad(cast<LoadSDNode>(N), 0) ||
324 (cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUASI.PARAM_I_ADDRESS); }]
327 def vtx_id3_az_extloadi8 : LoadParamFrag<az_extloadi8>;
328 def vtx_id3_az_extloadi16 : LoadParamFrag<az_extloadi16>;
329 def vtx_id3_load : LoadParamFrag<load>;
331 class LoadVtxId1 <PatFrag load> : PatFrag <
332 (ops node:$ptr), (load node:$ptr), [{
333 const MemSDNode *LD = cast<MemSDNode>(N);
334 return LD->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS ||
335 (LD->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS &&
336 !isa<GlobalValue>(GetUnderlyingObject(
337 LD->getMemOperand()->getValue(), CurDAG->getDataLayout())));
340 def vtx_id1_az_extloadi8 : LoadVtxId1 <az_extloadi8>;
341 def vtx_id1_az_extloadi16 : LoadVtxId1 <az_extloadi16>;
342 def vtx_id1_load : LoadVtxId1 <load>;
344 class LoadVtxId2 <PatFrag load> : PatFrag <
345 (ops node:$ptr), (load node:$ptr), [{
346 const MemSDNode *LD = cast<MemSDNode>(N);
347 return LD->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS &&
348 isa<GlobalValue>(GetUnderlyingObject(
349 LD->getMemOperand()->getValue(), CurDAG->getDataLayout()));
352 def vtx_id2_az_extloadi8 : LoadVtxId2 <az_extloadi8>;
353 def vtx_id2_az_extloadi16 : LoadVtxId2 <az_extloadi16>;
354 def vtx_id2_load : LoadVtxId2 <load>;
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 def INTERP_PAIR_XY : AMDGPUShaderInst <
361 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
362 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
363 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
366 def INTERP_PAIR_ZW : AMDGPUShaderInst <
367 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
368 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
369 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
372 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
373 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
377 def DOT4 : SDNode<"AMDGPUISD::DOT4",
378 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
379 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
380 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
384 def COS_HW : SDNode<"AMDGPUISD::COS_HW",
385 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
388 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
389 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
392 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
394 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
396 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
397 def : R600Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
398 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
399 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
400 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
401 (i32 imm:$DST_SEL_W),
402 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
403 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
404 (i32 imm:$COORD_TYPE_W)),
405 (inst R600_Reg128:$SRC_GPR,
406 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
407 imm:$offsetx, imm:$offsety, imm:$offsetz,
408 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
410 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
411 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
415 //===----------------------------------------------------------------------===//
416 // Interpolation Instructions
417 //===----------------------------------------------------------------------===//
419 def INTERP_VEC_LOAD : AMDGPUShaderInst <
420 (outs R600_Reg128:$dst),
422 "INTERP_LOAD $src0 : $dst">;
424 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
425 let bank_swizzle = 5;
428 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
429 let bank_swizzle = 5;
432 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
434 //===----------------------------------------------------------------------===//
435 // Export Instructions
436 //===----------------------------------------------------------------------===//
439 field bits<32> Word0;
446 let Word0{12-0} = arraybase;
447 let Word0{14-13} = type;
448 let Word0{21-15} = gpr;
449 let Word0{22} = 0; // RW_REL
450 let Word0{29-23} = 0; // INDEX_GPR
451 let Word0{31-30} = elem_size;
454 class ExportSwzWord1 {
455 field bits<32> Word1;
464 let Word1{2-0} = sw_x;
465 let Word1{5-3} = sw_y;
466 let Word1{8-6} = sw_z;
467 let Word1{11-9} = sw_w;
470 class ExportBufWord1 {
471 field bits<32> Word1;
478 let Word1{11-0} = arraySize;
479 let Word1{15-12} = compMask;
482 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
483 def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
484 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
485 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
486 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
491 multiclass SteamOutputExportPattern<Instruction ExportInst,
492 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
494 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
495 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
496 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
497 4095, imm:$mask, buf0inst, 0)>;
499 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
500 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
501 (ExportInst $src, 0, imm:$arraybase,
502 4095, imm:$mask, buf1inst, 0)>;
504 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
505 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
506 (ExportInst $src, 0, imm:$arraybase,
507 4095, imm:$mask, buf2inst, 0)>;
509 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
510 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
511 (ExportInst $src, 0, imm:$arraybase,
512 4095, imm:$mask, buf3inst, 0)>;
515 // Export Instructions should not be duplicated by TailDuplication pass
516 // (which assumes that duplicable instruction are affected by exec mask)
517 let usesCustomInserter = 1, isNotDuplicable = 1 in {
519 class ExportSwzInst : InstR600ISA<(
521 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
522 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,
524 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),
525 []>, ExportWord0, ExportSwzWord1 {
527 let Inst{31-0} = Word0;
528 let Inst{63-32} = Word1;
532 } // End usesCustomInserter = 1
534 class ExportBufInst : InstR600ISA<(
536 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
537 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
538 !strconcat("EXPORT", " $gpr"),
539 []>, ExportWord0, ExportBufWord1 {
541 let Inst{31-0} = Word0;
542 let Inst{63-32} = Word1;
546 //===----------------------------------------------------------------------===//
547 // Control Flow Instructions
548 //===----------------------------------------------------------------------===//
551 def KCACHE : InstFlag<"printKCache">;
553 class ALU_CLAUSE<bits<4> inst, string OpName> : R600WrapperInst <(outs),
554 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
555 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
556 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
557 i32imm:$COUNT, i32imm:$Enabled),
558 !strconcat(OpName, " $COUNT, @$ADDR, "
559 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
560 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
565 let WHOLE_QUAD_MODE = 0;
567 let isCodeGenOnly = 1;
568 let UseNamedOperandTable = 1;
570 let Inst{31-0} = Word0;
571 let Inst{63-32} = Word1;
574 class CF_WORD0_R600 {
575 field bits<32> Word0;
582 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs),
583 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
590 let VALID_PIXEL_MODE = 0;
592 let COUNT = CNT{2-0};
594 let COUNT_3 = CNT{3};
595 let END_OF_PROGRAM = 0;
596 let WHOLE_QUAD_MODE = 0;
598 let Inst{31-0} = Word0;
599 let Inst{63-32} = Word1;
602 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs),
603 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
608 let JUMPTABLE_SEL = 0;
610 let VALID_PIXEL_MODE = 0;
612 let END_OF_PROGRAM = 0;
614 let Inst{31-0} = Word0;
615 let Inst{63-32} = Word1;
618 def CF_ALU : ALU_CLAUSE<8, "ALU">;
619 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
620 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
621 def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">;
622 def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">;
623 def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">;
625 def FETCH_CLAUSE : R600WrapperInst <(outs),
626 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
630 let isCodeGenOnly = 1;
633 def ALU_CLAUSE : R600WrapperInst <(outs),
634 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
638 let isCodeGenOnly = 1;
641 def LITERALS : R600WrapperInst <(outs),
642 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
643 let isCodeGenOnly = 1;
649 let Inst{31-0} = literal1;
650 let Inst{63-32} = literal2;
653 def PAD : R600WrapperInst <(outs), (ins), "PAD", [] > {
657 //===----------------------------------------------------------------------===//
658 // Common Instructions R600, R700, Evergreen, Cayman
659 //===----------------------------------------------------------------------===//
661 let isCodeGenOnly = 1, isPseudo = 1 in {
663 let usesCustomInserter = 1 in {
665 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
669 [(set f32:$dst, (AMDGPUclamp f32:$src0))]
672 class FABS <RegisterClass rc> : AMDGPUShaderInst <
676 [(set f32:$dst, (fabs f32:$src0))]
679 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
683 [(set f32:$dst, (fneg f32:$src0))]
686 } // usesCustomInserter = 1
688 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
689 ComplexPattern addrPat> {
690 let UseNamedOperandTable = 1 in {
692 def RegisterLoad : AMDGPUShaderInst <
693 (outs dstClass:$dst),
694 (ins addrClass:$addr, i32imm:$chan),
695 "RegisterLoad $dst, $addr",
696 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
698 let isRegisterLoad = 1;
701 def RegisterStore : AMDGPUShaderInst <
703 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
704 "RegisterStore $val, $addr",
705 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
707 let isRegisterStore = 1;
712 } // End isCodeGenOnly = 1, isPseudo = 1
715 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
716 // Non-IEEE MUL: 0 * anything = 0
717 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE">;
718 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
719 // TODO: Do these actually match the regular fmin/fmax behavior?
720 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>;
721 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>;
722 // According to https://msdn.microsoft.com/en-us/library/windows/desktop/cc308050%28v=vs.85%29.aspx
723 // DX10 min/max returns the other operand if one is NaN,
724 // this matches http://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic
725 def MAX_DX10 : R600_2OP_Helper <0x5, "MAX_DX10", fmaxnum>;
726 def MIN_DX10 : R600_2OP_Helper <0x6, "MIN_DX10", fminnum>;
728 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
729 // so some of the instruction names don't match the asm string.
730 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
731 def SETE : R600_2OP <
733 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]
738 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))]
743 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))]
748 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))]
751 def SETE_DX10 : R600_2OP <
753 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))]
756 def SETGT_DX10 : R600_2OP <
758 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))]
761 def SETGE_DX10 : R600_2OP <
763 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))]
766 // FIXME: This should probably be COND_ONE
767 def SETNE_DX10 : R600_2OP <
769 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))]
772 // FIXME: Need combine for AMDGPUfract
773 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
774 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>;
775 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
776 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
777 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
779 def MOV : R600_1OP <0x19, "MOV", []>;
782 // This is a hack to get rid of DUMMY_CHAIN nodes.
783 // Most DUMMY_CHAINs should be eliminated during legalization, but undef
784 // values can sneak in some to selection.
785 let isPseudo = 1, isCodeGenOnly = 1 in {
786 def DUMMY_CHAIN : R600WrapperInst <
792 } // end let isPseudo = 1, isCodeGenOnly = 1
795 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
797 class MOV_IMM <ValueType vt, Operand immType> : R600WrapperInst <
798 (outs R600_Reg32:$dst),
804 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
806 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
809 (MOV_IMM_I32 imm:$val)
812 def MOV_IMM_GLOBAL_ADDR : MOV_IMM<iPTR, i32imm>;
814 (AMDGPUconstdata_ptr tglobaladdr:$addr),
815 (MOV_IMM_GLOBAL_ADDR tglobaladdr:$addr)
819 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
822 (MOV_IMM_F32 fpimm:$val)
825 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
826 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
827 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
828 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
830 let hasSideEffects = 1 in {
832 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
834 } // end hasSideEffects
836 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
837 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
838 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
839 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
840 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
841 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
842 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", smax>;
843 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", smin>;
844 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", umax>;
845 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", umin>;
847 def SETE_INT : R600_2OP <
849 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
852 def SETGT_INT : R600_2OP <
854 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
857 def SETGE_INT : R600_2OP <
859 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
862 def SETNE_INT : R600_2OP <
864 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
867 def SETGT_UINT : R600_2OP <
869 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
872 def SETGE_UINT : R600_2OP <
874 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
877 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
878 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
879 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
880 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
882 def CNDE_INT : R600_3OP <
884 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
887 def CNDGE_INT : R600_3OP <
889 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))]
892 def CNDGT_INT : R600_3OP <
894 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))]
897 //===----------------------------------------------------------------------===//
898 // Texture instructions
899 //===----------------------------------------------------------------------===//
901 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
903 class R600_TEX <bits<11> inst, string opName> :
904 InstR600 <(outs R600_Reg128:$DST_GPR),
905 (ins R600_Reg128:$SRC_GPR,
906 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
907 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
908 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
909 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
910 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
912 !strconcat(" ", opName,
913 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
914 "$SRC_GPR.$srcx$srcy$srcz$srcw "
915 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
916 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
918 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
919 let Inst{31-0} = Word0;
920 let Inst{63-32} = Word1;
922 let TEX_INST = inst{4-0};
928 let FETCH_WHOLE_QUAD = 0;
930 let SAMPLER_INDEX_MODE = 0;
931 let RESOURCE_INDEX_MODE = 0;
936 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
940 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
941 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
942 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
943 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
944 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
945 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
946 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
947 def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> {
950 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
951 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
952 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
953 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
954 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
955 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
956 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
958 defm : TexPattern<0, TEX_SAMPLE>;
959 defm : TexPattern<1, TEX_SAMPLE_C>;
960 defm : TexPattern<2, TEX_SAMPLE_L>;
961 defm : TexPattern<3, TEX_SAMPLE_C_L>;
962 defm : TexPattern<4, TEX_SAMPLE_LB>;
963 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
964 defm : TexPattern<6, TEX_LD, v4i32>;
965 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
966 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
967 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
968 defm : TexPattern<10, TEX_LDPTR, v4i32>;
970 //===----------------------------------------------------------------------===//
971 // Helper classes for common instructions
972 //===----------------------------------------------------------------------===//
974 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
979 class MULADD_Common <bits<5> inst> : R600_3OP <
984 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
986 [(set f32:$dst, (fmad f32:$src0, f32:$src1, f32:$src2))]
989 class FMA_Common <bits<5> inst> : R600_3OP <
991 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU
994 let OtherPredicates = [FMA];
997 class CNDE_Common <bits<5> inst> : R600_3OP <
999 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]
1002 class CNDGT_Common <bits<5> inst> : R600_3OP <
1004 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))]
1006 let Itinerary = VecALU;
1009 class CNDGE_Common <bits<5> inst> : R600_3OP <
1011 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))]
1013 let Itinerary = VecALU;
1017 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1018 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
1020 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
1021 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
1022 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
1023 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
1024 R600_Pred:$pred_sel_X,
1026 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
1027 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
1028 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
1029 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
1030 R600_Pred:$pred_sel_Y,
1032 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
1033 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
1034 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
1035 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
1036 R600_Pred:$pred_sel_Z,
1038 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
1039 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
1040 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
1041 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
1042 R600_Pred:$pred_sel_W,
1043 LITERAL:$literal0, LITERAL:$literal1),
1048 let UseNamedOperandTable = 1;
1053 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
1054 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
1055 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
1056 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
1057 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
1060 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
1063 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1064 multiclass CUBE_Common <bits<11> inst> {
1066 def _pseudo : InstR600 <
1067 (outs R600_Reg128:$dst),
1068 (ins R600_Reg128:$src0),
1070 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))],
1074 let UseNamedOperandTable = 1;
1077 def _real : R600_2OP <inst, "CUBE", []>;
1079 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1081 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1082 inst, "EXP_IEEE", fexp2
1084 let Itinerary = TransALU;
1087 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1088 inst, "FLT_TO_INT", fp_to_sint
1090 let Itinerary = TransALU;
1093 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1094 inst, "INT_TO_FLT", sint_to_fp
1096 let Itinerary = TransALU;
1099 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1100 inst, "FLT_TO_UINT", fp_to_uint
1102 let Itinerary = TransALU;
1105 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1106 inst, "UINT_TO_FLT", uint_to_fp
1108 let Itinerary = TransALU;
1111 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1112 inst, "LOG_CLAMPED", []
1115 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1116 inst, "LOG_IEEE", flog2
1118 let Itinerary = TransALU;
1121 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1122 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1123 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1124 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1125 inst, "MULHI_INT", mulhs> {
1126 let Itinerary = TransALU;
1129 class MULHI_INT24_Common <bits<11> inst> : R600_2OP_Helper <
1130 inst, "MULHI_INT24", AMDGPUmulhi_i24> {
1131 let Itinerary = VecALU;
1134 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1135 inst, "MULHI", mulhu> {
1136 let Itinerary = TransALU;
1139 class MULHI_UINT24_Common <bits<11> inst> : R600_2OP_Helper <
1140 inst, "MULHI_UINT24", AMDGPUmulhi_u24> {
1141 let Itinerary = VecALU;
1144 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1145 inst, "MULLO_INT", mul> {
1146 let Itinerary = TransALU;
1148 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1149 let Itinerary = TransALU;
1152 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1153 inst, "RECIP_CLAMPED", []
1155 let Itinerary = TransALU;
1158 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1159 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))]
1161 let Itinerary = TransALU;
1164 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1165 inst, "RECIP_UINT", AMDGPUurecip
1167 let Itinerary = TransALU;
1170 // Clamped to maximum.
1171 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1172 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamp
1174 let Itinerary = TransALU;
1177 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1178 inst, "RECIPSQRT_IEEE", AMDGPUrsq> {
1179 let Itinerary = TransALU;
1182 // TODO: There is also RECIPSQRT_FF which clamps to zero.
1184 class SIN_Common <bits<11> inst> : R600_1OP <
1185 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1187 let Itinerary = TransALU;
1190 class COS_Common <bits<11> inst> : R600_1OP <
1191 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1193 let Itinerary = TransALU;
1196 def CLAMP_R600 : CLAMP <R600_Reg32>;
1197 def FABS_R600 : FABS<R600_Reg32>;
1198 def FNEG_R600 : FNEG<R600_Reg32>;
1200 //===----------------------------------------------------------------------===//
1201 // Helper patterns for complex intrinsics
1202 //===----------------------------------------------------------------------===//
1204 // FIXME: Should be predicated on unsafe fp math.
1205 multiclass DIV_Common <InstR600 recip_ieee> {
1207 (fdiv f32:$src0, f32:$src1),
1208 (MUL_IEEE $src0, (recip_ieee $src1))
1211 def : RcpPat<recip_ieee, f32>;
1214 //===----------------------------------------------------------------------===//
1215 // R600 / R700 Instructions
1216 //===----------------------------------------------------------------------===//
1218 let Predicates = [isR600] in {
1220 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1221 def MULADD_r600 : MULADD_Common<0x10>;
1222 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1223 def CNDE_r600 : CNDE_Common<0x18>;
1224 def CNDGT_r600 : CNDGT_Common<0x19>;
1225 def CNDGE_r600 : CNDGE_Common<0x1A>;
1226 def DOT4_r600 : DOT4_Common<0x50>;
1227 defm CUBE_r600 : CUBE_Common<0x52>;
1228 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1229 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1230 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1231 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1232 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1233 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1234 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1235 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1236 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1237 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1238 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1239 def SIN_r600 : SIN_Common<0x6E>;
1240 def COS_r600 : COS_Common<0x6F>;
1241 def ASHR_r600 : ASHR_Common<0x70>;
1242 def LSHR_r600 : LSHR_Common<0x71>;
1243 def LSHL_r600 : LSHL_Common<0x72>;
1244 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1245 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1246 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1247 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1248 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1250 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1251 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1253 def : R600Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1254 def : RsqPat<RECIPSQRT_IEEE_r600, f32>;
1256 def R600_ExportSwz : ExportSwzInst {
1257 let Word1{20-17} = 0; // BURST_COUNT
1258 let Word1{21} = eop;
1259 let Word1{22} = 0; // VALID_PIXEL_MODE
1260 let Word1{30-23} = inst;
1261 let Word1{31} = 1; // BARRIER
1263 defm : ExportPattern<R600_ExportSwz, 39>;
1265 def R600_ExportBuf : ExportBufInst {
1266 let Word1{20-17} = 0; // BURST_COUNT
1267 let Word1{21} = eop;
1268 let Word1{22} = 0; // VALID_PIXEL_MODE
1269 let Word1{30-23} = inst;
1270 let Word1{31} = 1; // BARRIER
1272 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1274 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1275 "TEX $CNT @$ADDR"> {
1278 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1279 "VTX $CNT @$ADDR"> {
1282 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1283 "LOOP_START_DX10 @$ADDR"> {
1287 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1291 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1292 "LOOP_BREAK @$ADDR"> {
1296 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1297 "CONTINUE @$ADDR"> {
1301 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1302 "JUMP @$ADDR POP:$POP_COUNT"> {
1305 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR),
1306 "PUSH_ELSE @$ADDR"> {
1308 let POP_COUNT = 0; // FIXME?
1310 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1311 "ELSE @$ADDR POP:$POP_COUNT"> {
1314 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1319 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1320 "POP @$ADDR POP:$POP_COUNT"> {
1323 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1327 let END_OF_PROGRAM = 1;
1333 //===----------------------------------------------------------------------===//
1334 // Regist loads and stores - for indirect addressing
1335 //===----------------------------------------------------------------------===//
1337 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1339 // Hardcode channel to 0
1340 // NOTE: LSHR is not available here. LSHR is per family instruction
1342 (i32 (load_private ADDRIndirect:$addr) ),
1343 (R600_RegisterLoad FRAMEri:$addr, (i32 0))
1346 (store_private i32:$val, ADDRIndirect:$addr),
1347 (R600_RegisterStore i32:$val, FRAMEri:$addr, (i32 0))
1351 //===----------------------------------------------------------------------===//
1352 // Pseudo instructions
1353 //===----------------------------------------------------------------------===//
1355 let isPseudo = 1 in {
1357 def PRED_X : InstR600 <
1358 (outs R600_Predicate_Bit:$dst),
1359 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1361 let FlagOperandIdx = 3;
1364 let isTerminator = 1, isBranch = 1 in {
1365 def JUMP_COND : InstR600 <
1367 (ins brtarget:$target, R600_Predicate_Bit:$p),
1368 "JUMP $target ($p)",
1372 def JUMP : InstR600 <
1374 (ins brtarget:$target),
1379 let isPredicable = 1;
1383 } // End isTerminator = 1, isBranch = 1
1385 let usesCustomInserter = 1 in {
1387 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1389 def MASK_WRITE : AMDGPUShaderInst <
1391 (ins R600_Reg32:$src),
1396 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1400 (outs R600_Reg128:$dst),
1401 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1402 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1403 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [],
1408 def TXD_SHADOW: InstR600 <
1409 (outs R600_Reg128:$dst),
1410 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1411 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1412 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1416 } // End isPseudo = 1
1417 } // End usesCustomInserter = 1
1420 //===----------------------------------------------------------------------===//
1421 // Constant Buffer Addressing Support
1422 //===----------------------------------------------------------------------===//
1424 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1425 def CONST_COPY : Instruction {
1426 let OutOperandList = (outs R600_Reg32:$dst);
1427 let InOperandList = (ins i32imm:$src);
1429 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1430 let AsmString = "CONST_COPY";
1431 let hasSideEffects = 0;
1432 let isAsCheapAsAMove = 1;
1433 let Itinerary = NullALU;
1435 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1437 def TEX_VTX_CONSTBUF :
1438 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "VTX_READ_eg $dst, $ptr",
1439 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$buffer_id)))]>,
1440 VTX_WORD1_GPR, VTX_WORD0_eg {
1444 let FETCH_WHOLE_QUAD = 0;
1448 let USE_CONST_FIELDS = 0;
1449 let NUM_FORMAT_ALL = 2;
1450 let FORMAT_COMP_ALL = 1;
1451 let SRF_MODE_ALL = 1;
1452 let MEGA_FETCH_COUNT = 16;
1457 let DATA_FORMAT = 35;
1459 let Inst{31-0} = Word0;
1460 let Inst{63-32} = Word1;
1462 // LLVM can only encode 64-bit instructions, so these fields are manually
1463 // encoded in R600CodeEmitter
1466 // bits<2> ENDIAN_SWAP = 0;
1467 // bits<1> CONST_BUF_NO_STRIDE = 0;
1468 // bits<1> MEGA_FETCH = 0;
1469 // bits<1> ALT_CONST = 0;
1470 // bits<2> BUFFER_INDEX_MODE = 0;
1474 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1475 // is done in R600CodeEmitter
1477 // Inst{79-64} = OFFSET;
1478 // Inst{81-80} = ENDIAN_SWAP;
1479 // Inst{82} = CONST_BUF_NO_STRIDE;
1480 // Inst{83} = MEGA_FETCH;
1481 // Inst{84} = ALT_CONST;
1482 // Inst{86-85} = BUFFER_INDEX_MODE;
1483 // Inst{95-86} = 0; Reserved
1485 // VTX_WORD3 (Padding)
1487 // Inst{127-96} = 0;
1492 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst, $ptr">,
1493 VTX_WORD1_GPR, VTX_WORD0_eg {
1497 let FETCH_WHOLE_QUAD = 0;
1501 let USE_CONST_FIELDS = 1;
1502 let NUM_FORMAT_ALL = 0;
1503 let FORMAT_COMP_ALL = 0;
1504 let SRF_MODE_ALL = 1;
1505 let MEGA_FETCH_COUNT = 16;
1510 let DATA_FORMAT = 0;
1512 let Inst{31-0} = Word0;
1513 let Inst{63-32} = Word1;
1515 // LLVM can only encode 64-bit instructions, so these fields are manually
1516 // encoded in R600CodeEmitter
1519 // bits<2> ENDIAN_SWAP = 0;
1520 // bits<1> CONST_BUF_NO_STRIDE = 0;
1521 // bits<1> MEGA_FETCH = 0;
1522 // bits<1> ALT_CONST = 0;
1523 // bits<2> BUFFER_INDEX_MODE = 0;
1527 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1528 // is done in R600CodeEmitter
1530 // Inst{79-64} = OFFSET;
1531 // Inst{81-80} = ENDIAN_SWAP;
1532 // Inst{82} = CONST_BUF_NO_STRIDE;
1533 // Inst{83} = MEGA_FETCH;
1534 // Inst{84} = ALT_CONST;
1535 // Inst{86-85} = BUFFER_INDEX_MODE;
1536 // Inst{95-86} = 0; Reserved
1538 // VTX_WORD3 (Padding)
1540 // Inst{127-96} = 0;
1544 //===---------------------------------------------------------------------===//
1545 // Flow and Program control Instructions
1546 //===---------------------------------------------------------------------===//
1547 class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
1550 let Namespace = "AMDGPU";
1551 dag OutOperandList = outs;
1552 dag InOperandList = ins;
1553 let Pattern = pattern;
1554 let AsmString = !strconcat(asmstr, "\n");
1556 let Itinerary = NullALU;
1557 bit hasIEEEFlag = 0;
1558 bit hasZeroOpFlag = 0;
1561 let hasSideEffects = 0;
1562 let isCodeGenOnly = 1;
1565 multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {
1566 def _i32 : ILFormat<(outs),
1567 (ins brtarget:$target, rci:$src0),
1568 "; i32 Pseudo branch instruction",
1569 [(Op bb:$target, (i32 rci:$src0))]>;
1570 def _f32 : ILFormat<(outs),
1571 (ins brtarget:$target, rcf:$src0),
1572 "; f32 Pseudo branch instruction",
1573 [(Op bb:$target, (f32 rcf:$src0))]>;
1576 // Only scalar types should generate flow control
1577 multiclass BranchInstr<string name> {
1578 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src),
1579 !strconcat(name, " $src"), []>;
1580 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src),
1581 !strconcat(name, " $src"), []>;
1583 // Only scalar types should generate flow control
1584 multiclass BranchInstr2<string name> {
1585 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1586 !strconcat(name, " $src0, $src1"), []>;
1587 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1588 !strconcat(name, " $src0, $src1"), []>;
1591 //===---------------------------------------------------------------------===//
1592 // Custom Inserter for Branches and returns, this eventually will be a
1594 //===---------------------------------------------------------------------===//
1595 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
1596 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
1597 "; Pseudo unconditional branch instruction",
1599 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>;
1602 //===---------------------------------------------------------------------===//
1603 // Return instruction
1604 //===---------------------------------------------------------------------===//
1605 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1606 usesCustomInserter = 1 in {
1607 def RETURN : ILFormat<(outs), (ins variable_ops),
1608 "RETURN", [(AMDGPUendpgm)]
1612 //===----------------------------------------------------------------------===//
1613 // Branch Instructions
1614 //===----------------------------------------------------------------------===//
1616 def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src),
1617 "IF_PREDICATE_SET $src", []>;
1619 let isTerminator=1 in {
1620 def BREAK : ILFormat< (outs), (ins),
1622 def CONTINUE : ILFormat< (outs), (ins),
1624 def DEFAULT : ILFormat< (outs), (ins),
1626 def ELSE : ILFormat< (outs), (ins),
1628 def ENDSWITCH : ILFormat< (outs), (ins),
1630 def ENDMAIN : ILFormat< (outs), (ins),
1632 def END : ILFormat< (outs), (ins),
1634 def ENDFUNC : ILFormat< (outs), (ins),
1636 def ENDIF : ILFormat< (outs), (ins),
1638 def WHILELOOP : ILFormat< (outs), (ins),
1640 def ENDLOOP : ILFormat< (outs), (ins),
1642 def FUNC : ILFormat< (outs), (ins),
1644 def RETDYN : ILFormat< (outs), (ins),
1646 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1647 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
1648 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1649 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
1650 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1651 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
1652 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1653 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
1654 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1655 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
1656 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1657 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
1658 defm IFC : BranchInstr2<"IFC">;
1659 defm BREAKC : BranchInstr2<"BREAKC">;
1660 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
1663 //===----------------------------------------------------------------------===//
1664 // Indirect addressing pseudo instructions
1665 //===----------------------------------------------------------------------===//
1667 let isPseudo = 1 in {
1669 class ExtractVertical <RegisterClass vec_rc> : InstR600 <
1670 (outs R600_Reg32:$dst),
1671 (ins vec_rc:$vec, R600_Reg32:$index), "",
1676 let Constraints = "$dst = $vec" in {
1678 class InsertVertical <RegisterClass vec_rc> : InstR600 <
1680 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "",
1685 } // End Constraints = "$dst = $vec"
1687 } // End isPseudo = 1
1689 def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>;
1690 def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>;
1692 def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>;
1693 def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>;
1695 class ExtractVerticalPat <Instruction inst, ValueType vec_ty,
1696 ValueType scalar_ty> : R600Pat <
1697 (scalar_ty (extractelt vec_ty:$vec, i32:$index)),
1701 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>;
1702 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>;
1703 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>;
1704 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>;
1706 class InsertVerticalPat <Instruction inst, ValueType vec_ty,
1707 ValueType scalar_ty> : R600Pat <
1708 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)),
1709 (inst $vec, $value, $index)
1712 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>;
1713 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>;
1714 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>;
1715 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>;
1717 //===----------------------------------------------------------------------===//
1719 //===----------------------------------------------------------------------===//
1721 let SubtargetPredicate = isR600toCayman in {
1723 // CND*_INT Patterns for f32 True / False values
1725 class CND_INT_f32 <InstR600 cnd, CondCode cc> : R600Pat <
1726 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
1727 (cnd $src0, $src1, $src2)
1730 def : CND_INT_f32 <CNDE_INT, SETEQ>;
1731 def : CND_INT_f32 <CNDGT_INT, SETGT>;
1732 def : CND_INT_f32 <CNDGE_INT, SETGE>;
1734 //CNDGE_INT extra pattern
1736 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT),
1737 (CNDGE_INT $src0, $src1, $src2)
1741 def KILP : R600Pat <
1743 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1747 (int_AMDGPU_kill f32:$src0),
1748 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
1751 def : Extract_Element <f32, v4f32, 0, sub0>;
1752 def : Extract_Element <f32, v4f32, 1, sub1>;
1753 def : Extract_Element <f32, v4f32, 2, sub2>;
1754 def : Extract_Element <f32, v4f32, 3, sub3>;
1756 def : Insert_Element <f32, v4f32, 0, sub0>;
1757 def : Insert_Element <f32, v4f32, 1, sub1>;
1758 def : Insert_Element <f32, v4f32, 2, sub2>;
1759 def : Insert_Element <f32, v4f32, 3, sub3>;
1761 def : Extract_Element <i32, v4i32, 0, sub0>;
1762 def : Extract_Element <i32, v4i32, 1, sub1>;
1763 def : Extract_Element <i32, v4i32, 2, sub2>;
1764 def : Extract_Element <i32, v4i32, 3, sub3>;
1766 def : Insert_Element <i32, v4i32, 0, sub0>;
1767 def : Insert_Element <i32, v4i32, 1, sub1>;
1768 def : Insert_Element <i32, v4i32, 2, sub2>;
1769 def : Insert_Element <i32, v4i32, 3, sub3>;
1771 def : Extract_Element <f32, v2f32, 0, sub0>;
1772 def : Extract_Element <f32, v2f32, 1, sub1>;
1774 def : Insert_Element <f32, v2f32, 0, sub0>;
1775 def : Insert_Element <f32, v2f32, 1, sub1>;
1777 def : Extract_Element <i32, v2i32, 0, sub0>;
1778 def : Extract_Element <i32, v2i32, 1, sub1>;
1780 def : Insert_Element <i32, v2i32, 0, sub0>;
1781 def : Insert_Element <i32, v2i32, 1, sub1>;
1783 // bitconvert patterns
1785 def : BitConvert <i32, f32, R600_Reg32>;
1786 def : BitConvert <f32, i32, R600_Reg32>;
1787 def : BitConvert <v2f32, v2i32, R600_Reg64>;
1788 def : BitConvert <v2i32, v2f32, R600_Reg64>;
1789 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1790 def : BitConvert <v4i32, v4f32, R600_Reg128>;
1792 // DWORDADDR pattern
1793 def : DwordAddrPat <i32, R600_Reg32>;
1795 } // End SubtargetPredicate = isR600toCayman
1797 def getLDSNoRetOp : InstrMapping {
1798 let FilterClass = "R600_LDS_1A1D";
1799 let RowFields = ["BaseOp"];
1800 let ColFields = ["DisableEncoding"];
1801 let KeyCol = ["$dst"];
1802 let ValueCols = [[""""]];