1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// R600 Machine Scheduler interface
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
18 #include "llvm/CodeGen/MachineScheduler.h"
26 struct R600RegisterInfo;
28 class R600SchedStrategy final : public MachineSchedStrategy {
29 const ScheduleDAGMILive *DAG = nullptr;
30 const R600InstrInfo *TII = nullptr;
31 const R600RegisterInfo *TRI = nullptr;
32 MachineRegisterInfo *MRI = nullptr;
50 AluDiscarded, // LLVM Instructions that are going to be eliminated
54 std::vector<SUnit *> Available[IDLast], Pending[IDLast];
55 std::vector<SUnit *> AvailableAlus[AluLast];
56 std::vector<SUnit *> PhysicalRegCopy;
60 InstKind NextInstKind;
62 unsigned AluInstCount;
63 unsigned FetchInstCount;
65 int InstKindLimit[IDLast];
70 R600SchedStrategy() = default;
71 ~R600SchedStrategy() override = default;
73 void initialize(ScheduleDAGMI *dag) override;
74 SUnit *pickNode(bool &IsTopNode) override;
75 void schedNode(SUnit *SU, bool IsTopNode) override;
76 void releaseTopNode(SUnit *SU) override;
77 void releaseBottomNode(SUnit *SU) override;
80 std::vector<MachineInstr *> InstructionsGroupCandidate;
83 int getInstKind(SUnit *SU);
84 bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
85 AluKind getAluKind(SUnit *SU) const;
87 unsigned AvailablesAluCount() const;
88 SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
89 void PrepareNextSlot();
90 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
92 void AssignSlot(MachineInstr *MI, unsigned Slot);
94 SUnit* pickOther(int QID);
95 void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
98 } // end namespace llvm
100 #endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H