1 //===--------------------- R600MergeVectorRegisters.cpp -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass merges inputs of swizzeable instructions into vector sharing
12 /// common data and/or have enough undef subreg using swizzle abilities.
14 /// For instance let's consider the following pseudo code :
15 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
17 /// vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3
18 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3
21 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
23 /// vreg7<def> = INSERT_SUBREG vreg4, sub3
24 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3
26 /// This allow regalloc to reduce register pressure for vector registers and
27 /// to reduce MOV count.
28 //===----------------------------------------------------------------------===//
31 #include "AMDGPUSubtarget.h"
32 #include "R600Defines.h"
33 #include "R600InstrInfo.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/ADT/StringRef.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineDominators.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineFunctionPass.h"
41 #include "llvm/CodeGen/MachineInstr.h"
42 #include "llvm/CodeGen/MachineInstrBuilder.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineOperand.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/IR/DebugLoc.h"
47 #include "llvm/PassAnalysisSupport.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/raw_ostream.h"
57 #define DEBUG_TYPE "vec-merger"
60 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
61 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg),
62 E = MRI.def_instr_end(); It != E; ++It) {
63 return (*It).isImplicitDef();
65 if (MRI.isReserved(Reg)) {
68 llvm_unreachable("Reg without a def");
77 DenseMap<unsigned, unsigned> RegToChan;
78 std::vector<unsigned> UndefReg;
80 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
81 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE);
82 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
83 MachineOperand &MO = Instr->getOperand(i);
84 unsigned Chan = Instr->getOperand(i + 1).getImm();
85 if (isImplicitlyDef(MRI, MO.getReg()))
86 UndefReg.push_back(Chan);
88 RegToChan[MO.getReg()] = Chan;
92 RegSeqInfo() = default;
94 bool operator==(const RegSeqInfo &RSI) const {
95 return RSI.Instr == Instr;
99 class R600VectorRegMerger : public MachineFunctionPass {
101 MachineRegisterInfo *MRI;
102 const R600InstrInfo *TII;
104 bool canSwizzle(const MachineInstr &MI) const;
105 bool areAllUsesSwizzeable(unsigned Reg) const;
106 void SwizzleInput(MachineInstr &,
107 const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
108 bool tryMergeVector(const RegSeqInfo *Untouched, RegSeqInfo *ToMerge,
109 std::vector<std::pair<unsigned, unsigned>> &Remap) const;
110 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
111 std::vector<std::pair<unsigned, unsigned>> &RemapChan);
112 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
113 std::vector<std::pair<unsigned, unsigned>> &RemapChan);
114 MachineInstr *RebuildVector(RegSeqInfo *MI, const RegSeqInfo *BaseVec,
115 const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
116 void RemoveMI(MachineInstr *);
117 void trackRSI(const RegSeqInfo &RSI);
119 typedef DenseMap<unsigned, std::vector<MachineInstr *>> InstructionSetMap;
120 DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq;
121 InstructionSetMap PreviousRegSeqByReg;
122 InstructionSetMap PreviousRegSeqByUndefCount;
127 R600VectorRegMerger() : MachineFunctionPass(ID),
130 void getAnalysisUsage(AnalysisUsage &AU) const override {
131 AU.setPreservesCFG();
132 AU.addRequired<MachineDominatorTree>();
133 AU.addPreserved<MachineDominatorTree>();
134 AU.addRequired<MachineLoopInfo>();
135 AU.addPreserved<MachineLoopInfo>();
136 MachineFunctionPass::getAnalysisUsage(AU);
139 StringRef getPassName() const override {
140 return "R600 Vector Registers Merge Pass";
143 bool runOnMachineFunction(MachineFunction &Fn) override;
146 } // end anonymous namespace.
148 char R600VectorRegMerger::ID = 0;
150 bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI)
152 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
154 switch (MI.getOpcode()) {
155 case AMDGPU::R600_ExportSwz:
156 case AMDGPU::EG_ExportSwz:
163 bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
164 RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap)
166 unsigned CurrentUndexIdx = 0;
167 for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(),
168 E = ToMerge->RegToChan.end(); It != E; ++It) {
169 DenseMap<unsigned, unsigned>::const_iterator PosInUntouched =
170 Untouched->RegToChan.find((*It).first);
171 if (PosInUntouched != Untouched->RegToChan.end()) {
172 Remap.push_back(std::pair<unsigned, unsigned>
173 ((*It).second, (*PosInUntouched).second));
176 if (CurrentUndexIdx >= Untouched->UndefReg.size())
178 Remap.push_back(std::pair<unsigned, unsigned>
179 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
186 unsigned getReassignedChan(
187 const std::vector<std::pair<unsigned, unsigned>> &RemapChan,
189 for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
190 if (RemapChan[j].first == Chan)
191 return RemapChan[j].second;
193 llvm_unreachable("Chan wasn't reassigned");
196 MachineInstr *R600VectorRegMerger::RebuildVector(
197 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
198 const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
199 unsigned Reg = RSI->Instr->getOperand(0).getReg();
200 MachineBasicBlock::iterator Pos = RSI->Instr;
201 MachineBasicBlock &MBB = *Pos->getParent();
202 DebugLoc DL = Pos->getDebugLoc();
204 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg();
205 DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan;
206 std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
207 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
208 E = RSI->RegToChan.end(); It != E; ++It) {
209 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
210 unsigned SubReg = (*It).first;
211 unsigned Swizzle = (*It).second;
212 unsigned Chan = getReassignedChan(RemapChan, Swizzle);
214 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
219 UpdatedRegToChan[SubReg] = Chan;
220 std::vector<unsigned>::iterator ChanPos = llvm::find(UpdatedUndef, Chan);
221 if (ChanPos != UpdatedUndef.end())
222 UpdatedUndef.erase(ChanPos);
223 assert(!is_contained(UpdatedUndef, Chan) &&
224 "UpdatedUndef shouldn't contain Chan more than once!");
225 DEBUG(dbgs() << " ->"; Tmp->dump(););
229 MachineInstr *NewMI =
230 BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg).addReg(SrcVec);
231 DEBUG(dbgs() << " ->"; NewMI->dump(););
233 DEBUG(dbgs() << " Updating Swizzle:\n");
234 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
235 E = MRI->use_instr_end(); It != E; ++It) {
236 DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->");
237 SwizzleInput(*It, RemapChan);
240 RSI->Instr->eraseFromParent();
244 RSI->RegToChan = UpdatedRegToChan;
245 RSI->UndefReg = UpdatedUndef;
250 void R600VectorRegMerger::RemoveMI(MachineInstr *MI) {
251 for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(),
252 E = PreviousRegSeqByReg.end(); It != E; ++It) {
253 std::vector<MachineInstr *> &MIs = (*It).second;
254 MIs.erase(llvm::find(MIs, MI), MIs.end());
256 for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(),
257 E = PreviousRegSeqByUndefCount.end(); It != E; ++It) {
258 std::vector<MachineInstr *> &MIs = (*It).second;
259 MIs.erase(llvm::find(MIs, MI), MIs.end());
263 void R600VectorRegMerger::SwizzleInput(MachineInstr &MI,
264 const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
266 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
270 for (unsigned i = 0; i < 4; i++) {
271 unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
272 for (unsigned j = 0, e = RemapChan.size(); j < e; j++) {
273 if (RemapChan[j].first == Swizzle) {
274 MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
281 bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const {
282 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
283 E = MRI->use_instr_end(); It != E; ++It) {
284 if (!canSwizzle(*It))
290 bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI,
291 RegSeqInfo &CompatibleRSI,
292 std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
293 for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(),
294 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) {
297 if (PreviousRegSeqByReg[MOp->getReg()].empty())
299 for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) {
300 CompatibleRSI = PreviousRegSeq[MI];
301 if (RSI == CompatibleRSI)
303 if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan))
310 bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
311 RegSeqInfo &CompatibleRSI,
312 std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
313 unsigned NeededUndefs = 4 - RSI.UndefReg.size();
314 if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
316 std::vector<MachineInstr *> &MIs =
317 PreviousRegSeqByUndefCount[NeededUndefs];
318 CompatibleRSI = PreviousRegSeq[MIs.back()];
319 tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
323 void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
324 for (DenseMap<unsigned, unsigned>::const_iterator
325 It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) {
326 PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
328 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
329 PreviousRegSeq[RSI.Instr] = RSI;
332 bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
333 if (skipFunction(*Fn.getFunction()))
336 const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>();
337 TII = ST.getInstrInfo();
338 MRI = &Fn.getRegInfo();
340 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
341 MBB != MBBe; ++MBB) {
342 MachineBasicBlock *MB = &*MBB;
343 PreviousRegSeq.clear();
344 PreviousRegSeqByReg.clear();
345 PreviousRegSeqByUndefCount.clear();
347 for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
348 MII != MIIE; ++MII) {
349 MachineInstr &MI = *MII;
350 if (MI.getOpcode() != AMDGPU::REG_SEQUENCE) {
351 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
352 unsigned Reg = MI.getOperand(1).getReg();
353 for (MachineRegisterInfo::def_instr_iterator
354 It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end();
362 RegSeqInfo RSI(*MRI, &MI);
364 // All uses of MI are swizzeable ?
365 unsigned Reg = MI.getOperand(0).getReg();
366 if (!areAllUsesSwizzeable(Reg))
370 dbgs() << "Trying to optimize ";
374 RegSeqInfo CandidateRSI;
375 std::vector<std::pair<unsigned, unsigned>> RemapChan;
376 DEBUG(dbgs() << "Using common slots...\n";);
377 if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) {
378 // Remove CandidateRSI mapping
379 RemoveMI(CandidateRSI.Instr);
380 MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
384 DEBUG(dbgs() << "Using free slots...\n";);
386 if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) {
387 RemoveMI(CandidateRSI.Instr);
388 MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
399 llvm::FunctionPass *llvm::createR600VectorRegMerger() {
400 return new R600VectorRegMerger();