1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "R600RegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "R600Defines.h"
18 #include "R600InstrInfo.h"
19 #include "R600MachineFunctionInfo.h"
23 R600RegisterInfo::R600RegisterInfo() : AMDGPURegisterInfo() {
28 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
29 BitVector Reserved(getNumRegs());
31 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
32 const R600InstrInfo *TII = ST.getInstrInfo();
34 Reserved.set(AMDGPU::ZERO);
35 Reserved.set(AMDGPU::HALF);
36 Reserved.set(AMDGPU::ONE);
37 Reserved.set(AMDGPU::ONE_INT);
38 Reserved.set(AMDGPU::NEG_HALF);
39 Reserved.set(AMDGPU::NEG_ONE);
40 Reserved.set(AMDGPU::PV_X);
41 Reserved.set(AMDGPU::ALU_LITERAL_X);
42 Reserved.set(AMDGPU::ALU_CONST);
43 Reserved.set(AMDGPU::PREDICATE_BIT);
44 Reserved.set(AMDGPU::PRED_SEL_OFF);
45 Reserved.set(AMDGPU::PRED_SEL_ZERO);
46 Reserved.set(AMDGPU::PRED_SEL_ONE);
47 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
49 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
50 E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
54 TII->reserveIndirectRegisters(Reserved, MF);
59 // Dummy to not crash RegisterClassInfo.
60 static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
62 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
63 const MachineFunction *) const {
64 return &CalleeSavedReg;
67 unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
68 return AMDGPU::NoRegister;
71 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
72 return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
75 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
76 return GET_REG_INDEX(getEncodingValue(Reg));
79 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
83 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
87 const RegClassWeight &R600RegisterInfo::getRegClassWeight(
88 const TargetRegisterClass *RC) const {
92 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
93 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
105 void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
107 unsigned FIOperandNum,
108 RegScavenger *RS) const {
109 llvm_unreachable("Subroutines not supported yet");