1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCInstrDesc.h"
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
21 // Low bits - basic encoding information.
25 // SALU instruction formats.
32 // VALU instruction formats.
37 // TODO: Should this be spilt into VOP3 a and b?
45 // Memory instruction formats.
54 // Pseudo instruction formats.
58 // High bits - other information.
59 VM_CNT = UINT64_C(1) << 32,
60 EXP_CNT = UINT64_C(1) << 33,
61 LGKM_CNT = UINT64_C(1) << 34,
63 WQM = UINT64_C(1) << 35,
64 DisableWQM = UINT64_C(1) << 36,
65 Gather4 = UINT64_C(1) << 37,
66 SOPK_ZEXT = UINT64_C(1) << 38,
67 SCALAR_STORE = UINT64_C(1) << 39,
68 FIXED_SIZE = UINT64_C(1) << 40,
69 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
70 VOP3_OPSEL = UINT64_C(1) << 42,
71 maybeAtomic = UINT64_C(1) << 43,
72 renamedInGFX9 = UINT64_C(1) << 44,
74 // Is a clamp on FP type.
75 FPClamp = UINT64_C(1) << 45,
77 // Is an integer clamp
78 IntClamp = UINT64_C(1) << 46,
80 // Clamps lo component of register.
81 ClampLo = UINT64_C(1) << 47,
83 // Clamps hi component of register.
84 // ClampLo and ClampHi set for packed clamp.
85 ClampHi = UINT64_C(1) << 48,
87 // Is a packed VOP3P instruction.
88 IsPacked = UINT64_C(1) << 49,
90 // Is a D16 buffer instruction.
91 D16Buf = UINT64_C(1) << 50,
93 // Uses floating point double precision rounding mode
94 FPDPRounding = UINT64_C(1) << 51
97 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
98 // The result is true if any of these tests are true.
100 S_NAN = 1 << 0, // Signaling NaN
101 Q_NAN = 1 << 1, // Quiet NaN
102 N_INFINITY = 1 << 2, // Negative infinity
103 N_NORMAL = 1 << 3, // Negative normal
104 N_SUBNORMAL = 1 << 4, // Negative subnormal
105 N_ZERO = 1 << 5, // Negative zero
106 P_ZERO = 1 << 6, // Positive zero
107 P_SUBNORMAL = 1 << 7, // Positive subnormal
108 P_NORMAL = 1 << 8, // Positive normal
109 P_INFINITY = 1 << 9 // Positive infinity
115 /// Operands with register or 32-bit immediate
116 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
117 OPERAND_REG_IMM_INT64,
118 OPERAND_REG_IMM_INT16,
119 OPERAND_REG_IMM_FP32,
120 OPERAND_REG_IMM_FP64,
121 OPERAND_REG_IMM_FP16,
123 /// Operands with register or inline constant
124 OPERAND_REG_INLINE_C_INT16,
125 OPERAND_REG_INLINE_C_INT32,
126 OPERAND_REG_INLINE_C_INT64,
127 OPERAND_REG_INLINE_C_FP16,
128 OPERAND_REG_INLINE_C_FP32,
129 OPERAND_REG_INLINE_C_FP64,
130 OPERAND_REG_INLINE_C_V2FP16,
131 OPERAND_REG_INLINE_C_V2INT16,
133 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
134 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
136 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
137 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16,
139 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
140 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
142 // Operand for source modifiers for VOP instructions
145 // Operand for SDWA instructions
146 OPERAND_SDWA_VOPC_DST,
148 /// Operand with 32-bit immediate that uses the constant bus.
154 namespace SIStackID {
155 enum StackTypes : uint8_t {
161 // Input operand modifiers bit-masks
162 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
163 namespace SISrcMods {
165 NEG = 1 << 0, // Floating-point negate modifier
166 ABS = 1 << 1, // Floating-point absolute modifier
167 SEXT = 1 << 0, // Integer sign-extend modifier
168 NEG_HI = ABS, // Floating-point negate high packed component modifier.
171 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
175 namespace SIOutMods {
184 namespace VGPRIndexMode {
186 SRC0_ENABLE = 1 << 0,
187 SRC1_ENABLE = 1 << 1,
188 SRC2_ENABLE = 1 << 2,
193 namespace AMDGPUAsmVariants {
204 namespace EncValues { // Encoding values of enum9/8/7 operands
213 INLINE_INTEGER_C_MIN = 128,
214 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
215 INLINE_INTEGER_C_MAX = 208,
216 INLINE_FLOATING_C_MIN = 240,
217 INLINE_FLOATING_C_MAX = 248,
223 } // namespace EncValues
224 } // namespace AMDGPU
227 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
229 enum Id { // Message ID, width(4) [3:0].
235 ID_GAPS_LAST_, // Indicate that sequence has gaps.
236 ID_GAPS_FIRST_ = ID_INTERRUPT,
239 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
242 enum Op { // Both GS and SYS operation IDs.
251 OP_GS_FIRST_ = OP_GS_NOP,
253 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
255 OP_SYS_ECC_ERR_INTERRUPT = 1,
257 OP_SYS_HOST_TRAP_ACK,
260 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
262 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
265 enum StreamId { // Stream ID, (2) [9:8].
266 STREAM_ID_DEFAULT_ = 0,
268 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
269 STREAM_ID_SHIFT_ = 8,
271 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
274 } // namespace SendMsg
276 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
278 enum Id { // HwRegCode, (6) [5:0]
280 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
289 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
290 ID_SYMBOLIC_LAST_ = 16,
293 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
296 enum Offset { // Offset, (5) [10:6]
300 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
302 OFFSET_SRC_SHARED_BASE = 16,
303 OFFSET_SRC_PRIVATE_BASE = 0
306 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
307 WIDTH_M1_DEFAULT_ = 31,
308 WIDTH_M1_SHIFT_ = 11,
310 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
312 WIDTH_M1_SRC_SHARED_BASE = 15,
313 WIDTH_M1_SRC_PRIVATE_BASE = 15
318 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
320 enum Id { // id of symbolic names
330 // swizzle mode encodings
332 QUAD_PERM_ENC = 0x8000,
333 QUAD_PERM_ENC_MASK = 0xFF00,
335 BITMASK_PERM_ENC = 0x0000,
336 BITMASK_PERM_ENC_MASK = 0x8000,
338 // QUAD_PERM encodings
341 LANE_MAX = LANE_MASK,
345 // BITMASK_PERM encodings
348 BITMASK_MAX = BITMASK_MASK,
351 BITMASK_AND_SHIFT = 0,
352 BITMASK_OR_SHIFT = 5,
353 BITMASK_XOR_SHIFT = 10
356 } // namespace Swizzle
377 SRC_SGPR_MASK = 0x100,
378 SRC_VGPR_MASK = 0xFF,
379 VOPC_DST_VCC_MASK = 0x80,
380 VOPC_DST_SGPR_MASK = 0x7F,
396 QUAD_PERM_LAST = 0xFF,
399 ROW_SHL_FIRST = 0x101,
400 ROW_SHL_LAST = 0x10F,
403 ROW_SHR_FIRST = 0x111,
404 ROW_SHR_LAST = 0x11F,
407 ROW_ROR_FIRST = 0x121,
408 ROW_ROR_LAST = 0x12F,
410 DPP_UNUSED4_FIRST = 0x131,
411 DPP_UNUSED4_LAST = 0x133,
413 DPP_UNUSED5_FIRST = 0x135,
414 DPP_UNUSED5_LAST = 0x137,
416 DPP_UNUSED6_FIRST = 0x139,
417 DPP_UNUSED6_LAST = 0x13B,
419 DPP_UNUSED7_FIRST = 0x13D,
420 DPP_UNUSED7_LAST = 0x13F,
422 ROW_HALF_MIRROR = 0x141,
429 } // namespace AMDGPU
431 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
432 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
433 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
434 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
435 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
436 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
437 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
438 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
439 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
440 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
441 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
443 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
444 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
445 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
446 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
447 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
448 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
449 #define C_00B84C_USER_SGPR 0xFFFFFFC1
450 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
451 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
452 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
453 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
454 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
455 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
456 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
457 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
458 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
459 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
460 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
461 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
462 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
463 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
464 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
465 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
466 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
467 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
469 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
470 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
471 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
473 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
474 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
475 #define C_00B84C_LDS_SIZE 0xFF007FFF
476 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
477 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
478 #define C_00B84C_EXCP_EN
480 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
481 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
483 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
484 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
485 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
486 #define C_00B848_VGPRS 0xFFFFFFC0
487 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
488 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
489 #define C_00B848_SGPRS 0xFFFFFC3F
490 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
491 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
492 #define C_00B848_PRIORITY 0xFFFFF3FF
493 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
494 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
495 #define C_00B848_FLOAT_MODE 0xFFF00FFF
496 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
497 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
498 #define C_00B848_PRIV 0xFFEFFFFF
499 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
500 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
501 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
502 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
503 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
504 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
505 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
506 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
507 #define C_00B848_IEEE_MODE 0xFF7FFFFF
510 // Helpers for setting FLOAT_MODE
511 #define FP_ROUND_ROUND_TO_NEAREST 0
512 #define FP_ROUND_ROUND_TO_INF 1
513 #define FP_ROUND_ROUND_TO_NEGINF 2
514 #define FP_ROUND_ROUND_TO_ZERO 3
516 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
518 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
519 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
521 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
522 #define FP_DENORM_FLUSH_OUT 1
523 #define FP_DENORM_FLUSH_IN 2
524 #define FP_DENORM_FLUSH_NONE 3
527 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
529 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
530 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
532 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
533 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
535 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
536 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
538 #define R_SPILLED_SGPRS 0x4
539 #define R_SPILLED_VGPRS 0x8
540 } // End namespace llvm