1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCInstrDesc.h"
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
16 namespace SIInstrFlags {
17 // This needs to be kept in sync with the field bits in InstSI.
43 VOPAsmPrefer32Bit = 1 << 24,
52 /// Operand with register or 32-bit immediate
53 OPERAND_REG_IMM32 = MCOI::OPERAND_FIRST_TARGET,
54 /// Operand with register or inline constant
57 /// Operand with 32-bit immediate that uses the constant bus. The standard
58 /// OPERAND_IMMEDIATE should be used for special immediates such as source
65 namespace SIInstrFlags {
67 // First 4 bits are the instruction encoding
73 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
74 // The result is true if any of these tests are true.
76 S_NAN = 1 << 0, // Signaling NaN
77 Q_NAN = 1 << 1, // Quiet NaN
78 N_INFINITY = 1 << 2, // Negative infinity
79 N_NORMAL = 1 << 3, // Negative normal
80 N_SUBNORMAL = 1 << 4, // Negative subnormal
81 N_ZERO = 1 << 5, // Negative zero
82 P_ZERO = 1 << 6, // Positive zero
83 P_SUBNORMAL = 1 << 7, // Positive subnormal
84 P_NORMAL = 1 << 8, // Positive normal
85 P_INFINITY = 1 << 9 // Positive infinity
89 // Input operand modifiers bit-masks
90 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
93 NEG = 1 << 0, // Floating-point negate modifier
94 ABS = 1 << 1, // Floating-point absolute modifier
95 SEXT = 1 << 0 // Integer sign-extend modifier
110 namespace EncValues { // Encoding values of enum9/8/7 operands
117 INLINE_INTEGER_C_MIN = 128,
118 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
119 INLINE_INTEGER_C_MAX = 208,
120 INLINE_FLOATING_C_MIN = 240,
121 INLINE_FLOATING_C_MAX = 248,
127 } // namespace EncValues
128 } // namespace AMDGPU
133 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
135 enum Id { // Message ID, width(4) [3:0].
141 ID_GAPS_LAST_, // Indicate that sequence has gaps.
142 ID_GAPS_FIRST_ = ID_INTERRUPT,
145 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
148 enum Op { // Both GS and SYS operation IDs.
157 OP_GS_FIRST_ = OP_GS_NOP,
159 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
161 OP_SYS_ECC_ERR_INTERRUPT = 1,
163 OP_SYS_HOST_TRAP_ACK,
166 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
168 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
171 enum StreamId { // Stream ID, (2) [9:8].
172 STREAM_ID_DEFAULT_ = 0,
174 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
175 STREAM_ID_SHIFT_ = 8,
177 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
180 } // namespace SendMsg
182 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
184 enum Id { // HwRegCode, (6) [5:0]
186 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
187 ID_SYMBOLIC_LAST_ = 8,
190 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
193 enum Offset { // Offset, (5) [10:6]
197 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_)
200 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
201 WIDTH_M1_DEFAULT_ = 31,
202 WIDTH_M1_SHIFT_ = 11,
204 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_)
208 } // namespace AMDGPU
211 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
212 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
213 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
214 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
215 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
216 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
217 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
218 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
220 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
221 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
222 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
223 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
224 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
225 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
226 #define C_00B84C_USER_SGPR 0xFFFFFFC1
227 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
228 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
229 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
230 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
231 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
232 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
233 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
234 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
235 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
236 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
237 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
238 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
239 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
240 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
241 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
243 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
244 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
245 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
247 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
248 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
249 #define C_00B84C_LDS_SIZE 0xFF007FFF
250 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
251 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
252 #define C_00B84C_EXCP_EN
254 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
255 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
257 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
258 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
259 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
260 #define C_00B848_VGPRS 0xFFFFFFC0
261 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
262 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
263 #define C_00B848_SGPRS 0xFFFFFC3F
264 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
265 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
266 #define C_00B848_PRIORITY 0xFFFFF3FF
267 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
268 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
269 #define C_00B848_FLOAT_MODE 0xFFF00FFF
270 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
271 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
272 #define C_00B848_PRIV 0xFFEFFFFF
273 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
274 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
275 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
276 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
277 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
278 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
279 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
280 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
281 #define C_00B848_IEEE_MODE 0xFF7FFFFF
284 // Helpers for setting FLOAT_MODE
285 #define FP_ROUND_ROUND_TO_NEAREST 0
286 #define FP_ROUND_ROUND_TO_INF 1
287 #define FP_ROUND_ROUND_TO_NEGINF 2
288 #define FP_ROUND_ROUND_TO_ZERO 3
290 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
292 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
293 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
295 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
296 #define FP_DENORM_FLUSH_OUT 1
297 #define FP_DENORM_FLUSH_IN 2
298 #define FP_DENORM_FLUSH_NONE 3
301 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
303 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
304 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
306 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
307 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
309 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
310 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
312 #define R_SPILLED_SGPRS 0x4
313 #define R_SPILLED_VGPRS 0x8