1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCInstrDesc.h"
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
21 // Low bits - basic encoding information.
25 // SALU instruction formats.
32 // VALU instruction formats.
37 // TODO: Should this be spilt into VOP3 a and b?
45 // Memory instruction formats.
54 // Pseudo instruction formats.
58 // High bits - other information.
59 VM_CNT = UINT64_C(1) << 32,
60 EXP_CNT = UINT64_C(1) << 33,
61 LGKM_CNT = UINT64_C(1) << 34,
63 WQM = UINT64_C(1) << 35,
64 DisableWQM = UINT64_C(1) << 36,
65 Gather4 = UINT64_C(1) << 37,
66 SOPK_ZEXT = UINT64_C(1) << 38,
67 SCALAR_STORE = UINT64_C(1) << 39,
68 FIXED_SIZE = UINT64_C(1) << 40,
69 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
70 VOP3_OPSEL = UINT64_C(1) << 42,
71 maybeAtomic = UINT64_C(1) << 43,
72 renamedInGFX9 = UINT64_C(1) << 44,
74 // Is a clamp on FP type.
75 FPClamp = UINT64_C(1) << 45,
77 // Is an integer clamp
78 IntClamp = UINT64_C(1) << 46,
80 // Clamps lo component of register.
81 ClampLo = UINT64_C(1) << 47,
83 // Clamps hi component of register.
84 // ClampLo and ClampHi set for packed clamp.
85 ClampHi = UINT64_C(1) << 48,
87 // Is a packed VOP3P instruction.
88 IsPacked = UINT64_C(1) << 49
91 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
92 // The result is true if any of these tests are true.
94 S_NAN = 1 << 0, // Signaling NaN
95 Q_NAN = 1 << 1, // Quiet NaN
96 N_INFINITY = 1 << 2, // Negative infinity
97 N_NORMAL = 1 << 3, // Negative normal
98 N_SUBNORMAL = 1 << 4, // Negative subnormal
99 N_ZERO = 1 << 5, // Negative zero
100 P_ZERO = 1 << 6, // Positive zero
101 P_SUBNORMAL = 1 << 7, // Positive subnormal
102 P_NORMAL = 1 << 8, // Positive normal
103 P_INFINITY = 1 << 9 // Positive infinity
109 /// Operands with register or 32-bit immediate
110 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
111 OPERAND_REG_IMM_INT64,
112 OPERAND_REG_IMM_INT16,
113 OPERAND_REG_IMM_FP32,
114 OPERAND_REG_IMM_FP64,
115 OPERAND_REG_IMM_FP16,
117 /// Operands with register or inline constant
118 OPERAND_REG_INLINE_C_INT16,
119 OPERAND_REG_INLINE_C_INT32,
120 OPERAND_REG_INLINE_C_INT64,
121 OPERAND_REG_INLINE_C_FP16,
122 OPERAND_REG_INLINE_C_FP32,
123 OPERAND_REG_INLINE_C_FP64,
124 OPERAND_REG_INLINE_C_V2FP16,
125 OPERAND_REG_INLINE_C_V2INT16,
127 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
128 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
130 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
131 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16,
133 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
134 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
136 // Operand for source modifiers for VOP instructions
139 // Operand for SDWA instructions
141 OPERAND_SDWA_VOPC_DST,
143 /// Operand with 32-bit immediate that uses the constant bus.
149 // Input operand modifiers bit-masks
150 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
151 namespace SISrcMods {
153 NEG = 1 << 0, // Floating-point negate modifier
154 ABS = 1 << 1, // Floating-point absolute modifier
155 SEXT = 1 << 0, // Integer sign-extend modifier
156 NEG_HI = ABS, // Floating-point negate high packed component modifier.
159 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
163 namespace SIOutMods {
172 namespace VGPRIndexMode {
174 SRC0_ENABLE = 1 << 0,
175 SRC1_ENABLE = 1 << 1,
176 SRC2_ENABLE = 1 << 2,
181 namespace AMDGPUAsmVariants {
192 namespace EncValues { // Encoding values of enum9/8/7 operands
201 INLINE_INTEGER_C_MIN = 128,
202 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
203 INLINE_INTEGER_C_MAX = 208,
204 INLINE_FLOATING_C_MIN = 240,
205 INLINE_FLOATING_C_MAX = 248,
211 } // namespace EncValues
212 } // namespace AMDGPU
215 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
217 enum Id { // Message ID, width(4) [3:0].
223 ID_GAPS_LAST_, // Indicate that sequence has gaps.
224 ID_GAPS_FIRST_ = ID_INTERRUPT,
227 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
230 enum Op { // Both GS and SYS operation IDs.
239 OP_GS_FIRST_ = OP_GS_NOP,
241 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
243 OP_SYS_ECC_ERR_INTERRUPT = 1,
245 OP_SYS_HOST_TRAP_ACK,
248 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
250 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
253 enum StreamId { // Stream ID, (2) [9:8].
254 STREAM_ID_DEFAULT_ = 0,
256 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
257 STREAM_ID_SHIFT_ = 8,
259 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
262 } // namespace SendMsg
264 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
266 enum Id { // HwRegCode, (6) [5:0]
268 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
276 ID_SYMBOLIC_LAST_ = 8,
280 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
283 enum Offset { // Offset, (5) [10:6]
287 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
289 OFFSET_SRC_SHARED_BASE = 16,
290 OFFSET_SRC_PRIVATE_BASE = 0
293 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
294 WIDTH_M1_DEFAULT_ = 31,
295 WIDTH_M1_SHIFT_ = 11,
297 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
299 WIDTH_M1_SRC_SHARED_BASE = 15,
300 WIDTH_M1_SRC_PRIVATE_BASE = 15
305 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
307 enum Id { // id of symbolic names
317 // swizzle mode encodings
319 QUAD_PERM_ENC = 0x8000,
320 QUAD_PERM_ENC_MASK = 0xFF00,
322 BITMASK_PERM_ENC = 0x0000,
323 BITMASK_PERM_ENC_MASK = 0x8000,
325 // QUAD_PERM encodings
328 LANE_MAX = LANE_MASK,
332 // BITMASK_PERM encodings
335 BITMASK_MAX = BITMASK_MASK,
338 BITMASK_AND_SHIFT = 0,
339 BITMASK_OR_SHIFT = 5,
340 BITMASK_XOR_SHIFT = 10
343 } // namespace Swizzle
364 SRC_SGPR_MASK = 0x100,
365 SRC_VGPR_MASK = 0xFF,
366 VOPC_DST_VCC_MASK = 0x80,
367 VOPC_DST_SGPR_MASK = 0x7F,
378 } // namespace AMDGPU
380 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
381 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
382 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
383 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
384 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
385 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
386 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
387 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
388 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
389 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
390 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
392 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
393 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
394 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
395 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
396 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
397 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
398 #define C_00B84C_USER_SGPR 0xFFFFFFC1
399 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
400 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
401 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
402 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
403 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
404 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
405 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
406 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
407 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
408 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
409 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
410 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
411 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
412 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
413 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
414 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
415 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
416 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
418 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
419 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
420 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
422 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
423 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
424 #define C_00B84C_LDS_SIZE 0xFF007FFF
425 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
426 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
427 #define C_00B84C_EXCP_EN
429 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
430 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
432 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
433 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
434 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
435 #define C_00B848_VGPRS 0xFFFFFFC0
436 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
437 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
438 #define C_00B848_SGPRS 0xFFFFFC3F
439 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
440 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
441 #define C_00B848_PRIORITY 0xFFFFF3FF
442 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
443 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
444 #define C_00B848_FLOAT_MODE 0xFFF00FFF
445 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
446 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
447 #define C_00B848_PRIV 0xFFEFFFFF
448 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
449 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
450 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
451 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
452 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
453 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
454 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
455 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
456 #define C_00B848_IEEE_MODE 0xFF7FFFFF
459 // Helpers for setting FLOAT_MODE
460 #define FP_ROUND_ROUND_TO_NEAREST 0
461 #define FP_ROUND_ROUND_TO_INF 1
462 #define FP_ROUND_ROUND_TO_NEGINF 2
463 #define FP_ROUND_ROUND_TO_ZERO 3
465 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
467 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
468 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
470 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
471 #define FP_DENORM_FLUSH_OUT 1
472 #define FP_DENORM_FLUSH_IN 2
473 #define FP_DENORM_FLUSH_NONE 3
476 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
478 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
479 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
481 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
482 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
484 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
485 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
487 #define R_SPILLED_SGPRS 0x4
488 #define R_SPILLED_VGPRS 0x8
489 } // End namespace llvm