1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCInstrDesc.h"
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
21 // Low bits - basic encoding information.
25 // SALU instruction formats.
32 // VALU instruction formats.
37 // TODO: Should this be spilt into VOP3 a and b?
44 // Memory instruction formats.
53 // Pseudo instruction formats.
57 // High bits - other information.
58 VM_CNT = UINT64_C(1) << 32,
59 EXP_CNT = UINT64_C(1) << 33,
60 LGKM_CNT = UINT64_C(1) << 34,
62 WQM = UINT64_C(1) << 35,
63 DisableWQM = UINT64_C(1) << 36,
64 Gather4 = UINT64_C(1) << 37,
65 SOPK_ZEXT = UINT64_C(1) << 38,
66 SCALAR_STORE = UINT64_C(1) << 39,
67 FIXED_SIZE = UINT64_C(1) << 40,
68 VOPAsmPrefer32Bit = UINT64_C(1) << 41
72 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
73 // The result is true if any of these tests are true.
75 S_NAN = 1 << 0, // Signaling NaN
76 Q_NAN = 1 << 1, // Quiet NaN
77 N_INFINITY = 1 << 2, // Negative infinity
78 N_NORMAL = 1 << 3, // Negative normal
79 N_SUBNORMAL = 1 << 4, // Negative subnormal
80 N_ZERO = 1 << 5, // Negative zero
81 P_ZERO = 1 << 6, // Positive zero
82 P_SUBNORMAL = 1 << 7, // Positive subnormal
83 P_NORMAL = 1 << 8, // Positive normal
84 P_INFINITY = 1 << 9 // Positive infinity
90 /// Operands with register or 32-bit immediate
91 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
92 OPERAND_REG_IMM_INT64,
93 OPERAND_REG_IMM_INT16,
98 /// Operands with register or inline constant
99 OPERAND_REG_INLINE_C_INT16,
100 OPERAND_REG_INLINE_C_INT32,
101 OPERAND_REG_INLINE_C_INT64,
102 OPERAND_REG_INLINE_C_FP16,
103 OPERAND_REG_INLINE_C_FP32,
104 OPERAND_REG_INLINE_C_FP64,
106 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
107 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
109 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
110 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_FP64,
112 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
113 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
115 // Operand for source modifiers for VOP instructions
118 /// Operand with 32-bit immediate that uses the constant bus.
124 // Input operand modifiers bit-masks
125 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
126 namespace SISrcMods {
128 NEG = 1 << 0, // Floating-point negate modifier
129 ABS = 1 << 1, // Floating-point absolute modifier
130 SEXT = 1 << 0 // Integer sign-extend modifier
134 namespace SIOutMods {
143 namespace VGPRIndexMode {
145 SRC0_ENABLE = 1 << 0,
146 SRC1_ENABLE = 1 << 1,
147 SRC2_ENABLE = 1 << 2,
152 namespace AMDGPUAsmVariants {
162 namespace EncValues { // Encoding values of enum9/8/7 operands
169 INLINE_INTEGER_C_MIN = 128,
170 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
171 INLINE_INTEGER_C_MAX = 208,
172 INLINE_FLOATING_C_MIN = 240,
173 INLINE_FLOATING_C_MAX = 248,
179 } // namespace EncValues
180 } // namespace AMDGPU
183 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
185 enum Id { // Message ID, width(4) [3:0].
191 ID_GAPS_LAST_, // Indicate that sequence has gaps.
192 ID_GAPS_FIRST_ = ID_INTERRUPT,
195 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
198 enum Op { // Both GS and SYS operation IDs.
207 OP_GS_FIRST_ = OP_GS_NOP,
209 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
211 OP_SYS_ECC_ERR_INTERRUPT = 1,
213 OP_SYS_HOST_TRAP_ACK,
216 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
218 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
221 enum StreamId { // Stream ID, (2) [9:8].
222 STREAM_ID_DEFAULT_ = 0,
224 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
225 STREAM_ID_SHIFT_ = 8,
227 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
230 } // namespace SendMsg
232 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
234 enum Id { // HwRegCode, (6) [5:0]
236 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
244 ID_SYMBOLIC_LAST_ = 8,
247 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
250 enum Offset { // Offset, (5) [10:6]
254 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_)
257 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
258 WIDTH_M1_DEFAULT_ = 31,
259 WIDTH_M1_SHIFT_ = 11,
261 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_)
285 } // namespace AMDGPU
287 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
288 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
289 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
290 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
291 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
292 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
293 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
294 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
296 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
297 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
298 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
299 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
300 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
301 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
302 #define C_00B84C_USER_SGPR 0xFFFFFFC1
303 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
304 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
305 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
306 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
307 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
308 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
309 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
310 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
311 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
312 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
313 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
314 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
315 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
316 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
317 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
319 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
320 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
321 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
323 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
324 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
325 #define C_00B84C_LDS_SIZE 0xFF007FFF
326 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
327 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
328 #define C_00B84C_EXCP_EN
330 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
331 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
333 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
334 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
335 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
336 #define C_00B848_VGPRS 0xFFFFFFC0
337 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
338 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
339 #define C_00B848_SGPRS 0xFFFFFC3F
340 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
341 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
342 #define C_00B848_PRIORITY 0xFFFFF3FF
343 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
344 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
345 #define C_00B848_FLOAT_MODE 0xFFF00FFF
346 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
347 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
348 #define C_00B848_PRIV 0xFFEFFFFF
349 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
350 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
351 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
352 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
353 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
354 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
355 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
356 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
357 #define C_00B848_IEEE_MODE 0xFF7FFFFF
360 // Helpers for setting FLOAT_MODE
361 #define FP_ROUND_ROUND_TO_NEAREST 0
362 #define FP_ROUND_ROUND_TO_INF 1
363 #define FP_ROUND_ROUND_TO_NEGINF 2
364 #define FP_ROUND_ROUND_TO_ZERO 3
366 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
368 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
369 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
371 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
372 #define FP_DENORM_FLUSH_OUT 1
373 #define FP_DENORM_FLUSH_IN 2
374 #define FP_DENORM_FLUSH_NONE 3
377 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
379 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
380 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
382 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
383 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
385 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
386 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
388 #define R_SPILLED_SGPRS 0x4
389 #define R_SPILLED_VGPRS 0x8
391 } // End namespace llvm