1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCInstrDesc.h"
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
21 // Low bits - basic encoding information.
25 // SALU instruction formats.
32 // VALU instruction formats.
37 // TODO: Should this be spilt into VOP3 a and b?
45 // Memory instruction formats.
54 // Pseudo instruction formats.
58 // High bits - other information.
59 VM_CNT = UINT64_C(1) << 32,
60 EXP_CNT = UINT64_C(1) << 33,
61 LGKM_CNT = UINT64_C(1) << 34,
63 WQM = UINT64_C(1) << 35,
64 DisableWQM = UINT64_C(1) << 36,
65 Gather4 = UINT64_C(1) << 37,
66 SOPK_ZEXT = UINT64_C(1) << 38,
67 SCALAR_STORE = UINT64_C(1) << 39,
68 FIXED_SIZE = UINT64_C(1) << 40,
69 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
70 HasFPClamp = UINT64_C(1) << 42
73 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
74 // The result is true if any of these tests are true.
76 S_NAN = 1 << 0, // Signaling NaN
77 Q_NAN = 1 << 1, // Quiet NaN
78 N_INFINITY = 1 << 2, // Negative infinity
79 N_NORMAL = 1 << 3, // Negative normal
80 N_SUBNORMAL = 1 << 4, // Negative subnormal
81 N_ZERO = 1 << 5, // Negative zero
82 P_ZERO = 1 << 6, // Positive zero
83 P_SUBNORMAL = 1 << 7, // Positive subnormal
84 P_NORMAL = 1 << 8, // Positive normal
85 P_INFINITY = 1 << 9 // Positive infinity
91 /// Operands with register or 32-bit immediate
92 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
93 OPERAND_REG_IMM_INT64,
94 OPERAND_REG_IMM_INT16,
99 /// Operands with register or inline constant
100 OPERAND_REG_INLINE_C_INT16,
101 OPERAND_REG_INLINE_C_INT32,
102 OPERAND_REG_INLINE_C_INT64,
103 OPERAND_REG_INLINE_C_FP16,
104 OPERAND_REG_INLINE_C_FP32,
105 OPERAND_REG_INLINE_C_FP64,
106 OPERAND_REG_INLINE_C_V2FP16,
107 OPERAND_REG_INLINE_C_V2INT16,
109 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
110 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
112 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
113 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16,
115 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
116 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
118 // Operand for source modifiers for VOP instructions
121 // Operand for SDWA instructions
123 OPERAND_SDWA_VOPC_DST,
125 /// Operand with 32-bit immediate that uses the constant bus.
131 // Input operand modifiers bit-masks
132 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
133 namespace SISrcMods {
135 NEG = 1 << 0, // Floating-point negate modifier
136 ABS = 1 << 1, // Floating-point absolute modifier
137 SEXT = 1 << 0, // Integer sign-extend modifier
138 NEG_HI = ABS, // Floating-point negate high packed component modifier.
144 namespace SIOutMods {
153 namespace VGPRIndexMode {
155 SRC0_ENABLE = 1 << 0,
156 SRC1_ENABLE = 1 << 1,
157 SRC2_ENABLE = 1 << 2,
162 namespace AMDGPUAsmVariants {
173 namespace EncValues { // Encoding values of enum9/8/7 operands
180 INLINE_INTEGER_C_MIN = 128,
181 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
182 INLINE_INTEGER_C_MAX = 208,
183 INLINE_FLOATING_C_MIN = 240,
184 INLINE_FLOATING_C_MAX = 248,
190 } // namespace EncValues
191 } // namespace AMDGPU
194 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
196 enum Id { // Message ID, width(4) [3:0].
202 ID_GAPS_LAST_, // Indicate that sequence has gaps.
203 ID_GAPS_FIRST_ = ID_INTERRUPT,
206 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
209 enum Op { // Both GS and SYS operation IDs.
218 OP_GS_FIRST_ = OP_GS_NOP,
220 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
222 OP_SYS_ECC_ERR_INTERRUPT = 1,
224 OP_SYS_HOST_TRAP_ACK,
227 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
229 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
232 enum StreamId { // Stream ID, (2) [9:8].
233 STREAM_ID_DEFAULT_ = 0,
235 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
236 STREAM_ID_SHIFT_ = 8,
238 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
241 } // namespace SendMsg
243 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
245 enum Id { // HwRegCode, (6) [5:0]
247 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
255 ID_SYMBOLIC_LAST_ = 8,
259 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
262 enum Offset { // Offset, (5) [10:6]
266 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
268 OFFSET_SRC_SHARED_BASE = 16,
269 OFFSET_SRC_PRIVATE_BASE = 0
272 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
273 WIDTH_M1_DEFAULT_ = 31,
274 WIDTH_M1_SHIFT_ = 11,
276 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
278 WIDTH_M1_SRC_SHARED_BASE = 15,
279 WIDTH_M1_SRC_PRIVATE_BASE = 15
284 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
286 enum Id { // id of symbolic names
296 // swizzle mode encodings
298 QUAD_PERM_ENC = 0x8000,
299 QUAD_PERM_ENC_MASK = 0xFF00,
301 BITMASK_PERM_ENC = 0x0000,
302 BITMASK_PERM_ENC_MASK = 0x8000,
304 // QUAD_PERM encodings
307 LANE_MAX = LANE_MASK,
311 // BITMASK_PERM encodings
314 BITMASK_MAX = BITMASK_MASK,
317 BITMASK_AND_SHIFT = 0,
318 BITMASK_OR_SHIFT = 5,
319 BITMASK_XOR_SHIFT = 10
322 } // namespace Swizzle
343 SRC_SGPR_MASK = 0x100,
344 SRC_VGPR_MASK = 0xFF,
345 VOPC_DST_VCC_MASK = 0x80,
346 VOPC_DST_SGPR_MASK = 0x7F,
355 } // namespace AMDGPU
357 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
358 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
359 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
360 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
361 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
362 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
363 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
364 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
365 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
367 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
368 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
369 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
370 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
371 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
372 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
373 #define C_00B84C_USER_SGPR 0xFFFFFFC1
374 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
375 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
376 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
377 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
378 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
379 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
380 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
381 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
382 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
383 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
384 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
385 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
386 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
387 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
388 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
389 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
390 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
391 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
393 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
394 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
395 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
397 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
398 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
399 #define C_00B84C_LDS_SIZE 0xFF007FFF
400 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
401 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
402 #define C_00B84C_EXCP_EN
404 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
405 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
407 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
408 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
409 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
410 #define C_00B848_VGPRS 0xFFFFFFC0
411 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
412 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
413 #define C_00B848_SGPRS 0xFFFFFC3F
414 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
415 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
416 #define C_00B848_PRIORITY 0xFFFFF3FF
417 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
418 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
419 #define C_00B848_FLOAT_MODE 0xFFF00FFF
420 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
421 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
422 #define C_00B848_PRIV 0xFFEFFFFF
423 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
424 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
425 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
426 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
427 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
428 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
429 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
430 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
431 #define C_00B848_IEEE_MODE 0xFF7FFFFF
434 // Helpers for setting FLOAT_MODE
435 #define FP_ROUND_ROUND_TO_NEAREST 0
436 #define FP_ROUND_ROUND_TO_INF 1
437 #define FP_ROUND_ROUND_TO_NEGINF 2
438 #define FP_ROUND_ROUND_TO_ZERO 3
440 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
442 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
443 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
445 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
446 #define FP_DENORM_FLUSH_OUT 1
447 #define FP_DENORM_FLUSH_IN 2
448 #define FP_DENORM_FLUSH_NONE 3
451 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
453 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
454 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
456 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
457 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
459 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
460 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
462 #define R_SPILLED_SGPRS 0x4
463 #define R_SPILLED_VGPRS 0x8
464 } // End namespace llvm