1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCInstrDesc.h"
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
21 // Low bits - basic encoding information.
25 // SALU instruction formats.
32 // VALU instruction formats.
37 // TODO: Should this be spilt into VOP3 a and b?
45 // Memory instruction formats.
54 // Pseudo instruction formats.
58 // High bits - other information.
59 VM_CNT = UINT64_C(1) << 32,
60 EXP_CNT = UINT64_C(1) << 33,
61 LGKM_CNT = UINT64_C(1) << 34,
63 WQM = UINT64_C(1) << 35,
64 DisableWQM = UINT64_C(1) << 36,
65 Gather4 = UINT64_C(1) << 37,
66 SOPK_ZEXT = UINT64_C(1) << 38,
67 SCALAR_STORE = UINT64_C(1) << 39,
68 FIXED_SIZE = UINT64_C(1) << 40,
69 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
70 HasFPClamp = UINT64_C(1) << 42
73 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
74 // The result is true if any of these tests are true.
76 S_NAN = 1 << 0, // Signaling NaN
77 Q_NAN = 1 << 1, // Quiet NaN
78 N_INFINITY = 1 << 2, // Negative infinity
79 N_NORMAL = 1 << 3, // Negative normal
80 N_SUBNORMAL = 1 << 4, // Negative subnormal
81 N_ZERO = 1 << 5, // Negative zero
82 P_ZERO = 1 << 6, // Positive zero
83 P_SUBNORMAL = 1 << 7, // Positive subnormal
84 P_NORMAL = 1 << 8, // Positive normal
85 P_INFINITY = 1 << 9 // Positive infinity
91 /// Operands with register or 32-bit immediate
92 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
93 OPERAND_REG_IMM_INT64,
94 OPERAND_REG_IMM_INT16,
99 /// Operands with register or inline constant
100 OPERAND_REG_INLINE_C_INT16,
101 OPERAND_REG_INLINE_C_INT32,
102 OPERAND_REG_INLINE_C_INT64,
103 OPERAND_REG_INLINE_C_FP16,
104 OPERAND_REG_INLINE_C_FP32,
105 OPERAND_REG_INLINE_C_FP64,
106 OPERAND_REG_INLINE_C_V2FP16,
107 OPERAND_REG_INLINE_C_V2INT16,
109 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
110 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
112 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
113 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16,
115 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
116 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
118 // Operand for source modifiers for VOP instructions
121 /// Operand with 32-bit immediate that uses the constant bus.
127 // Input operand modifiers bit-masks
128 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
129 namespace SISrcMods {
131 NEG = 1 << 0, // Floating-point negate modifier
132 ABS = 1 << 1, // Floating-point absolute modifier
133 SEXT = 1 << 0, // Integer sign-extend modifier
134 NEG_HI = ABS, // Floating-point negate high packed component modifier.
140 namespace SIOutMods {
149 namespace VGPRIndexMode {
151 SRC0_ENABLE = 1 << 0,
152 SRC1_ENABLE = 1 << 1,
153 SRC2_ENABLE = 1 << 2,
158 namespace AMDGPUAsmVariants {
168 namespace EncValues { // Encoding values of enum9/8/7 operands
175 INLINE_INTEGER_C_MIN = 128,
176 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
177 INLINE_INTEGER_C_MAX = 208,
178 INLINE_FLOATING_C_MIN = 240,
179 INLINE_FLOATING_C_MAX = 248,
185 } // namespace EncValues
186 } // namespace AMDGPU
189 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
191 enum Id { // Message ID, width(4) [3:0].
197 ID_GAPS_LAST_, // Indicate that sequence has gaps.
198 ID_GAPS_FIRST_ = ID_INTERRUPT,
201 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
204 enum Op { // Both GS and SYS operation IDs.
213 OP_GS_FIRST_ = OP_GS_NOP,
215 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
217 OP_SYS_ECC_ERR_INTERRUPT = 1,
219 OP_SYS_HOST_TRAP_ACK,
222 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
224 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
227 enum StreamId { // Stream ID, (2) [9:8].
228 STREAM_ID_DEFAULT_ = 0,
230 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
231 STREAM_ID_SHIFT_ = 8,
233 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
236 } // namespace SendMsg
238 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
240 enum Id { // HwRegCode, (6) [5:0]
242 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
250 ID_SYMBOLIC_LAST_ = 8,
254 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
257 enum Offset { // Offset, (5) [10:6]
261 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
263 OFFSET_SRC_SHARED_BASE = 16,
264 OFFSET_SRC_PRIVATE_BASE = 0
267 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
268 WIDTH_M1_DEFAULT_ = 31,
269 WIDTH_M1_SHIFT_ = 11,
271 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
273 WIDTH_M1_SRC_SHARED_BASE = 15,
274 WIDTH_M1_SRC_PRIVATE_BASE = 15
298 } // namespace AMDGPU
300 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
301 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
302 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
303 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
304 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
305 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
306 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
307 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
308 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
310 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
311 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
312 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
313 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
314 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
315 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
316 #define C_00B84C_USER_SGPR 0xFFFFFFC1
317 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
318 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
319 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
320 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
321 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
322 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
323 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
324 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
325 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
326 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
327 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
328 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
329 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
330 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
331 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
332 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
333 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
334 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
336 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
337 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
338 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
340 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
341 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
342 #define C_00B84C_LDS_SIZE 0xFF007FFF
343 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
344 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
345 #define C_00B84C_EXCP_EN
347 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
348 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
350 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
351 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
352 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
353 #define C_00B848_VGPRS 0xFFFFFFC0
354 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
355 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
356 #define C_00B848_SGPRS 0xFFFFFC3F
357 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
358 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
359 #define C_00B848_PRIORITY 0xFFFFF3FF
360 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
361 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
362 #define C_00B848_FLOAT_MODE 0xFFF00FFF
363 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
364 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
365 #define C_00B848_PRIV 0xFFEFFFFF
366 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
367 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
368 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
369 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
370 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
371 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
372 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
373 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
374 #define C_00B848_IEEE_MODE 0xFF7FFFFF
377 // Helpers for setting FLOAT_MODE
378 #define FP_ROUND_ROUND_TO_NEAREST 0
379 #define FP_ROUND_ROUND_TO_INF 1
380 #define FP_ROUND_ROUND_TO_NEGINF 2
381 #define FP_ROUND_ROUND_TO_ZERO 3
383 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
385 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
386 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
388 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
389 #define FP_DENORM_FLUSH_OUT 1
390 #define FP_DENORM_FLUSH_IN 2
391 #define FP_DENORM_FLUSH_NONE 3
394 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
396 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
397 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
399 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
400 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
402 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
403 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
405 #define R_SPILLED_SGPRS 0x4
406 #define R_SPILLED_VGPRS 0x8
407 } // End namespace llvm